A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
|
1. A semiconductor device comprising:
a plurality of volatile memory cells;
peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during a first operating mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a second operating mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the first operating mode; and
a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during the second operating mode;
wherein the peripheral circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.
12. A semiconductor device comprising:
a plurality of volatile memory cells;
peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during an active mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a standby mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the active mode; and
a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply the standby mode;
wherein the peripheral circuitry comprises a sense amplifier;
wherein the peripheral circuit circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.
17. A method for making a semiconductor device comprising:
forming a plurality of volatile memory cells;
forming peripheral circuitry coupled to the plurality of volatile memory cells and comprising a plurality of low threshold voltage (Vt) transistors configured to provide high speed operation during a first operating mode and a plurality of high Vt transistors configured as headers to reduce leakage in the low Vt transistors during a second operating mode, the high Vt and low Vt transistors each comprising a superlattice, the superlattice comprising a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions;
forming a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during the first operating mode; and
forming a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a the second operating mode;
wherein the peripheral circuitry is operable at a first clock rate during the first operating mode and a second clock rate lower than the first clock rate during the second operating mode, and wherein data stored in the plurality of volatile memory cells is fully refreshed during the second operating mode.
2. The semiconductor device of
3. The semiconductor device of
4. The semiconductor device of
5. The semiconductor device of
6. The semiconductor device of
7. The semiconductor device of
10. The semiconductor device of
11. The semiconductor device of
13. The semiconductor device of
14. The semiconductor device of
15. The semiconductor device of
16. The semiconductor device of
18. The method of
20. The method of
21. The method of
22. The method of
23. The method of
|
The present application claims the benefit of provisional application nos. 62/334,741 filed May 11, 2016; 62/375,972 filed Aug. 17, 2016; and 62/381,207 filed Aug. 30, 2016, all of which are hereby incorporated herein in their entireties by reference.
The present disclosure generally relates to semiconductor devices and, more particularly, to semiconductor memory devices and related methods.
One important requirement for DRAM (Dynamic Random Access Memory) devices is the ability to hold data in an inactive state with the minimum power drain. This power drain comes from the need to refresh the data stored in bit cells in selected portions of the memory, as well as leakage in the rest of the periphery. This specification is referred to as IDD6. This directly affects the usable time from a battery charge for smart phones, laptops, etc. Another important parameter for DRAM devices is latency. Latency is the delay between selecting a random location within the memory device and the arrival of the selected data on the outputs.
One particularly advantageous memory device is set forth in U.S. Pat. No. 7,659,539 to Kreps et al., which is assigned to the present Assignee and hereby incorporated herein in its entirety by reference. This patent discloses a semiconductor device which includes a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.
Despite the advantages of such devices, further developments in memory technology may be desired in certain applications, such as where reduced power drain and latency are desired.
A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
More particularly, in an example embodiment the first operating mode may comprise an active mode, and the second operating mode may comprise a standby mode. By way of example, the at least one peripheral circuit may comprises a sense amplifier. In accordance with another example, the at least one peripheral circuit may comprise a main wordline decoder (MWD) circuit, as well as a wordline pre-decoder circuit coupled to the MWD circuitry. In addition, the at least one peripheral circuit may comprises an address decoder circuit in another example implementation. Furthermore, the at least one peripheral circuit may include at least one transistor having a source and a drain, and the superlattice may define a channel between the source and the drain.
Furthermore, each base semiconductor portion may comprise silicon, germanium, etc., for example. Also by way of example, the at least one non-semiconductor monolayer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen. In addition, at least some semiconductor atoms from opposing base semiconductor portions of each superlattice layer may be chemically bound together through the non-semiconductor layer therebetween.
A related method for making a semiconductor device is also provided. The method may include forming a plurality of memory cells, and forming at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice, as discussed briefly above. The method may also include forming a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and forming a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.
MST technology for CMOS devices from Atomera Technologies, Inc., which is described further below with reference to
During IDD6 standby where the data in the array is continually refreshed, however, it is not necessary to operate at the same speed as during the faster active mode made possible by the use of MST technology. The specification for the time a bit cell can reliably store the data is easily long enough for the entire array to be fully refreshed at the current performance levels of the Row Activation circuitry. As a result, this creates an opportunity to operate the Row activation path of the circuit at a significantly lower voltage, while maintaining the clock rate at current levels (as opposed to the faster levels made possible by overdriven MST technology). By reducing the VDD applied to these circuits from 1.0V to 0.7V, for example, the array can be fully refreshed at current speeds, thus allowing this portion of the standby power to be reduced by approximately 50%, as will be discussed further below. The present invention describes a modification to the typical DRAM architecture that allows such a power reduction during IDD6 standby mode.
A further characteristic of MST technology is that high Vt and low Vt devices may each be optimized separately on the same chip. By optimizing the high Vt devices for minimal leakage, they may be used as headers for reducing leakage in the rest of the periphery during standby mode, while allowing optimization of the low Vt devices in these paths to be even faster than the 70% improvement referred to above during active mode.
Referring initially to
Turning now to
Turning now to
The bit cells and primary sense amps (block 400) are driven by Vddbit, which is usually in the range of 0.9V to 1.0V for both active and standby modes, which is similar to the configuration of
Note also in the timing diagram of
Starting along the bottom, the 5 blocks 300, 500, 600, 700, and 800 are not needed for refresh, so by inserting a high Vt header 205 to Vdd and footer 206 to Vss for all of these blocks, the low Vt devices that make up the logic, drivers, secondary sense amps, etc., in these paths may be optimized for enhanced performance at the expense of leakage (i.e., lower Vt). The upper limit for total leakage of these low Vt devices is the point where the leakage starts to become noticeable in power during active mode. The signals that control these headers are SB (Standby) and SB_ (Standby inverted). When SB goes high (going into IDD6 standby mode) at T1, these devices are turned off, thus limiting the leakage of all these blocks to the leakage of these High Vt devices, regardless of the leakage characteristics of the Low Vt devices that make up the logic, drivers, secondary sense amps, etc., in these paths.
The functionality of these headers is now described in greater detail with respect to
In order for the NOR gate 611 example as shown to be put into a known state during standby, the NMOS devices may be hooked to Vss. Yet, the top PMOS device is hooked to Vvdd (Virtual Vdd) so that its leakage is determined by the high Vt header 205 rather than the low Vt (higher performance) devices in the NOR gate. For this example, the NOR gate 611 drives 3 inverters in succession. This illustrates the connection of VVdd and Vvss to the source nodes of these circuits. Since NOR gate 611 output 650 is held at ground (with now a very low leakage path to Vdd through the header), the next stage should be connected in an opposite fashion. Now the NMOS device 613 is connected through a low leakage high Vt footer to ground, and the PMOS pullup 612 is connected directly to Vdd, since it is being driven by a low level from the NOR gate 611 in standby mode (after T1 on
There are certain operating considerations for the level shifter. First, under all conditions (particularly strong P, weak N, and 0.7V on Vddsw), the output node 103 should be pulled well enough below the input trip point of inverter 185 so that the output of the inverter (node 104) reaches the full CMOS level (1.5V). Thus, the drive strength of the p-channel pullup network in the level shifter 175 may be significantly less than the drive strength of the NMOS pulldown network. Yet, this creates a situation where the high-going slew rate of node 103 when the input transitions to ground is extremely slow (see the box 90 in the timing diagram in
For the architecture described in the example embodiments, this slow rise time of node 103 when de-selecting the SWL is somewhat acceptable during standby, since we are slowing down the Refresh cycle time (compared to the active cycle time) by operating the peripheral circuitry at 0.7V, while maintaining Vddh in the array. Thus, the speed of operation for reading the contents of the bit cells to the primary sense amplifiers is the same. Yet, during active operation (which will be 70% faster than existing designs once MST technology is enabled), the duty cycle of the SWL selection should be relatively close to 50% to handle the much faster frequencies enabled by MST technology during active mode.
In addition, the PI includes two additional PMOS devices in series (P146 and 151). They are only enabled during active mode (SB on the gate of PMOS 151 goes low) to make the rise time faster during active mode. When the input node 101 is high (1.0V), the high Vt PMOS devices 145 and 146 are just at Vtp, and draw almost no current. Therefore PMOS 146 and 151 may be as large as is practical in the area available. When the input 101 falls to 0, PMOS 145 (whose size was determined by the ratio in standby mode) is turned on in parallel to PMOS devices 146 and 151 in series, making the rise time of node 103 extremely fast.
Turning to
Referring additionally to the graph 250 of
The power savings which may be achieved using the above-described approach will be further understood with reference to an example implementation using IDD specifications for a Micron Dual-Channel LPDDR3 SDRAM (although the techniques described herein may be used with other types of DRAM devices). For active read and write modes (no row activation), power is almost entirely in Vdd2 (1.2V for LPDDR3, 1.1V for LPDDR4). That is, it is in the read and write paths, not Vddbit. Upon activation, power is in Vdd1 (1.8V) and Vdd2 (1.2V). Vdd2 still dominates, but not as much. Vddbit is regulated from the lower Vdd2 voltage. During an all bank auto-refresh burst current, power is in Vdd1 (1.8V) and Vdd2 (1.2V). Since multiple banks are being refreshed at the same time, this is more or less a scaled up version of the “activate” power numbers. However, during standby (IDD6), power is in Vdd1 and Vdd2 and Vdd2 is still very dominant with bit CV2f being the biggest component. Applicant theorizes, without wishing to be bound thereto, that Vddbit comes from Vdd2. The ratio of Idd2 vs Idd1 is 7:1 as additional portions of the array are refreshed, vs. about 5:1 in the Activate and burst refresh cases. Note also that for the above-noted LPDDR3 device, not all portions of the array are refreshed in every mode. If Vdd reduction or performance improvements are not required, then gains provided through incorporation of MST may be translated to area reduction. More particularly, the gains in Ieff/Ioff may be converted into reducing the sizes of devices in parts of the circuit where the area impact is significant, keeping the same or slightly better performance in those areas.
Turning additionally to the example DRAM architecture 30 of
With respect to the first example shown in
With respect to the second example shown in
For an activate mode, Vdd1 (1.8V)=8 mA. If Vddbit is reduced by 100 mV, Vdd1 may be able to be reduced by an additional 100 mV due to improved Vt variation of the pass gate with MST. As a result, the total savings would be (1-1.62/1.82)*100=21%. Furthermore, where Vddca+Vddq=6 mA, if Vddq may not be reduced, it may be possible to reduce Vddca (Command/Address buss) by 50%. For Vdd2 (1.2V)=41.5 mA, the percentage of Power in Vdd 2=41.5/(41.5+8+6)=75%. The percentage of this power that is attributable to Vddbit is nearly 100% due to the dominance of bit line capacitance (approximately 80ff per bit line). The front end path to word line may be no more than 2-3 pf vs. 100's of pF for bit lines Also, since Vdd2 is dominated by Vddbit, the savings is app. (1-1.12/1.22)*100=16%, where 92% of 1.2 is 1.104. As such, the percentage of power saved=15-20% for LPDDR designs, where standby is very important.
For an all bank auto refresh burst mode where Vdd1 (1.8V)=30 mA, if Vddbit is reduced by 100 mV, Vdd1 may be able to be reduced by an additional 100 mV due to improved Vt variation of a pass gate with a MST superlattice. Total savings may be (1-1.62/1.82)*100=21%. For Vddca+Vddq=6 mA, if Vddq may not be reduced, Vddca (commend/Address buss) may still be reduced by approximately 50%. For Vdd2 (1.2V)=150 mA, the percentage of power in Vdd2=150/(150+30+6)=80%. Moreover, the percentage of this power that is Vddbit is nearly 100% due to dominance of bit line capacitance (approximately 80ff per bit line). The front end path to the wordline may be no more than 2-3 pf vs. 100's of pF for bit lines. Since Vdd2 is dominated by Vddbit, the savings is approximately (1-1.12/1.22)*100=16%, where 92% of 1.2 is 1.104. The percentage of power saved=15-20% for LPDDR designs, where standby is more important. With respect to the above-described approach of further reduction of Vddbit for servers (DDR designs), this would increase refresh current due to more frequent refreshes required.
Turning again to the example of
To summarize, for computationally-intensive applications where caching is effective, the estimated savings would be approximately 50%. That is, these are situations dominated by read and write operations without the need to activate the word lines very often. For refresh modes, the savings may be approximately 15-20%. This is based upon the amount of offset improvement that may be achieved in the primary sense amps, for example. Increasing the improvement in Vt variation from 40% to 60% may further increase this number to 25-30%. Moreover, reducing Vddbit may not necessarily help Idd6 since the higher necessary frequency of refresh operations may offset the CV2f savings on the bit lines.
For server farms, the percentage of activate operations vs. read or write operations may be higher due to the fully random nature of the packets. This is where reducing Vddbit may be beneficial, since the percentage of time spent in refresh is very low.
A description of the above-noted MST technology which may be used in DRAM memory cells in accordance with the present application is now provided. Generally speaking, the MST technology relates to advanced semiconductor materials such as the superlattice 25 described further below. Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicant's use a “conductivity reciprocal effective mass tensor”, Me−1 and Mh−1 for electrons and holes respectively, defined as:
for electrons and:
for holes, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
Applicant's definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.
Referring now to
Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. The energy band-modifying layers 50 are indicated by stippling in
The energy band-modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By “constrained within a crystal lattice of adjacent base semiconductor portions” it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer 50 therebetween, as seen in
In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
Applicant theorizes without wishing to be bound thereto that energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.
Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.
It is also theorized that semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.
The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n. The cap layer 52 may comprise a plurality of base semiconductor monolayers 46. The cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.
Each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example
It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram of
In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.
Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.
It is theorized without Applicant wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown in
While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.
The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
Indeed, referring now additionally to
In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
In
It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicant to further theorize that the 5/1/3/1 superlattice 25′ should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.
Further details regarding the implementation of MST technology in a semiconductor memory device may be found in the above-noted U.S. Pat. No. 7,659,539 to Kreps et al., for example.
Many modifications and other embodiments will come to the mind of one skilled in the art having the benefit of the teachings presented herein. Therefore, it is understood that the disclosure is not to be limited to the specific exemplary embodiments disclosed herein.
Patent | Priority | Assignee | Title |
10580866, | Nov 16 2018 | ATOMERA INCORPORATED | Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance |
10580867, | Nov 16 2018 | ATOMERA INCORPORATED | FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance |
10593761, | Nov 16 2018 | ATOMERA INCORPORATED | Method for making a semiconductor device having reduced contact resistance |
10763370, | Apr 12 2018 | ATOMERA INCORPORATED | Inverted T channel field effect transistor (ITFET) including a superlattice |
10777451, | Mar 08 2018 | ATOMERA INCORPORATED | Semiconductor device including enhanced contact structures having a superlattice |
10818755, | Nov 16 2018 | ATOMERA INCORPORATED | Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance |
10825901, | Jul 17 2019 | ATOMERA INCORPORATED | Semiconductor devices including hyper-abrupt junction region including a superlattice |
10825902, | Jul 17 2019 | ATOMERA INCORPORATED | Varactor with hyper-abrupt junction region including spaced-apart superlattices |
10840335, | Nov 16 2018 | ATOMERA INCORPORATED | Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance |
10840336, | Nov 16 2018 | ATOMERA INCORPORATED | Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods |
10840337, | Nov 16 2018 | ATOMERA INCORPORATED | Method for making a FINFET having reduced contact resistance |
10840388, | Jul 17 2019 | ATOMERA INCORPORATED | Varactor with hyper-abrupt junction region including a superlattice |
10847618, | Nov 16 2018 | ATOMERA INCORPORATED | Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance |
10854717, | Nov 16 2018 | ATOMERA INCORPORATED | Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance |
10868120, | Jul 17 2019 | ATOMERA INCORPORATED | Method for making a varactor with hyper-abrupt junction region including a superlattice |
10879356, | Mar 08 2018 | ATOMERA INCORPORATED | Method for making a semiconductor device including enhanced contact structures having a superlattice |
10879357, | Jul 17 2019 | ATOMERA INCORPORATED | Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice |
10884185, | Apr 12 2018 | ATOMERA INCORPORATED | Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice |
10937868, | Jul 17 2019 | ATOMERA INCORPORATED | Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices |
10937888, | Jul 17 2019 | ATOMERA INCORPORATED | Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices |
11075078, | Mar 06 2020 | ATOMERA INCORPORATED | Method for making a semiconductor device including a superlattice within a recessed etch |
11094818, | Apr 23 2019 | ATOMERA INCORPORATED | Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods |
11177351, | Feb 26 2020 | ATOMERA INCORPORATED | Semiconductor device including a superlattice with different non-semiconductor material monolayers |
11183565, | Jul 17 2019 | ATOMERA INCORPORATED | Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods |
11302823, | Feb 26 2020 | ATOMERA INCORPORATED | Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers |
11329154, | Apr 23 2019 | ATOMERA INCORPORATED | Semiconductor device including a superlattice and an asymmetric channel and related methods |
11355667, | Apr 12 2018 | ATOMERA INCORPORATED | Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice |
11387325, | Mar 08 2018 | ATOMERA INCORPORATED | Vertical semiconductor device with enhanced contact structure and associated methods |
11417370, | Aug 12 2020 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device |
11437486, | Jan 14 2020 | ATOMERA INCORPORATED | Methods for making bipolar junction transistors including emitter-base and base-collector superlattices |
11437487, | Jan 14 2020 | ATOMERA INCORPORATED | Bipolar junction transistors including emitter-base and base-collector superlattices |
11469302, | Jun 11 2020 | ATOMERA INCORPORATED | Semiconductor device including a superlattice and providing reduced gate leakage |
11569368, | Jun 11 2020 | ATOMERA INCORPORATED | Method for making semiconductor device including a superlattice and providing reduced gate leakage |
11631584, | Oct 28 2021 | ATOMERA INCORPORATED | Method for making semiconductor device with selective etching of superlattice to define etch stop layer |
11664427, | Mar 08 2018 | ATOMERA INCORPORATED | Vertical semiconductor device with enhanced contact structure and associated methods |
11664459, | Apr 12 2018 | ATOMERA INCORPORATED | Method for making an inverted T channel field effect transistor (ITFET) including a superlattice |
11682712, | May 26 2021 | ATOMERA INCORPORATED | Method for making semiconductor device including superlattice with O18 enriched monolayers |
11721546, | Oct 28 2021 | ATOMERA INCORPORATED | Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms |
11728385, | May 26 2021 | ATOMERA INCORPORATED | Semiconductor device including superlattice with O18 enriched monolayers |
11742202, | Mar 03 2021 | ATOMERA INCORPORATED | Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlattice |
11790958, | Aug 12 2020 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device |
11810784, | Apr 21 2021 | ATOMERA INCORPORATED | Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer |
11837634, | Jul 02 2020 | ATOMERA INCORPORATED | Semiconductor device including superlattice with oxygen and carbon monolayers |
11848356, | Jul 02 2020 | ATOMERA INCORPORATED | Method for making semiconductor device including superlattice with oxygen and carbon monolayers |
11869968, | Apr 23 2019 | ATOMERA INCORPORATED | Semiconductor device including a superlattice and an asymmetric channel and related methods |
11923418, | Apr 21 2021 | ATOMERA INCORPORATED | Semiconductor device including a superlattice and enriched silicon 28 epitaxial layer |
11923431, | Jan 14 2020 | ATOMERA INCORPORATED | Bipolar junction transistors including emitter-base and base-collector superlattices |
11935940, | Jan 14 2020 | ATOMERA INCORPORATED | Methods for making bipolar junction transistors including emitter-base and base-collector superlattices |
11978771, | Jul 02 2020 | ATOMERA INCORPORATED | Gate-all-around (GAA) device including a superlattice |
12119380, | Jul 02 2020 | ATOMERA INCORPORATED | Method for making semiconductor device including superlattice with oxygen and carbon monolayers |
12142641, | Jul 02 2020 | ATOMERA INCORPORATED | Method for making gate-all-around (GAA) device including a superlattice |
12142662, | Mar 24 2023 | ATOMERA INCORPORATED | Method for making nanostructure transistors with offset source/drain dopant blocking structures including a superlattice |
12142669, | Mar 24 2023 | ATOMERA INCORPORATED | Method for making nanostructure transistors with flush source/drain dopant blocking structures including a superlattice |
ER2052, | |||
ER471, | |||
ER621, |
Patent | Priority | Assignee | Title |
4937204, | Mar 15 1985 | Sony Corporation | Method of making a superlattice heterojunction bipolar device |
5216262, | Mar 02 1992 | TWK TECHNOLOGIES, INC | Quantum well structures useful for semiconductor devices |
5357119, | Feb 19 1993 | Board of Regents of the University of California | Field effect devices having short period superlattice structures using Si and Ge |
5683934, | Sep 26 1994 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Enhanced mobility MOSFET device and method |
5796119, | Oct 29 1993 | Texas Instruments Incorporated | Silicon resonant tunneling |
6141361, | Sep 30 1994 | ATOMERA INCORPORATED | Wavelength selective filter |
6376337, | Nov 10 1997 | NANODYNAMICS, INC | Epitaxial SiOx barrier/insulation layer |
6472685, | Dec 03 1997 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
6741624, | Mar 05 1999 | ATOMERA INCORPORATED | Fabry-Perot laser with wavelength control |
6830964, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making semiconductor device including band-engineered superlattice |
6833294, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making semiconductor device including band-engineered superlattice |
6878576, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making semiconductor device including band-engineered superlattice |
6891188, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including band-engineered superlattice |
6897472, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including MOSFET having band-engineered superlattice |
6927413, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including band-engineered superlattice |
6958486, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including band-engineered superlattice |
6962018, | Apr 14 2004 | Dual fishing pole holder | |
6993222, | Mar 03 1999 | ATOMERA INCORPORATED | Optical filter device with aperiodically arranged grating elements |
7018900, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions |
7033437, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making semiconductor device including band-engineered superlattice |
7034329, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure |
7045377, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
7045813, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a superlattice with regions defining a semiconductor junction |
7071119, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure |
7105895, | Nov 09 1998 | NANODYNAMICS, INC | Epitaxial SiOx barrier/insulation layer |
7109052, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice |
7123792, | Mar 05 1999 | ATOMERA INCORPORATED | Configurable aperiodic grating device |
7148712, | Jun 24 2005 | Oxford Instruments Measurement Systems LLC | Probe for use in determining an attribute of a coating on a substrate |
7153763, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device including band-engineered superlattice using intermediate annealing |
7202494, | Jun 26 2003 | ATOMERA INCORPORATED | FINFET including a superlattice |
7227174, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
7229902, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
7265002, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel |
7279699, | Jun 26 2003 | ATOMERA INCORPORATED | Integrated circuit comprising a waveguide having an energy band engineered superlattice |
7279701, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions |
7288457, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions |
7303948, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including MOSFET having band-engineered superlattice |
7432524, | Jun 26 2003 | ATOMERA INCORPORATED | Integrated circuit comprising an active optical device having an energy band engineered superlattice |
7435988, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel |
7436026, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions |
7446002, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device comprising a superlattice dielectric interface layer |
7446334, | Jun 26 2003 | ATOMERA INCORPORATED | Electronic device comprising active optical devices with an energy band engineered superlattice |
7491587, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer |
7514328, | Jun 26 2003 | ATOMERA INCORPORATED | Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween |
7517702, | Dec 22 2005 | ATOMERA INCORPORATED | Method for making an electronic device including a poled superlattice having a net electrical dipole moment |
7531828, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions |
7531829, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance |
7531850, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a memory cell with a negative differential resistance (NDR) device |
7586116, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device having a semiconductor-on-insulator configuration and a superlattice |
7586165, | Jun 26 2003 | ATOMERA INCORPORATED | Microelectromechanical systems (MEMS) device including a superlattice |
7598515, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a strained superlattice and overlying stress layer and related methods |
7612366, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a strained superlattice layer above a stress layer |
7626767, | Aug 10 2007 | ASIA OPTICAL INTERNATIONAL LTD | Zoom lens |
7659539, | Jun 26 2003 | ATOMERA INCORPORATED | Semiconductor device including a floating gate memory cell with a superlattice channel |
7700447, | Feb 21 2006 | ATOMERA INCORPORATED | Method for making a semiconductor device comprising a lattice matching layer |
7718996, | Feb 21 2006 | ATOMERA INCORPORATED | Semiconductor device comprising a lattice matching layer |
7781827, | Jan 24 2007 | ATOMERA INCORPORATED | Semiconductor device with a vertical MOSFET including a superlattice and related methods |
7812339, | Apr 23 2007 | ATOMERA INCORPORATED | Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures |
7863066, | Feb 16 2007 | ATOMERA INCORPORATED | Method for making a multiple-wavelength opto-electronic device including a superlattice |
7880161, | Feb 16 2007 | ATOMERA INCORPORATED | Multiple-wavelength opto-electronic device including a superlattice |
7928425, | Jan 25 2007 | ATOMERA INCORPORATED | Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods |
8389974, | Feb 16 2007 | ATOMERA INCORPORATED | Multiple-wavelength opto-electronic device including a superlattice |
8811068, | May 13 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit devices and methods |
9275996, | Nov 22 2013 | ATOMERA INCORPORATED | Vertical semiconductor devices including superlattice punch through stop layer and related methods |
9406753, | Nov 22 2013 | MEARS TECHNOLOGIES, INC | Semiconductor devices including superlattice depletion layer stack and related methods |
9558939, | Jan 15 2016 | ATOMERA INCORPORATED | Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source |
9741428, | May 13 2011 | MIE FUJITSU SEMICONDUCTOR LIMITED | Integrated circuit devices and methods |
20030034529, | |||
20030057416, | |||
20060220118, | |||
20070012910, | |||
20070020833, | |||
20080012004, | |||
20080258134, | |||
20110215299, | |||
20140313819, | |||
20140325249, | |||
20150357414, | |||
20160099317, | |||
20160111495, | |||
20160149023, | |||
20160336406, | |||
20160336407, | |||
20160358773, | |||
20170169874, | |||
20170271341, | |||
20170294514, | |||
20170301757, | |||
GB2347520, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Mar 17 2017 | ROY, RICHARD STEPHEN | ATOMERA INCORPORATED | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 042464 | /0339 | |
May 11 2017 | ATOMERA INCORPORATED | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Sep 27 2018 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Apr 20 2022 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Date | Maintenance Schedule |
Oct 23 2021 | 4 years fee payment window open |
Apr 23 2022 | 6 months grace period start (w surcharge) |
Oct 23 2022 | patent expiry (for year 4) |
Oct 23 2024 | 2 years to revive unintentionally abandoned end. (for year 4) |
Oct 23 2025 | 8 years fee payment window open |
Apr 23 2026 | 6 months grace period start (w surcharge) |
Oct 23 2026 | patent expiry (for year 8) |
Oct 23 2028 | 2 years to revive unintentionally abandoned end. (for year 8) |
Oct 23 2029 | 12 years fee payment window open |
Apr 23 2030 | 6 months grace period start (w surcharge) |
Oct 23 2030 | patent expiry (for year 12) |
Oct 23 2032 | 2 years to revive unintentionally abandoned end. (for year 12) |