In one embodiment, a control circuit configured for an interleaved switching power supply, can include: (i) a feedback compensation signal generation circuit configured to sample an output voltage of the interleaved switching power supply, and to generate a feedback compensation signal; (ii) a first switch control circuit configured to compare a voltage signal indicative of an inductor current in the first voltage regulation circuit against the feedback compensation signal, and to control a first main power switch in the first voltage regulation circuit; and (iii) a second switch control circuit configured to turn on a second main power switch in the second voltage regulation circuit after half of a switching cycle after the first main power switch is turned on, and to regulate an on time of the second main power switch.
|
1. A control circuit configured for an interleaved switching power supply having first and second voltage regulation circuits coupled in parallel, the control circuit comprising:
a) a feedback compensation signal generation circuit configured to generate a feedback compensation signal based on an error between an output voltage of said interleaved switching power supply and a first reference voltage;
b) a first switch control circuit configured to compare a voltage signal indicative of an inductor current in said first voltage regulation circuit against said feedback compensation signal, to turn on a first main power switch in said first voltage regulation circuit when a valley value of said voltage signal reaches said feedback compensation signal, and then to turn off said first main power switch after a predetermined time during which a first capacitor is charged to a second reference voltage in order to control said first voltage regulation circuit to operate in a valley value current control mode with a fixed on time; and
c) a second switch control circuit configured to turn on a second main power switch in said second voltage regulation circuit after half of a switching cycle after said first main power switch is turned on, and to regulate an on time of said second main power switch in response to an error of inductor current average values of inductor currents of said first and second voltage regulation circuits in said switching cycle and a peak value of a second voltage signal indicative of a second inductor current in said second voltage regulation circuit, in order to control said second voltage regulation circuit to operate in a peak current control mode.
2. The control circuit of
a) a first comparator configured to generate a first switch on signal in response to a comparison of said voltage signal against said feedback compensation signal;
b) a first off signal generating circuit configured to operate when a control signal of said first main power switch is active, and to generate a first switch off signal to control said on time of said first main power switch to be a predetermined time; and
c) a first RS flip-flop configured to activate said control signal of said first main power switch to turn on said first main power switch when said first switch on signal is active, and to deactivate said control signal of said first main power switch to turn off said first main power switch when said first switch off signal is active.
3. The control circuit of
a) a first switch, a first current source, and a first capacitor coupled in parallel between a non-inverting input terminal of a second comparator and ground;
b) said first switch being controlled by said control signal of said first main power switch such that said first current source charges said first capacitor when said control signal of said first main power switch is active, and said first capacitor is discharged when said control signal of said first main power switch is inactive; and
c) said second comparator being configured to said first switch off signal when said voltage across said first capacitor is charged to said second reference voltage.
4. The control circuit of
a) a phase-difference control circuit configured to receive said first switch on signal, and to generate a second switch on signal after said half of said switching cycle after said first main power switch is turned on, wherein said switching cycle comprises a full switching operation of said first main power switch;
b) a second off signal generating circuit configured to compare said inductor current average values of said inductor currents of said first and second voltage regulation circuits in said switching cycle, and to regulate a generation time of said second switch off signal; and
c) a second RS flip-flop configured to generate a control signal of said second main power switch in response to said second switch on signal and said second switch off signal.
5. The control circuit of
a) a first buffer coupled to said first comparator, and to a set terminal of a third RS flip-flop, a second buffer coupled to said first buffer, and to a reset terminal of said third RS flip-flop, wherein said third RS flip-flop is configured to generate a first control signal;
b) a third buffer coupled to said first comparator, and to a reset terminal of a fourth RS flip-flop, said fourth RS flip-flop having a set terminal coupled to said first buffer, wherein said fourth RS flip-flop is configured to generate a switch control signal;
c) a fifth RS flip-flop having a set terminal coupled to said first comparator, and a reset terminal coupled to an output of a third comparator, wherein said fifth RS flip-flop is configured to generate a second control signal at a complementary output terminal;
d) a first charging circuit configured to charge a second capacitor of a first charging circuit when said first control signal is inactive;
e) a sense capacitor coupled to said third comparator and ground, wherein said second switch is coupled between said first charging circuit and said sense capacitor, said switch control signal being configured to control said second switch;
f) a second charging circuit configured to charge said third capacitor in said second charging circuit when said second control signal is inactive; and
g) said third comparator being configured to generate a second switch on signal when said voltage across said third capacitor equals a level of a voltage across said sense capacitor.
6. The control circuit of
7. The control circuit of
8. The control circuit of
a) a current balancing circuit configured to compare said inductor current average values of said inductor currents of said first and second voltage regulation circuits, and to generate a compensation voltage signal;
b) an analog adder configured to receive said feedback compensation signal and said compensation voltage signal, and to generate a compensation reference signal; and
c) a fourth comparator configured to receive a voltage signal indicative of said inductor current in said second voltage regulation circuit and said compensation reference signal, and to generate a second switch off signal.
9. The control circuit of
a) a second transconductance amplifier configured to receive said voltage signals indicative of said inductor currents in said first and second voltage regulation circuits; and
b) a second compensation capacitor coupled between an output of said second transconductance operational amplifier and ground, wherein a voltage across said second compensation capacitor is configured as said compensation voltage signal.
10. The control circuit of
a) a sampling circuit configured to sense said output voltage of said interleaved switching power supply, and to generate a voltage sense signal;
b) a first transconductance operational amplifier configured to receive said first reference voltage, and said voltage sense signal; and
c) a first compensation capacitor coupled between an output of said first transconductance operational amplifier and ground, wherein a voltage across said first compensation capacitor is configured as said feedback compensation signal.
11. The control circuit of
12. The control circuit of
13. The control circuit of
14. The control circuit of
15. The control circuit of
a) said up-clamp circuit comprises a first diode having a cathode coupled to said feedback compensation signal; and
b) said down-clamp circuit comprises a second diode having an anode coupled to said feedback compensation signal.
16. The control circuit of
a) said cathode of said first diode is directly connected to said feedback compensation signal; and
b) said anode of said second diode is directly connected to said feedback compensation signal.
17. The control circuit of
|
|||||||||||||||||||||||||||||
This application claims the benefit of Chinese Patent Application No. 201310522881.9, filed on Oct. 29, 2013, which is incorporated herein by reference in its entirety.
The present invention relates to a switch mode power supply, and more particularly to a control circuit for an interleaved switching power supply.
Switch mode power supplies can efficiently convert electrical power from a source to a load, or to several different loads, with each corresponding to a different output. The main transistor of a switching-mode supply can switch between on and off states at a given operating frequency, and voltage regulation can be achieved by varying the ratio of the on-to-off time of the main transistor. Switch mode power supplies may have relatively high power conversion efficiency, as compared to other types of power converters. Switch mode power supplies may also be substantially smaller and lighter than a linear supply due to the smaller transformer size and weight.
In one embodiment, a control circuit configured for an interleaved switching power supply, can include: (i) a feedback compensation signal generation circuit configured to sample an output voltage of the interleaved switching power supply, and to generate a feedback compensation signal; (ii) a first switch control circuit configured to compare a voltage signal indicative of an inductor current in the first voltage regulation circuit against the feedback compensation signal, and to turn on a first main power switch in the first voltage regulation circuit, and then to turn off the first main power switch after a predetermined time, in response to the voltage signal being equal to the feedback compensation signal; and (iii) a second switch control circuit configured to turn on a second main power switch in the second voltage regulation circuit after half of a switching cycle after the first main power switch is turned on, and to regulate an on time of the second main power switch in response to a comparison of inductor current average values of inductor currents of the two voltage regulation circuits in the switching cycle.
Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. For example, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.
Main circuits of a switching power supply can be coupled in an “interleaved” fashion, and in parallel to decrease the burden of the power switches, to improve the power density of the power supply, and to decrease the ripple of the output voltage of the switching power supply in order to maintain a higher quality of output voltage.
Other terminals of inductor L1 and inductor L2 can connect to each other. For example, a first terminal of free-wheeling diode D11 can connect to a second terminal of main power switch Q1. A first terminal of free-wheeling diode D12 can connect to a second terminal of main power switch Q2. The second terminals of free-wheeling diodes D11 and D12 can both connect to the negative electrode of input supply Vi. Output capacitor Co can connect to the second terminals of inductor L1 and inductor L2, and to ground. The positive electrode and negative electrode of output capacitor Co can be configured as the positive electrode and negative electrode of the output terminals of the interleaved switching power supply.
In operation of the interleaved switching power supply, the conduction phase of main power switch Q2 may lag that of main power switch Q1 by about 180°. Thus, currents iL1 and iL2 can be generated, and ripple waves of current iL1, and iL2 can be counteracted to decrease the current ripple of output current io. However, the frequency may be increased by, e.g., two times the original frequency, and the voltage ripple of output voltage Vo may also be decreased. Therefore, the values of inductor L1, inductor L2, and output capacitor Co can be decreased to improve the dynamic response. For example, each buck circuit may only afford half of the output power, and current flowing through inductors L1 and L2, and power switches Q1 and Q2 may be only half of that of regular buck circuit. Also, in high frequency working conditions, ceramic capacitors of lower equivalent resistance can be utilized as output capacitor Co to maintain the output of the switching power supply as steadier and with higher efficiency.
Phase difference control of an interleaved switching power supply can be achieved when constant frequency control is employed. For typical switching power supplies, improved dynamic response performance and simplified compensation design can be found via a constant time control mode. However, when a constant on time control mode is used in interleaved switching power supplies, interleaved parallel control of the two voltage regulators may be difficult to achieve due to the variable operation frequency.
In particular embodiments, a control circuit for an interleaved switching power supply can obtain an output voltage of the interleaved switching power supply by a feedback compensation signal generating circuit, and may output an feedback compensation signal (e.g., via calculation and compensation). A voltage signal indicative of the inductor current in a first voltage regulation circuit via a first switch control circuit can be compared against the feedback compensation signal. When the voltage signal equals a level of the feedback compensation signal, the first switch control circuit can control a first main power switch in the first voltage regulation circuit to be turned on. The first main power switch may be turned off after a predetermined time has elapsed.
After half of a switching cycle since the first main power switch is turned on, a second switch control circuit can control a second main power switch in a second voltage regulation circuit to be turned on. For example, a “switching cycle” may be a cycle corresponding to completion of an entire switching operation of the first main power switch. Also, inductor current average values of inductor currents in the two voltage regulation circuits may be compared, and when the inductor current average values are not equal, an on time of the second main power switch may be adjusted (e.g., increased or decreased), and the second main power switch may be turned off. In this way, inductor current average values may become equal to each other by regulating the on time of the second main power switch for several times (e.g., over a number of cycles). Thus, the two voltage regulation circuits may be turned on with a 180° phase-difference, and with equal on times. Accordingly, interleaved control between the two voltage regulation circuits when constant on time control is utilized in an interleaved switching power supply can be achieved, for improved dynamic response.
In one embodiment, a control circuit configured for an interleaved switching power supply, can include: (i) a feedback compensation signal generation circuit configured to sample an output voltage of the interleaved switching power supply, and to generate a feedback compensation signal; (ii) a first switch control circuit configured to compare a voltage signal indicative of an inductor current in the first voltage regulation circuit against the feedback compensation signal, and to turn on a first main power switch in the first voltage regulation circuit, and then to turn off the first main power switch after a predetermined time, in response to the voltage signal being equal to the feedback compensation signal; and (iii) a second switch control circuit configured to turn on a second main power switch in the second voltage regulation circuit after half of a switching cycle after the first main power switch is turned on, and to regulate an on time of the second main power switch in response to a comparison of inductor current average values of inductor currents of the two voltage regulation circuits in the switching cycle.
Referring now to
This example control circuit can include feedback compensation signal generation circuit 301, which can sample output voltage Vo at an output terminal of the interleaved switching power supply, in order to generate feedback compensation signal VC1 (e.g., by calculating and/or compensating). Switch control circuit 302 can receive a voltage signal (e.g., branch voltage signal ViL1) representing the inductor current of the first voltage regulator. Branch voltage signal ViL1 may be compared against feedback compensation signal VC1. When branch voltage signal ViL1 is consistent with (e.g., the same or substantially the same value as) feedback compensation signal VC1, main power switch Q1 of the first voltage regulator may be controlled to be on for a predetermined time by switch control circuit 302, and then main power switch Q1 can be turned off.
Switch control circuit 303 can control main power switch Q2 in the second voltage regulation circuit to be turned on half of a switching cycle after main switch Q1 is turned on. A switching cycle may be a time or cycle for completion of an entire switching operation of main power switch Q1. In addition, inductor current average values of the inductor currents of the two voltage regulation circuits in a switching cycle can be compared. In response, an on time of main power switch Q2 can be adjusted (e.g., increased or decreased) when these inductor current average values are not equal. Further, main power switch Q2 can be controlled to be turned off so as to match the inductor current average values with each other by repeatedly regulating the on time of main power switch Q2.
Switch control circuit 302 can include comparator A1, flip-flop RS1, and off signal generation circuit 3021. The non-inverting input terminal of comparator A1 can receive feedback compensation signal VC1, and the inverting input terminal of comparator A1 can receive branch voltage signal ViL1 of the first voltage regulation circuit. Switch on signal VS1 may be generated at the output terminals of comparator A1, and may be provided to the set terminal (S) of RS flip-flop RS1. Off signal generation circuit 3021 can receive the control signal (e.g., VQ1) of main power switch Q1. When VQ1 is active (e.g., logic high), off signal generation circuit 3021 can begin operation. After the predetermined time has elapsed, a first switch off signal may be provided to the reset terminal (R) of RS flip-flop RS1 to control the on time of main power switch Q1 to be substantially the predetermined time.
The output terminal (Q) of flip-flop RS1 can generate VQ1. When switch on signal VS1 is active, flip-flop RS1 may be set, and the control signal (e.g., VQ1) of main power switch Q1 therefrom may be activated to turn on main power switch Q1. When the first switch off signal is inactive, flip-flop RS1 may be reset, and control signal VQ1 may be inactive to turn off main power switch Q1. Further, off signal generation circuit 3021 can include comparator A2, capacitor C2, current source I1, and switch (e.g., transistor) S1. Switch S1, current source I1 and capacitor C2 can be coupled in parallel, with common notes connecting to the non-inverting input terminal of comparator A3, and to ground. Operation of switch S1 may be controlled by control signal VQ1, or an inverted version thereof. When control signal VQ1 is active, main power switch Q1 may be on, and capacitor C1 may be charged by current source I1. When control signal VQ1 is inactive, main power switch Q1 may be turned off, and the voltage across capacitor C1 may be discharged to ground.
The inverting input terminal of comparator A2 can receive reference voltage Vref2. When the voltage across capacitor C2 is charged to be consistent with (e.g., substantially a same level as) reference voltage Vref2, the first switch off signal may be activated at the output of comparator A2. For example, switch control circuit 303 can include phase-difference control circuit 3031, off signal generating circuit 3032, and RS flip-flop RS2. Phase difference control circuit 3031 can receive switch on signal VS1. When switch on signal VS1 is active, control signal VQ1 can be active, and main power switch Q1 may be turned on. A second switch on signal may be generated (e.g., and supplied to a set terminal of RS flip-flop RS2) a half switching cycle after main power switch Q1 was turned on.
Off signal generating circuit 3032 can compare inductor current average values of inductor currents iL1 and iL2 of the two voltage regulation circuits in a (e.g., in each) switching cycle, and may regulate a time for activation of the second switch off signal supplied to a reset terminal of RS flip-flop RS2 via off signal generating circuit 3032. In this way, the inductor current average values may be equal to each other after a number (e.g., several) of regulation cycles or iterations. RS flip-flop RS2 may generate a control signal of main switch Q2 (e.g., VQ2). When the second switch on signal is active, RS flip-flop RS2 may be set, and control signal VQ2 may be activated (e.g., go high) to turn on main switch Q2. When the second switch off signal is active, RS flip-flop RS2 may be reset, and control signal VQ2 may be inactive (e.g., low) to turn off main power switch Q2.
Phase-difference control circuit 3031 can include buffers B1, B2, B3, RS flip-flops RS3, RS4, RS5, charging circuits 30311 and 30312, switch S2, sense capacitor C4, and comparator A3. Buffer B1 may have an input terminal coupled to an output terminal of comparator A1, and an output terminal coupled to a set terminal of RS flip-flop RS3. Buffer B2 may have an input terminal coupled to the output terminal of buffer B1, and an output terminal coupled to a reset terminal of RS flip-flop RS3. For example, a first control signal may be generated at an output terminal of RS flip-flop RS3, to control charging circuit 30311.
Buffer B3 may have an input terminal coupled to the output terminal of comparator A1, and an output terminal coupled to a reset terminal of RS flip-flop RS4. RS flip-flop RS4 may have a set terminal coupled to the output terminal of comparator A1, and a switch control signal for switch S2 may be generated at an output terminal of RS flip-flop RS4. Buffer RS5 may have a set terminal coupled to the output terminal of comparator A1, and a reset terminal coupled to the output terminal of comparator A3. A second control signal for charging circuit 30312 may be generated at a complementary output terminal of RS flip-flop RS5.
Circuit 30311 can receive the first control signal, and when the first control signal is deactivated, capacitor C3 can be charged. For example, a charging time for charging an output voltage of capacitor C3 to a maximum output voltage via charging circuit 30311 may equal a switching cycle of main power switch Q1 Sense capacitor C4 can connect to an inverting input terminal of comparator A3, and to ground. Switch S2 can connect between an output terminal of charging circuit 30311 and sense capacitor C4. The switch control signal output from RS flip-flop RS4 can control switch S2. When the switch control signal is active, switch S2 may be on, and the voltage across sense capacitor S2 can equal a maximum output voltage of charging circuit 30311. When the switch control signal is inactive, switch S2 may be off, and the voltage across sense capacitor C4 may be maintained to be about the maximum output voltage of charging circuit 30311.
Charging circuit 30312 can receive the second control signal, and when the second control signal is deactivated, capacitor C5 can be charged. For example, maximum output voltages of charging circuits 30311 and 30312 may be equal. Also, a charging time for charging the output voltage to a level of the maximum output voltage via charging circuit 30312 may be half that of charging circuit 30311 (e.g., C3=2C5). Capacitor C5 can connect to a non-inverting input terminal of comparator A3. When the voltage across capacitor C5 equals a level of the voltage across sense capacitor C4, a second switch on signal may be activated by comparator A3. This second switch on signal can be provided to a set terminal of RS flip-flop RS2. Charging circuit 30311 can include current source I2, switch S3 and capacitor C3. Switch S3 can be controlled by the first control signal. Also, current source I2, switch S3, and capacitor C3 may be coupled in parallel between switch S2 and ground. Charging circuit 30312 can include current source I3, switch S4, and capacitor C5. Switch S4 can be controlled by the second control signal. Current source I3, switch S4, and capacitor C5 can be coupled in parallel between the non-inverting input terminal of comparator A3 and ground.
Off signal generating circuit 3032 can include current balancing circuit 30321, analog adder 202, and comparator A4. For example, current balancing circuit 30321 can compare inductor current average values of inductor currents iL1 and iL2 over a switching cycle, and may output compensation voltage signal VC6 indicative of a difference between the inductor current average values. Analog adder 202 can receive feedback compensation signal VC1 and compensation voltage signal VC6, and compensation reference signal Va generated at an output of analog adder 202 can be provided to an inverting input terminal of comparator A4. Comparator A4 may receive a voltage signal (e.g., branch voltage signal ViL2) indicative of the inductor current in the second voltage regulation circuit at a non-inverting terminal, and compensation reference signal Va at an inverting terminal. The second switch off signal may be generated at an output terminal of comparator A4, and may be provided to a reset terminal of RS flip-flop RS2.
Current balancing circuit 30321 can include transconductance operational amplifier Gm2 and compensation capacitor C6. Transconductance amplifier Gm2 may receive branch voltage signals ViL1 and ViL2, which can be indicative of the inductor currents in the first and second voltage regulation circuits. Compensation capacitor C6 can connect between an output terminal of transconductance operational amplifier Gm2 and ground, and a voltage across compensation capacitor C6 may be compensation voltage signal VC6.
Current balancing circuit 30321 also can include up-clamp and down-clamp circuits coupled to the output terminal of transconductance operational amplifier Gm2. The up-clamp and down-clamp circuits can be utilised to avoid amplitude differences between branch voltage signals ViL1 and ViL2 that may be too large for a given application. For example, the down-clamp circuit can include diode D3 and power supply V3 connected in series, and may be configured to limit the circuit voltage to be no higher than Uv3+UD3 (e.g., V3 plus a diode drop across D3). An anode of diode D3 can connect to an output terminal of transconductance operational amplifier Gm2, an anode of power supply V3 can connect to a cathode of diode D3, and a cathode of power supply V3 can connect to ground. For example, the up-clamp circuit can include diode D4 and power supply V4 connected in series, and may be configured to limit the circuit voltage to be no lower than Uv4−UD4 (e.g., V4 minus a diode drop across D4). A cathode of diode D4 may be coupled to an output terminal of transconductance operational amplifier Gm2, an anode of power supply V4 may be coupled to an anode of diode D4, and a cathode of power supply V4 can connect to ground.
Feedback compensation signal generating circuit 301 can include transconductance operational amplifier Gm1, compensation capacitor C1, sampling resistors R1 and R2. Sampling resistor R1 may be coupled to an output terminal of the interleaved switching power supply, and to an inverting input terminal of transconductance operational amplifier Gm1. Sampling resistor R2 can connect to the inverting input terminal of transconductance operational amplifier Gm1, and to ground. The non-inverting input terminal of transconductance operational amplifier Gm1 can receive reference voltage Vref1. Current output from transconductance amplifier Gm1 can be used to charge compensation capacitor C1, in order to generate feedback compensation signal VC1. For example, feedback compensation signal generating circuit 301 also can include up-clamp and down-clamp circuits coupled to the output terminal of transconductance operational amplifier Gm1 for controlling the variation range of feedback compensation signal VC1.
For example, the down-clamp circuit can include diode D1 and power supply V1 connected in series. An anode of diode D1 can connect to an output terminal of transconductance operational amplifier Gm1, an anode of power supply V1 can connect to a cathode of diode D1, and a cathode of power supply V1 can connect to ground. The down-clamp circuit may be configured to limit the circuit voltage to be no higher than Uv1+UD1. For example, the up-clamp circuit can include diode D2 and power supply V2 connected in series. A cathode of diode D2 can connect to an output terminal of transconductance operational amplifier Gm1, an anode of power supply V2 can connect to an anode of diode D2, and a cathode of power supply V2 can connect to ground. The up-clamp circuit may be configured to limit the circuit voltage to be no less than Uv2−UD2.
The interleaved switching power supply can include a first voltage regulation circuit, a second voltage regulation circuit, and output capacitor Co. The first voltage regulation circuit can include main power switch Q1, inductor L1, and free-wheeling diode D11. The second voltage regulation circuit can include main power switch Q2, inductor L2, and free-wheeling diode D12. Main power switches Q1 and Q2 can connect to a positive electrode of an input power supply, and inductors L1 and L2 can connect terminals of main power switches Q1 and Q2, and to each other. Diode D11 can connect main power switch Q1 and to the negative electrode of the input supply. Diode D12 can connect to main power switch Q2 and to the negative electrode of the input supply. Capacitor Co can connect to a common node of inductors L1 and L2, and to the negative electrode of the input supply (e.g., ground). The positive and negative electrodes of output capacitor Co may be configured as corresponding positive and negative electrodes of the interleaved switching power supply.
Feedback compensation signal generating circuit 301 can receive feedback signal Vs indicative of output voltage Vo, and may generate feedback compensation signal VC1 after being compensated by transconductance operational amplifier Gm1 and compensation capacitor C1. Comparator A1 in switch control circuit 302 may receive branch voltage signal ViL1 indicative of the inductor current of the first voltage regulation circuit, and feedback compensation signal VC1. When a valley value (e.g., a minimum or low value) of voltage signal ViL1 reaches a level of feedback compensation signal VC1, comparator A1 can output a high level. As a result, RS flip-flop RS1 can activate VQ1 to turn on main power switch Q1. Also, switch S1 may be controlled by an inverted version of control signal VQ1, so switch S1 may be off.
Current source I1 can charge capacitor C2, and when the voltage across capacitor C2 is charged to a level of reference voltage Vref2, comparator A2 can output a high level. As a result, RS flip-flop RS1 may be reset, and output signal VQ1 may go low to turn off main power switch Q1. Therefore, the on time of main power switch Q1 in the first voltage regulation circuit may be determined by current source I1, capacitor C2, and reference voltage Vref2. Thus, when these values are fixed, the on time of main power switch Q1 may be also fixed.
Buffers B1, B2, and B3 may be time delay circuits or buffers to guarantee that RS flip-flops can be triggered sequentially, for normal operation of switch control circuit 303. Because of the timing due to buffers B1, B2 and B3, RS flip-flop RS5 can be controlled initially, followed by RS flip-flop RS4, and then by RS flip-flop RS3. When main power switch Q1 is turned off, comparator A1 can output a low level, and RS flip-flop RS5 may provide a high level at its complementary output terminal. As a result, switch S4 may be turned on, and the voltage across capacitor C5 may be discharged to zero. RS flip-flop RS4 can output a low level, and switch S2 can be turned off as a result. RS flip-flop RS3 can output a low level to turn off switch S3, and current source I2 can charge capacitor C3 until the voltage across C3 reaches a maximum output voltage. For example, the maximum output voltage may be in direct proportion with the switching cycle, and the charging time via charging circuit 30311 may equal a switching cycle of main power switch Q1.
When charging is completed, main power switch Q1 may be turned on, comparator A1 can output a high level, RS flip-flop RS4 can output a high level, and switch S2 may be turned on. The maximum output voltage of capacitor C3 may be sampled by sense capacitor C4, and then switch S2 may be turned off. This voltage across sense capacitor C4 may be maintained by sense capacitor C4. RS flip-flop RS5 can output a low level at its complementary output terminal, switch S4 may be turned off, and current source I3 may charge capacitor C5. For example, if C3=2C5 or I2=2I3, the speed of voltage increase across capacitor C5 may be two times of that of capacitor C3.
Also, the maximum output voltage of capacitor C5 can be equal to that of capacitor C3, thus a half switching cycle after main power switch Q1 is turned on, the maximum output voltage of capacitor C5 may equal the voltage across sense capacitor C4, comparator A3 may output high level, signal VQ2 from RS flip-flop RS2 may go high, and main power switch Q2 may be turned on. Therefore, the turning on time of main power switch Q2 may be a half switching cycle that lags that of main power switch Q1. In other words, the phase-difference between the turn on times of main power switches Q1 and Q2 may be 180°, to realize interleaved control of the two voltage regulation circuits.
Current balancing circuit 30321 can receive branch voltage signals ViL1 and ViL2, and may generate a current signal indicative of a difference between averages of iL1 and iL2 in a switching cycle. The current signal generated by transconductance amplifier Gm2 may charge compensation capacitor C6 to obtain compensation voltage signal VC6. In a switching cycle, when the average value of iL1 is greater than that of iL2, compensation voltage signal VC6 from Gm2 can increase, thus compensation reference voltage Va can increase, and comparator A4 can output a low level. Main power switch Q2 can remain on, and a peak value of branch voltage signal ViL2 with reference to compensation reference voltage Va may also increase. When ViL2 increases to Va, the output of comparator A4 may go high, and main power switch Q2 may be turned off. When the circuit is stable after closed-loop regulation, average values of inductor currents iL1 and iL2 may be equal, and as a result, the on times of the two voltage regulation circuits may also be equal.
Similarly, in a switching cycle, when the average value of iL1 is less than that of iL2, compensation voltage signal VC6 obtained via Gm2 may decrease. As a result, compensation reference voltage Va may decrease, and a peak value of branch voltage signal ViL2 with reference to compensation reference voltage Va may be reached in advance. Thus, an average value of iL2 may be reduced, and when ViL2 reaches Va, the output of comparator A4 can high, resulting in main power switch Q2 being turned off. When the circuit is stable after closed-loop regulation, average values of inductor currents iL1 and iL2 may be equal, and as a result, the on times of the two voltage regulation circuits may also be equal.
In this fashion, the first voltage regulation circuit may operate in a valley value current control mode with a fixed on time, and the second voltage regulation circuit may operate in a peak current control mode. The on time of the second voltage regulation circuit may be determined by the first voltage regulation circuit, with its phase lagging by 180° to that of the first voltage regulation circuit when main power switch Q1 is turned on. However, as the on time of main switch Q2 in the second voltage regulation circuit may be not fixed, during a dynamic procedure, the two voltage regulation circuit may operate together to achieve current balancing, resulting in improved dynamic response relative to such voltage regulation circuits having fixed on times.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
| Patent | Priority | Assignee | Title |
| 10566900, | May 15 2017 | Silergy Semiconductor Technology (Hangzhou) LTD | Detection method, detection circuit, controller and switching power supply |
| 10886845, | May 15 2017 | Silergy Semiconductor Technology (Hangzhou) LTD | Detection method, detection circuit, controller and switching power supply |
| 11350502, | Sep 30 2019 | Silergy Semiconductor Technology (Hangzhou) LTD | Control circuit, control method and power converter |
| 11622430, | Sep 30 2019 | Silergy Semiconductor Technology (Hangzhou) LTD | Control circuit, control method and power converter |
| Patent | Priority | Assignee | Title |
| 7012411, | Mar 29 2004 | MONTEREY RESEARCH, LLC | Switching regulator control circuit, switching regulator and switching regulator control method |
| 7764054, | May 21 2008 | Semiconductor Components Industries, LLC | Voltage regulator with current-mode dual-edge width modulation and non-linear control |
| 8587968, | Oct 23 2009 | BCD SHANGHAI MICRO-ELECTRONICS COMPANY LIMITED | Control circuits and methods for switching mode power supplies |
| 8729819, | Feb 15 2012 | SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD. | Multi-output current-balancing circuit |
| 20020125869, | |||
| 20070013356, | |||
| 20080049478, | |||
| 20090115383, | |||
| 20130148387, | |||
| 20150067358, | |||
| CN101217255, | |||
| CN102707757, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Oct 20 2014 | YU, FENG | SILERGY SEMICONDUCTOR TECHNOLOGY HANGZHOU LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 034052 | /0744 | |
| Oct 22 2014 | ZHAO, CHEN | SILERGY SEMICONDUCTOR TECHNOLOGY HANGZHOU LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 034052 | /0744 | |
| Oct 28 2014 | Silergy Semiconductor Technology (Hangzhou) LTD | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Sep 18 2018 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
| Apr 04 2022 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Date | Maintenance Schedule |
| Oct 23 2021 | 4 years fee payment window open |
| Apr 23 2022 | 6 months grace period start (w surcharge) |
| Oct 23 2022 | patent expiry (for year 4) |
| Oct 23 2024 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Oct 23 2025 | 8 years fee payment window open |
| Apr 23 2026 | 6 months grace period start (w surcharge) |
| Oct 23 2026 | patent expiry (for year 8) |
| Oct 23 2028 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Oct 23 2029 | 12 years fee payment window open |
| Apr 23 2030 | 6 months grace period start (w surcharge) |
| Oct 23 2030 | patent expiry (for year 12) |
| Oct 23 2032 | 2 years to revive unintentionally abandoned end. (for year 12) |