A line ripple compensation technique is provided for a switching power converter operating in both a pulse frequency mode of operation and a pulse width modulation mode of operation.
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1. A controller for a switching power converter, comprising:
a peak voltage compensation circuit configured to determine a peak voltage adjustment factor responsive to a function of a difference between a desired switching period for a power switch and an actual switching period for the power switch, a desired peak voltage, and the desired switching period; and
a constant voltage control circuit including an adder configured to add the desired peak voltage with the peak voltage adjustment factor to provide a compensated peak voltage, wherein the constant voltage control circuit is further configured to command the power switch to be cycled off in a current cycle of the power switch responsive to a sense voltage equaling the compensated peak voltage.
9. A method, comprising:
while operating a power switch of a switching power converter in a pulse frequency modulation (pfm) mode of operation, determining a desired pfm switching period for a current cycle of a power switch responsive to feedback voltage from a load;
determining a difference between the desired pfm switching period and an actual switching period used for a preceding cycle of the power switch;
determining a peak voltage adjustment factor based upon a function of the difference, a desired peak voltage, and the desired pfm switching period;
adding the peak voltage adjustment factor to the desired peak voltage to provide a compensated peak voltage; and
switching off the power switch in the current cycle responsive to a sense resistor voltage equaling the compensated peak voltage.
15. A method, comprising:
while operating a power switch of a switching power converter in a pulse width modulation (PWM) mode of operation, determining a desired peak voltage for a current cycle of a power switch responsive to a feedback voltage from a load;
determining a difference between a desired switching period for the power switch and an actual switching period used for a preceding cycle of the power switch;
determining a peak voltage adjustment factor based upon a function of the difference, the desired peak voltage, and the desired switching period;
adding the peak voltage adjustment factor to the desired peak voltage to provide a compensated peak voltage; and
switching off the power switch in the current cycle responsive to a sense resistor voltage equaling the compensated peak voltage.
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This application generally relates to switching power converters and, more particularly, to line ripple compensation for switching power converters.
Switching power converters include a controller that controls the cycling of a power switch to regulate the delivery of power to a load. During a constant voltage control mode of operation, the controller controls the power switch cycling responsive to a feedback voltage signal derived from the output voltage delivered to a load. In a digital feedback loop, the feedback voltage signal is processed by a voltage sensing circuit including a comparator that drives a binary output signal responsive to whether the feedback signal is greater than or less than a reference voltage signal produced by a digital-to-analog converter (DAC). In an analog feedback loop, an error amplifier generates an error voltage responsive to the difference between the feedback voltage signal and the reference voltage signal.
Regardless of whether the controller has a digital or analog feedback loop, the controller determines a desired peak current for the current cycle of the power switch based upon the processing of the feedback voltage through the feedback loop. In particular, the controller monitors a sense voltage across a sense resistor in series with the power switch to determine whether the sense voltage indicates that the desired peak current has been obtained by comparing the sense voltage to a peak voltage that is proportional to the desired peak current. Once the controller determines that the sense voltage has reached the peak voltage, the controller switches off the power switch in the current power switch cycle.
The regulation of the output voltage through the cycling of the power switch according to each cycle's peak voltage determination is affected by the line voltage for the AC mains for providing the input power to the switching power converter. In particular, it is conventional for a controller to have to regulate the output voltage over a range of AC mains voltages. The particular AC line voltage depends upon country standards but is generally contained within a universal input range that covers roughly 90 VAC to 270 VAC. The AC line voltage is rectified through a diode bridge to produce a rectified input voltage having a magnitude that depends on the particular AC line voltage selected by the power utility. The rectified input voltage is smoothed through a bulk input capacitor but it is advantageous for the bulk input capacitor to be relatively small to keep manufacturing costs low, minimize harmonic distortion, and to lower the area demands on the printed circuit board on which the bulk input capacitor is mounted.
Given the small size of the bulk input capacitor, the rectified input voltage will have a sinusoidal profile that reaches a minimum value at each zero crossing for the AC line voltage. A rectified input voltage 100 is shown in
Since such low frequency line ripple in the output voltage is undesirable, it is conventional for a controller to implement line ripple compensation in which the peak voltage for each power switch cycle is adjusted. In particular, the peak voltage depends not only upon the processing of the feedback voltage through the controller's feedback loop but also upon the switching period. Although the switching period is ideally constant during high-load pulse-width-modulation (PWM) of the power switch cycling, the actual switching period used in each switching cycle may deviate from the desired switching period value. For example, the desired switching period may expire but the secondary current in the secondary winding of the transformer (or the inductor current in a non-isolated switching power converter) has not yet reduced to zero. The controller must then wait until zero conduction current is achieved before the power switch may be cycled on (in a critical discontinuous conduction mode). Similarly, the reflected voltage on the primary winding will oscillate after the secondary current has reached zero. This reflected voltage may oscillate to values during a discontinuous conduction mode that would harm the power switch if it were cycled on at such a time. It is thus conventional to switch on the power switch during valleys in the reflected voltage oscillations in a technique known as valley-mode switching. Both valley-mode switching and critical discontinuous conduction mode operation may thus result in a difference between the desired switching period and the actual switching period used in a given cycle of the power switch.
Controllers with line ripple compensation monitor the difference between the desired switching period and the actual switching period in a preceding cycle of the power switch to adjust the peak voltage for a current cycle of the power switch. But such conventional line ripple compensation is only performed during heavy-load PWM operation of the power switch. However, heavy load conditions are no longer restricted to PWM modes of operation in modern switching power converters due to the development of direct charge techniques in which the switching power converter must directly charge a battery as opposed to providing a regulated DC output voltage that is then converted through a non-isolated switching power converter (e.g., a buck converter) within a mobile device to the proper voltage and current for charging the battery. Direct charging is advantageous because the mobile device no longer needs the non-isolated switching power converter for the charging of its battery, which lowers manufacturing costs. But direct charging involves the usage of pulse frequency modulation (PFM) of the power switch cycling at relatively heavy loads such that line ripple compensation is desirable. But conventional line ripple compensation is not applicable during PFM operation.
Accordingly, there is a need in the art for controllers for switching power converters with improved line ripple compensation that is applicable to both PWM and PFM modes of operation.
To provide improved line ripple compensation and to extend its application beyond pulse width modulation operation to include pulse frequency modulation operation, a controller is provided that uses not only the difference between the actual switching period and the desired switching period but also the desired peak voltage to determine a peak voltage adjustment factor for the desired peak voltage. For example, the peak voltage adjustment factor may be proportional to a product of the difference between the actual switching period and the desired switching period with a ratio of the desired peak voltage to the desired switching period. The addition of the desired peak voltage and the resulting peak voltage adjustment factor provides a compensated peak voltage for the current switching period that provides the appropriate amount of output power to maintain a constant voltage despite the application of a heavy load during low AC line voltage conditions.
In a pulse frequency mode of operation, a control loop within the controller adjusts a desired switching period responsive to a feedback voltage from a load. As the load is increased, the controller decreases the desired switching period so that the pulse frequency is increased to provide increased power to the load. Conversely, as the load is decreased, the controller increases the desired switching period so that the pulse frequency is reduced to reduce the amount of power delivered to the load. Such adjustment of the desired switching period during pulse frequency modulation operation conventionally uses a static peak voltage. This static peak voltage is made dynamic through the line ripple compensation disclosed herein to prevent or inhibit line ripple during pulse frequency modulation operation in the presence of a relatively heavy load.
These and additional advantageous features may be better appreciated through a consideration of the following detailed description.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
During conventional PFM operation, the switching power controller adjusts the switching period to regulate the power delivered to a load. Each pulse (on-time) of the power switch is controlled by switching off the power switch in each cycle in response to a sense resistor voltage equaling a desired peak voltage. The desired peak voltage is static, it is the pulse width that is dynamic in pulse frequency modulation. This static peak voltage is made dynamic in the controller disclosed herein to provide an advantageous line ripple compensation during pulse frequency modulation as explained further herein. The resulting line ripple compensation technique is also applicable for pulse width modulation operation as well. To provide this improved line ripple compensation, the relationship between the output power and the peak voltage (V_Ipk) is exploited as follows. In particular, it can be shown that the output power (P) for a switching power converter operating in constant voltage mode (for either PFM or PWM operation) is
P=(½)*Lm(V_Ipk/Rs)2/T_Period(CV) Eq (1
where Lm is the magnetizing inductance of the primary winding (in a flyback converter) or of the inductor (in a non-isolated switching power converter), Rs is the resistance of the sense resistor, and T_Period(CV) is the desired switching period. Note that T_Period(CV) will be dynamic in a pulse frequency mode of operation whereas it will be static in a pulse width modulation mode of operation. From equation (1), the desired peak voltage V_Ipk(CV) becomes:
V_Ipk(CV)=(2*T_Period(CV)*P*Rs2/Lm)1/2 Eq (2)
which may be rephrased as:
V_Ipk(CV)=(2*P*Rs2/Lm)1/2*T_Period(CV)1/2 Eq. (3)
To determine what V_Ipk(CV) should be in a current cycle of the power switch based upon a change (ΔTp) between the actual switching period (T_Period(measured) in a preceding cycle of the power switch and the desired switching period T_Period(CV), a partial derivative ∂Vipk/∂T_Period(CV) is taken of the right side equation (3). In particular, the partial derivative leads to an expression for the peak voltage change (ΔV_Ipk) in a current cycle of the power switch as a function of the change (ΔTp) for the period in a preceding cycle of the power switch:
ΔV_Ipk(CV)=(½)*(V_Ipk(CV)/T_Period(CV))*ΔTp Eq. (4)
Since equation (4) is ultimately derived from equation (1), it may be seen that the resulting change in the peak voltage is the optimum amount to maintain a constant output voltage despite the difference in the actual switching period as compared to the desired switching period regardless of whether the controller is operating in a pulse width modulation mode of operation or in a pulse frequency modulation mode of operation.
A controller is provided that utilizes equation (4) to more carefully compensate for line ripple during PWM modes of operation and also to extend line ripple compensation to PFM modes. An example flyback converter 200 with a controller 205 configured for the line ripple compensation technique disclosed herein is shown in
Controller 205 is configured to adjust the desired peak voltage according to the line ripple compensation technique disclosed herein to determine a compensated peak voltage to be used in the current switching cycle. After switching on power switch transistor S1 in a current cycle, controller 205 monitors the sense voltage across sense resistor R_Sense to determine when a compensated peak current (I_PK) through the primary winding has been achieved responsive to the sense voltage equaling the compensated peak voltage and then switches off power switch transistor S1 accordingly. The feedback voltage V_FB used by controller 205 with regard to calculating the desired peak voltage in PWM operation (or the desired switching period in PFM operation) may be derived using an optoisolator or through primary-only sensing techniques. For illustration brevity, the feedback voltage is shown being received directly from the output voltage V_OUT produced on a secondary side flyback converter 200 including an output diode D and an output capacitor C.
Controller 200 is shown in more detail in
Regardless of the mode of operation, constant voltage control circuit 315 uses the desired peak voltage V_Ipk(CV) to control the power switch off time in the cycling of the power switch transistor. But merely using the desired peak voltage V_Ipk(CV) to control the power switch off time is subject to line ripple for low AC line voltage states such as discussed with regard to
There may be modes of operation besides the pulse width modulation mode and the pulse frequency modulation mode in which line ripple compensation is not used. Thus a multiplexer 325 can select for the peak voltage adjustment factor ΔV_Ipk or a zero depending upon if some mode of operation besides the pulse width modulation mode or the pulse frequency modulation mode is being used. In these other modes, multiplexer 325 may select for the zero value. Conversely, multiplexer 325 is controlled to select for the peak voltage adjustment factor ΔV_Ipk during either pulse width modulation operation or pulse frequency modulation operation. An adder 330 adds the desired peak voltage V_Ipk(CV) with the peak voltage adjustment factor ΔV_Ipk to produce the compensated peak voltage (V_Ipk′) that will be used in the current switching cycle.
The resulting line ripple compensation is quite advantageous as the compensation is more robust than conventional line ripple compensation techniques that merely compensate the peak voltage based upon the difference between the desired switching period and the actual switching period. Moreover, the line ripple compensation disclosed herein is applicable to both pulse width modulation and pulse frequency modulation operation. These advantages may be better appreciated with reference to the example peak voltage adjustment method shown in the flowchart of
As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
Nguyen, David, Shi, Fuqiang, Kong, Pengju, Chin, Kai-Wen
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jan 13 2017 | Dialog Semiconductor Inc. | (assignment on the face of the patent) | / | |||
| Apr 03 2017 | CHIN, KAI-WEN | DIALOG SEMICONDUCTOR INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041939 | /0474 | |
| Apr 03 2017 | SHI, FUQIANG | DIALOG SEMICONDUCTOR INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041939 | /0474 | |
| Apr 03 2017 | KONG, PENGJU | DIALOG SEMICONDUCTOR INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041939 | /0474 | |
| Apr 03 2017 | NGUYEN, DAVID | DIALOG SEMICONDUCTOR INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041939 | /0474 |
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