A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).
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21. An apparatus comprising:
a pulse generator configured to, in response to a test request, generate a test pulse to a logic chain;
the logic chain comprising a plurality of logic devices, each logic device serially connected to each other and configured to transfer the test pulse sequentially through the logic chain; and
a detector configured to detect whether the test pulse is attenuated below a threshold level.
16. A method comprising:
generating, by a semiconductor chip, a test pulse;
transmitting the test pulse down a logic chain of the semiconductor chip, wherein the logic chain comprises a plurality of logic devices arranged in series;
detecting, at each logic device of the logic chain, a strength of the test pulse; and
based upon a threshold value and the strength of the test pulse, generating a detection result that indicates an inter-symbol interference (ISI) characteristic of the semiconductor chip.
1. An apparatus comprising:
a pulse generator configured to, in response to a test request, generate a test pulse to a logic chain;
the logic chain comprising a plurality of logic devices, each logic device serially connected to each other and configured to transfer the test pulse sequentially through the logic chain; and
a detector configured to detect, from at least a portion of the logic devices of the logic chain, a logic level of respective output signals from the respective logic devices, and output a detection result indicating a degree of an inter-symbol interference (ISI).
8. A system comprising:
a wafer comprising a plurality of semiconductor chips; and
a tester configured to, for each of the plurality of the semiconductor chips:
transfer a test request to the respective semiconductor chip,
receive a test response corresponding to the test request from the respective semiconductor chip, and
output a test result for the respective semiconductor chip,
wherein each of the plurality of semiconductor chips: generates a test pulse in response to the test request, and outputs a respective test response indicating an amount of inter-symbol interference (ISI) associated with the respective semiconductor chip.
2. The apparatus of
an oscillator which activates in response to the test request; and
a selector configured to select one of multiple pulses that are output from the oscillator and output the selected pulse as the test pulse.
3. The apparatus of
4. The apparatus of
5. The apparatus of
wherein each of the sub-detectors detects a level of an output of a corresponding logic device among the plurality of logic devices and outputs one of a logic high and a logic low.
6. The apparatus of
wherein each of the sub-detectors comprises a D flip-flop, and for each of the sub-detectors, an initial value of the D flip-flop is maintained or inverted in response to an output of a logic device corresponding to the sub-detector from among the plurality of logic devices.
7. The apparatus of
9. The system of
a test request generator configured to generate the test request;
an encoder configured to encode the test response received from the plurality of semiconductor chips in a test code indicating the time point when the test pulse is extinguished in each of the plurality of semiconductor chips; and
a comparator configured to compare the test code and a reference value, and output test results indicating whether any of the plurality of semiconductor chips are defective.
10. The system of
11. The system of
12. The system of
a pulse generator configured to generate a test pulse in response to a test request;
a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and
a detector configured to detect a level of an output of each of the plurality of logics and output a detection result indicating a degree of an inter-symbol interference (ISI) characteristic.
13. The system of
wherein each of the sub-detectors detects a level of an output of a corresponding logic among the plurality of logics and outputs one of a logic high and a logic low.
14. The system of
wherein each of the sub-detectors comprises a D flip-flop that maintains or inverts an initial value according to whether the D flip-flop is clocked by an output of a corresponding logic among the plurality of logics.
15. The system of
17. The method of
18. The method of
19. The method of
20. The method of
22. The apparatus of
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This application claims the benefit of Korean Patent Application No. 10-2015-0115418, filed on Aug. 17, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
The disclosed subject matter relates to a semiconductor chip capable of reducing the production cost, a test system, and a method of testing the semiconductor chip.
In manufacturing a semiconductor chip, a test of various levels regarding if the semiconductor chip satisfies a specific condition is performed for each processing stage, and the semiconductor chip that fails the test is processed as a defective chip. For example, the test such as a variation of process, voltage, and temperature (PVT) of the semiconductor chip and a degree of an inter-symbol interference (ISI) thereof, etc. may be performed. In this regard, if it is detected at an initial stage whether the semiconductor chip is defective, the production cost of the semiconductor chip may be reduced without having to add unnecessary expenses.
The disclosed subject matter provides a semiconductor chip capable of reducing the production cost, a test system, and a method of testing the semiconductor chip.
According to an aspect of the disclosed subject matter, there is provided a semiconductor chip including a pulse generator configured to generate a test pulse in response to a test request; a logic chain including a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).
According to another aspect of the disclosed subject matter, there is provided a test system including a wafer including a plurality of semiconductor chips; and a tester configured to transfer a test request to each of the plurality of semiconductor chips, receive a test response corresponding to the test request from the plurality of semiconductor chips, and output test results, wherein each of the plurality of semiconductor chips generates a test pulse in response to the test request and outputs a test response indicating a time point when the test pulse is extinguished.
According to yet another aspect of the disclosed subject matter a method may include generating, by a semiconductor chip, a test pulse. The method may include transmitting the test pulse down a logic chain of the semiconductor chip, wherein the logic chain comprises a plurality of logic devices arranged in series. The method may also include detecting, at each logic device of the logic chain, strength of the test pulse. The method may further include based upon a threshold value and the detected strength of the test pulse, generating a detection result that indicates an inter-symbol interference (ISI) characteristic of the semiconductor chip.
Exemplary embodiments of the disclosed subject matter will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Exemplary embodiments of the disclosed subject matter are provided to fully convey the disclosed subject matter to those skilled in the art. The disclosed subject matter may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. It is to be appreciated that any and all alterations, equivalents, and/or substitutes that do not depart from the spirit and technical scope of the disclosed subject matter are encompassed in the disclosed subject matter.
Like elements will be rendered the same reference numeral in regard to description of the attached drawings. In the attached drawings, dimensions of structures may be exaggerated or contracted for purposes of illustration and to clarify the understanding of the disclosed subject matter.
The terms used in the present specification are merely used to describe particular embodiments, and are not intended to limit the disclosed subject matter. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. In the present specification, it is to be understood that the terms such as “including” or “having,” etc., are intended to indicate the existence of the features disclosed in the specification, and are not intended to preclude the possibility that one or more other features may exist or may be added. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. In the present specification, terms such as ‘first’, ‘second’, etc. are used to describe various features and used only for distinguishing one feature from another, and the features are not limited by the terms. Thus, when a first feature is described as being connected or coupled to a second feature, a third feature between the first and second features is not precluded.
Unless defined differently, all terms used in the description including technical and scientific terms have the same meaning as generally understood by those skilled in the art. Terms as defined in a commonly used dictionary should be construed as having the same meaning as in an associated technical context, and unless defined apparently in the description, the terms are not ideally or excessively construed as having formal meaning.
Hereinafter, an exemplary embodiment of the present disclosed subject matter is described in detail with reference to the accompanying drawings.
The pulse generator 120 may generate a test pulse TPLS in response to a test request TREQ. The test request TREQ may be generated, applied, or output from a tester (not shown) so as to test a degree or amount of inter-symbol interference (ISI) associated with the semiconductor chip 100 on a wafer. The pulse generator 120 may generate the test pulse TPLS as a single pulse.
For example, as shown in
The pulse generator 120 may further include an element or component that performs trimming such that the test pulse TPLS has a uniform pulse width. For example, in such an embodiment, the selector 124 of the pulse generator 120 may include a plurality of delay elements (e.g., buffers, etc.) that are serially connected to each other. A resistor or a capacitor that is connected to each of the delay elements may prevent a distortion of the test pulse TPLS.
The selector 124 of the pulse generator 120 may select a plurality of pulses from the multiple pulses generated by the oscillator 122 and output those plurality of pulses as the test pulse TPLS. However, for convenience of description, unless described separately, it is assumed that the test pulse TPLS is generated as the single pulse. It is understood that such is merely one illustrative example to which the disclosed subject matter is not limited.
Returning to
For example, as shown in
As shown in
The logic chain 140 may sequentially transfer the test pulse TPLS by each of the logic devices LG1-LGn. This transmission via various logic devices may weaken the intensity of the test pulse TPLS, and thus the test pulse TPLS may gradually fade out or attenuate. In this regard, an amount of time before the test pulse TPL is extinguished may differ according to the degree of the ISI of the semiconductor chip 100. For example, if the degree of the ISI of the semiconductor chip 100 is high, a speed at which the test pulse TPL fades out may be faster, and, if the degree of the ISI of the semiconductor chip 100 is low, the speed at which the test pulse TPL fades out may be slower.
Returning to
The detector 160 may detect of levels of the outputs OUT1-OUTn of the respective logic devices LG1-LGn and output one of a logic high H or a logic low L. For example, the first sub-detector SD1 may detect the level of the output OUT1 of the first logic device LG1 and output one of the logic high H or the logic low L, and the second sub-detector SD2 may detect the level of the output OUT2 of the second logic device LG2 and output one of the logic high H or the logic low L. Likewise, a x−1th sub-detector SDx−1 may detect a level of an output OUTx−1 of the x−1th logic device LGx−1 and output one of the logic high H or the logic low L, a xth sub-detector SDx may detect a level of an output OUTx of the xth logic device LGx and output one of the logic high H or the logic low L, and an nth sub-detector SDn may detect a level of an output OUTn of the nth logic device LGn and output one of the logic high H or the logic low L. Thus, the detector 160 may output the detection result DRST with a width of n bits.
As shown in
Each of the sub-detectors SD1-SDn of
In various embodiments, the detector 160 may include a sub-detector other than the D flip-flop DF. For example, the detector 160 may include the sub-detector that is implemented as a PMOS transistor connected between a power voltage and a first node having an initial value set as the logic high H and an NMOS transistor that is connected between the first node and a ground voltage and has a corresponding output applied to a gate among the outputs OUT1-OUTn of the logics LG1˜LGn. In this case, if the output of the corresponding logic is at a level capable of gating the NMOS transistor, the NMOS transistor is turned off, and subsequently, the first node is transited to the logic low L.
The encoder END may receive a test response TRSP (or its inverse, inverse test response TRSP#) from each of the semiconductor chips 100 and encode the test response TRSP in a test code TCD. For example, the test code TCD may include the detection result DRST (of
The comparator CPM may compare the test code TCD and a reference value and generate a test result TRST. The reference value may indicate a maximum degree of the ISI that is allowable to each of the semiconductor chips 100. For example, the reference value may indicate that the test pulse TPLS needs to be transferred up to a x−1th logic LGx−1 of
The wafer WAF may include the plurality of semiconductor chips 100. The plurality of semiconductor chips 100 included in the wafer WAF may be semiconductor chips of a wafer level. The plurality of semiconductor chips 100 on one wafer WAF may perform the same function. For example, each of the plurality of semiconductor chips 100 on one wafer WAF may be a memory chip.
For example, each of the plurality of semiconductor chips 100 on one wafer WAF may be a NAND flash memory chip of a vertical structure including a plurality of blocks as shown in
The NAND strings NS11, N21, NS31 may be provided between the first bit lines BL1 and the common source line CSL. The NAND strings NS12, N22, NS32 may be provided between the second bit lines BL2 and the common source line CSL. The NAND strings NS13, N23, NS33 may be provided between the third bit lines BL3 and the common source line CSL. Each (for example, NS11) of the NAND strings NS11 through NS33 may include a string selection transistor SST, a plurality of memory cells MC1 through MC8, and a ground selection transistor GST that are serially connected to each other. For convenience of description, a NAND string may be referred to as a string below.
Strings that are commonly connected to one bit line may constitute one column. For example, the strings NS11, N21, NS31 that are commonly connected to the first bit line BL1 may correspond to a first column, the strings NS12, N22, NS32 that are commonly connected to the second bit line BL2 may correspond to a second column, and the NAND strings NS13, N23, NS33 that are commonly connected to the third bit line BL3 may correspond to a third column.
Strings that are connected to one string selection line may constitute one row. For example, the strings NS11, N12, NS13 that are connected to the first string selection line SSL1 may correspond to a first row, the strings NS21, N22, NS23 that are connected to the second string selection line SSL2 may correspond to a second row, and the NAND strings NS31, N32, NS33 that are connected to the third string selection line SSL3 may correspond to a third row.
The string selection transistor SST may be connected to the string selection lines SSL1 through SSL3. The plurality of memory cells MC1 through MC8 may be connected to the corresponding word lines WL1 through WL8. The ground selection transistor GST may be connected to the ground selection lines GSL1 through GSL3. The string selection transistor SST may be connected to the corresponding bit line BL. The ground selection transistor GST may be connected to the common source line CSL.
The word line (for example, WL1) of the same height may be commonly connected. The string selection lines SSL1 through SSL3 may be separated from each other. The ground selection lines GSL1 through GSL3 may be separated from each other. For example, when memory cells that are connected to the first word line WL1 and belong to the strings NS11, NS12, and NS13 are programmed, the first word line WL1 and the first string selection line SSL1 may be selected.
Returning to
In a semiconductor chip and a method of testing the semiconductor chip according to an exemplary embodiment, the semiconductor chip 100 may include the pulse generator 120, the logic chain 140, and the detector 160 of
A process, voltage, and temperature (PVT) variation may be tested in the same way as described above. For example, it may be determined whether the PVT variation is within an allowable range based on the time when the test result TPLS is extinguished. As described above, the inner resistance of the transistor may increase in proportion to a temperature and also increase an influence of the ISI.
The encoder END is included in the tester TST in
However, the logic chain 140 may not be separately included in the test performing area TARE for the test and, as shown in
Block 1002 illustrates that, in one embodiment, a test request signal may be received by a semiconductor chip or device, as described above. In various embodiments, the test request signal may be received from a tester, as described above.
Block 1004 illustrates that, in one embodiment, a test pulse may be generated, as described above. In various embodiments, this may include selecting a particular pulse from a series of pulses created by an oscillator, as described above.
Block 1006 illustrates that, in one embodiment, the test pulse may be transmitted down or along a logic chain, as described above. As described above, the logic chain may include a plurality of logic devices arranged in series. As the test pulse travels down the logic chain, the test pulse may be attenuated, as described above.
Block 1008 illustrates that, in one embodiment, at each logic device (e.g. the output of the logic device), the strength or voltage of the test pulse may be measured or detected, as described above. In various embodiments, this may be done via a sub-detector circuit (e.g., a D flip-flop) that compares the received output of the logic device to a threshold value.
Block 1010 illustrates that, in one embodiment, the detected values may be converted into a detection result. In one embodiment, the detection result may include a plurality of bits, each bit corresponding to a sub-detector and to a logic device, as described above. This detection result may indicate at which logic device or a time point the test pulse attenuated below the threshold.
Block 1012 illustrates that, in one embodiment, the detection result may be output as a test response to the test request. In such an embodiment, this output may be presented or transmitted to the tester device, as described above.
While the disclosed subject matter has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Jeong, Byung-hoon, Lee, Tae-Sung, Kang, Dae-Woon, Ihm, Jeong-don, Kim, Sang-Lok, Lee, Seon-Kyoo
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