A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
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1. An array of memory cells, individual of the memory cells comprising a vertical ferroelectric field effect transistor construction, the vertical field effect transistor comprising:
an isolating core;
a transition metal dichalcogenide material encircling the isolating core and having a lateral wall thickness of 1 monolayer to 7 monolayers;
a ferroelectric gate dielectric material encircling the transition metal dichalcogenide material;
conductive gate material encircling the ferroelectric gate dielectric material, the transition metal dichalcogenide material extending elevationally inward and elevationally outward of the conductive gate material; and
a conductive contact directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.
20. An array of memory cells, the memory cells comprising a vertical string of vertical ferroelectric field effect transistors, the vertical string of vertical ferroelectric field effect transistors comprising:
an isolating core;
a transition metal dichalcogenide material encircling the isolating core and having a lateral wall thickness of 1 monolayer to 7 monolayers;
a ferroelectric gate dielectric material encircling the transition metal dichalcogenide material;
alternating tiers of dielectric material and conductive gate material encircling the ferroelectric gate dielectric material, the transition metal dichalcogenide material and the ferroelectric material extending elevationally along the isolating core through the tiers, the transition metal dichalcogenide material extending elevationally beyond at least one of a) an elevationally outer of the conductive gate material tiers, and b) an elevationally inner of the conductive gate material tiers; and
a conductive contact directly against a lateral outer sidewall of the transition metal dichalcogenide material that is elevationally beyond a) the outer tier of the conductive gate material, or b) the inner tier of the conductive gate material.
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This patent resulted from a continuation application of U.S. patent application Ser. No. 15/095,211, filed Apr. 11, 2016, entitled “Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical Ferroelectric Field Effect Transistors, Vertical Strings Of Ferroelectric Field Effect Transistors, And Vertical Strings Of Laterally Opposing Pairs Of Vertical Ferroelectric Field Effect Transistors”, naming Kamal M. Karda, Chandra Mouli, and Gurtej S. Sandhu as inventors, which was a divisional application of U.S. patent application Ser. No. 13/964,309, filed Aug. 12, 2013, now U.S. Pat. No. 9,337,210, the disclosures of which are incorporated by reference.
Embodiments disclosed herein pertain to vertical ferroelectric field effect transistor constructions, to constructions comprising a pair of vertical ferroelectric field effect transistors, to vertical strings of ferroelectric field effect transistors, and to vertical strings of laterally opposing pairs of vertical ferroelectric field effect transistors.
Memory is one type of integrated circuitry, and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bit lines, data lines, sense lines, or data/sense lines) and access lines (which may also be referred to as word lines). The digit lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a digit line and an access line.
Memory cells may be volatile or non-volatile. Non-volatile memory cells can store data for extended periods of time, in many instances including when the computer is turned off. Volatile memory dissipates and therefore requires being refreshed/rewritten, in many instances multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate dielectric. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field-effect transistors may also include additional structure, for example reversibly programmable charge storage regions as part of the gate construction. Transistors other than field-effect transistors, for example bipolar transistors, may additionally or alternately be used in memory cells. Transistors may be used in many types of memory. Further, transistors may be used and formed in arrays other than memory.
One type of transistor is a ferroelectric field effect transistor (FeFET), wherein the gate dielectric is ferroelectric. The polarization of the ferroelectric, aligned by applying a programming gate voltage, modifies the conductivity of the semiconductive channel between source and drain for a selected operating gate voltage. A suitable positive programming voltage directs the polarization along the semiconducting channel. This polarization of ferroelectric results in positive sheet charge closer to the channel and negative sheet charge closer to the gate. When considering a p-type semiconductor, accumulation of electrons at the interface occurs to compensate this ferroelectric charge. A low resistivity channel is thereby created. When switching the polarization to its other stable state, the ferroelectric polarization is aligned such that negative sheet charge is closer to the channel and the electrons in the semiconductive channel close the gate dielectric get depleted. This leads to high resistivity. The preference for high and low conductance, invoked by the ferroelectric polarization state, remains after removal of the programming gate voltage (at least for a time). The status of the channel can be read by applying a small drain voltage which does not disturb the ferroelectric polarization.
However, FeFETs can uncontrollably become depolarized, and hence lose a program state. Further, very high electric fields may exist between a typical thin oxide that is between the ferroelectric dielectric material and the channel causing reliability problems in operation.
An example embodiment vertical ferroelectric field effect transistor construction is described initially with reference to
An example substrate fragment 10 comprises dielectric material 12 having various materials formed there-over which comprise a vertical ferroelectric field effect transistor construction 14 (
Any of the materials and/or structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. As used herein, “different composition” only requires those portions of two stated materials that may be directly against one another to be chemically and/or physically different, for example if such materials are not homogenous. If the two stated materials are not directly against one another, “different composition” only requires that those portions of the two stated materials that are closest to one another be chemically and/or physically different if such materials are not homogenous. In this document, a material or structure is “directly against” another when there is at least some physical touching contact of the stated materials or structures relative one another. In contrast, “over”, “on”, and “against” not preceded by “directly”, encompass “directly against” as well as construction where intervening material(s) or structure(s) result(s) in no physical touching contact of the stated materials or structures relative one another. Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.
Substrate fragment 10 may comprise a semiconductor substrate. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Transistor construction 14 comprises an isolating core 16 (i.e., electrically isolating). Material of isolating core 16 may be dielectric, including for example any of the materials described above with respect to the composition of material 12. The material of isolating core 16 may be semiconductive or conductive, and for example may provide an electrically isolating function for circuitry components above and/or below (not shown) transistor construction 14, for example being held at ground or some other potential.
A transition metal dichalcogenide material 18 encircles isolating core 16 and has a lateral wall thickness of 1 monolayer to 7 monolayers. In one embodiment, transition metal dichalcogenide material 18 is no greater than 4 monolayers in lateral wall thickness, and in one embodiment no greater than 2 monolayers in lateral wall thickness. Example materials include one or more of MoS2, WS2, InS2, MoSe2, WSe2, and InSe2. Transition metal dichalcogenide material 18 may be considered as having an elevationally outermost end surface 17 and an elevationally innermost end surface 19.
A ferroelectric gate dielectric material 20 encircles transition metal dichalcogenide material 18. In one embodiment, ferroelectric gate dielectric material 20 has a lateral wall thickness of 1 nanometer to 30 nanometers, and in one embodiment a lateral wall thickness of 2 nanometers to 10 nanometers. Example materials include HfxSiyOz and HfxZryOz.
Isolating core 16, transition metal dichalcogenide material 18, and ferroelectric gate dielectric material 20 are each shown as having a respective perimeter that is circular in horizontal cross-section. Other shapes may be used.
Conductive gate material 24 encircles ferroelectric gate dielectric material 20. Examples include one or more of elemental metal(s), an alloy of two or more elemental metals, conductive metal compounds, and conductively-doped semiconductive material. Transition metal dichalcogenide material 18 extends elevationally inward and elevationally outward of conductive gate material 24. In one embodiment, ferroelectric gate dielectric material 20 extends elevationally inward and elevationally outward of conductive gate material 24. Dielectric material 26 may be elevationally over and elevationally under conductive gate material 24. Examples include any of the materials described above with respect to the composition of material 12. Transition metal dichalcogenide material 18 may be considered as having a lateral outer sidewall 27 that is elevationally inward of conductive gate material 24 and a lateral outer sidewall 29 that is elevationally outward of conductive gate material 24.
A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.
An alternate embodiment construction is next described with reference to
A conductive contact is directly against a lateral outer sidewall of each of the transition metal dichalcogenide films that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.
Embodiments of the invention encompass a vertical string of vertical ferroelectric field effect transistors, and are next described with reference to
Alternating tiers 44 of dielectric material 46 and conductive gate material 24 encircle ferroelectric gate dielectric material 20. Example dielectrics 26 include any of the materials described above with respect to the composition of material 12. Tiers 44 may be of any selected thickness, and may be of different thicknesses. Transition metal dichalcogenide material 18 and ferroelectric gate dielectric material 20 extend elevationally along isolating core 16 though tiers 44. The transition metal dichalcogenide material extends elevationally beyond at least one of a) an elevationally outer of the conductive gate material tiers (e.g., the top-most tier 44 that comprises material 24), and b) an elevationally inner of the conductive gate material tiers (e.g., the bottom-most tier 44 that comprises material 24).
A conductive contact is directly against a lateral outer sidewall of transition metal dichalcogenide material that is elevationally beyond a) the outer tier of the conductive gate material, or b) the inner tier of the conductive gate material.
Additional example embodiments of strings of vertical ferroelectric field effect transistors are next described with reference to
Transition metal dichalcogenide films 18 extend elevationally beyond at least one of a) an elevationally outer of the laterally opposing conductive gate material tiers (e.g., the top-most tier 44e that comprises gate material 24r, 24s), and b) an elevationally inner of the laterally opposing conductive gate material tiers (e.g., the bottom-most tier 44e that comprises conductive gate material 24r, 24s). A ferroelectric gate dielectric film 20 extends through tiers 44e over each of two opposing lateral sides 35 of the individual transition metal dichalcogenide films 18 between transition metal dichalcogenide films 18 and laterally opposing conductive gate material 24r and 24s.
A conductive contact is directly against a lateral outer sidewall of a) each of the transition metal dichalcogenide films that is elevationally beyond the outer tier of the opposing conductive gate material, or b) each of the transition metal dichalcogenide films that is elevationally beyond the inner tier of the opposing conductive gate material.
Use of a vertical transition metal dichalcogenide material or film that is from 1 monolayer to 7 monolayers thick as a channel in a vertical FeFET may reduce depolarization tendency of the ferroelectric dielectric, and/or may reduce an adverse high electric field that may exist between the ferroelectric dielectric and the channel.
In some embodiments, a vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.
In some embodiments, a construction comprising a pair of vertical ferroelectric field effect transistors comprises isolating material laterally between a pair of vertical ferroelectric field effect transistors. The pair of transistors comprises a transition metal dichalcogenide film over each of two opposing lateral sides of the isolating material and individually has a lateral thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric film is laterally outward of each of the transition metal dichalcogenide films. Conductive gate material is laterally outward of each of the ferroelectric gate dielectric films. The transition metal dichalcogenide films extend elevationally inward and elevationally outward of the conductive gate material on each of the two sides. A conductive contact is directly against a lateral outer sidewall of each of the transition metal dichalcogenide films that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material.
In some embodiments, a vertical string of vertical ferroelectric field effect transistors comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Alternating tiers of dielectric material and conductive gate material encircle the ferroelectric gate dielectric material. The transition metal dichalcogenide material and the ferroelectric material extend elevationally along the isolating core through the tiers. The transition metal dichalcogenide material extends elevationally beyond at least one of a) an elevationally outer of the conductive gate material tiers, and b) an elevationally inner of the conductive gate material tiers. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is elevationally beyond a) the outer tier of the conductive gate material, or b) the inner tier of the conductive gate material.
In some embodiments, a vertical string of laterally opposing pairs of vertical ferroelectric field effect transistors comprises alternating tiers of laterally opposing dielectric material and laterally opposing conductive gate material. The laterally opposing conductive gate material in individual of the tiers comprises a respective gate of one of a pair of laterally opposing vertical ferroelectric field effect transistors in that tier. Isolating material extends through the tiers laterally between the transistors of the respective pairs. A transition metal dichalcogenide film extends through the tiers over each of two opposing lateral sides of the isolating material between the isolating material and the laterally opposing conductive gate material. The transition metal dichalcogenide films individually have a lateral thickness of 1 monolayer to 7 monolayers. The transition metal dichalcogenide films extend elevationally beyond at least one of a) an elevationally outer of the laterally opposing conductive gate material tiers, and b) an elevationally inner of the laterally opposing conductive gate material tiers. A ferroelectric gate dielectric film extends through the tiers over each of two opposing lateral sides of the individual transition metal dichalcogenide films between the transition metal dichalcogenide films and the laterally opposing conductive gate material. A conductive contact is directly against a lateral outer sidewall of a) each of the transition metal dichalcogenide films that is elevationally beyond the outer tier of the opposing conductive gate material, or b) each of the transition metal dichalcogenide films that is elevationally beyond the inner tier of the opposing conductive gate material.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
Sandhu, Gurtej S., Mouli, Chandra, Karda, Kamal M.
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