A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
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1. A semiconductor die comprising:
a substrate, the substrate having boundaries defined by a substrate termination edge;
a first passivation layer over the substrate, the first passivation layer terminating at a first passivation termination edge that is inset from the substrate termination edge by a first distance; and
a second passivation layer over the first passivation layer and the substrate, the second passivation layer terminating at a second passivation termination edge that is inset from the substrate termination edge by a second distance, wherein the second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer and the second passivation layer is directly coupled to the first passivation termination edge.
14. A method for manufacturing a semiconductor die comprising:
providing a substrate, the substrate having boundaries defined by a substrate termination edge;
providing a first passivation layer over the substrate such that the first passivation layer terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance; and
providing a second passivation layer over the first passivation layer and the substrate such that the second passivation layer terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance, wherein the second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer and the second passivation layer is directly coupled to the first passivation termination edge.
2. The semiconductor die of
3. The semiconductor die of
an active area in which one or more active devices are provided; and
a barrier region surrounding the active area and configured to electrically isolate the active area from the substrate termination edge, wherein:
the barrier region terminates at a barrier region termination edge that is inset from the substrate termination edge by a fourth distance, wherein the fourth distance is greater than the third distance; and
a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.
4. The semiconductor die of
5. The semiconductor die of
6. The semiconductor die of
7. The semiconductor die of
8. The semiconductor die of
9. The semiconductor die of
an active area in which one or more active devices are provided; and
a barrier region surrounding the active area and configured to electrically isolate the active area from the substrate termination edge, wherein:
the barrier region terminates at a barrier region termination edge that is inset from the substrate termination edge by a third distance, wherein the third distance is greater than the second distance; and
a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.
10. The semiconductor die of
11. The semiconductor die of
12. The semiconductor die of
13. The semiconductor die of
15. The method of
16. The method of
surrounds an active region in which one or more active devices are provided;
electrically isolates the active region from the substrate termination edge; and
terminates at a barrier region termination edge that is inset from the substrate termination edge by a fourth distance that is greater than the third distance such that a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.
18. The method of
19. The method of
20. The method of
surrounds an active region in which one or more active devices are provided;
electrically isolates the active region from the substrate termination edge; and
terminates at a barrier region termination edge that is inset from the substrate termination edge by a fourth distance that is greater than the third distance such that a charge redistribution path is formed by a region between the barrier region termination edge and the substrate termination edge.
21. The method of
22. The method of
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The present disclosure is related to semiconductor devices, and in particular to semiconductor devices with increased ruggedness and methods for making the same.
Numerous semiconductor devices can be fabricated together on a semiconductor die. For purposes of illustration,
The first passivation layer 14 is provided over the active area 24 and extends over the barrier region 26 to a passivation termination edge 30. The second passivation layer 16 is over the first passivation layer 14 and similarly extends to the passivation termination edge 30. The third passivation layer 18 is over the second passivation layer 16 and similarly extends to the passivation termination edge 30. The contact pads 20 may be provided on the second passivation layer 16 and be exposed to the outside environment via one or more openings in the third passivation layer 18. While not shown, metallization layers within the first passivation layer 14 and the second passivation layer 16 may couple the contact pads to one or more semiconductor devices in the active area 24. The passivation termination edge 30 is inset from the substrate termination edge 22 by a certain distance D.
The first passivation layer 14, the second passivation layer 16, and the third passivation layer 18 are provided to isolate the semiconductor devices in the active area 24 from the surrounding environment, both electrically and physically. However, when the conventional semiconductor die 10 is in a humid environment and subject to high temperatures and/or bias voltages, one or more of the first passivation layer 14, the second passivation layer 16, and the third passivation layer 18 may delaminate from their underlying layer, allowing moisture to penetrate into the active area 24. This may cause failure of the conventional semiconductor die 10. This problem is exacerbated by an electric field created by operating one or more semiconductor devices in the active area 24, which may be quite high at the passivation termination edge 30. This electric field may draw moisture from the passivation termination edge 30 towards the active area 24 and thus cause failure of the conventional semiconductor die 10 as discussed above.
In light of the above, there is a need for a semiconductor die with improved ruggedness and methods for manufacturing the same.
The present disclosure is related to semiconductor devices, and in particular to semiconductor devices with increased ruggedness and methods for making the same. In one embodiment, a semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer. By overlapping the second passivation layer and the first passivation layer, the ruggedness of the semiconductor die can be significantly increased, since moisture can be prevented from penetrating the first passivation layer and the second passivation layer.
In one embodiment, a method for manufacturing a semiconductor die includes the steps of providing a substrate, providing a first passivation layer over the substrate, and providing a second passivation layer over the first passivation layer. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is provided over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer. By overlapping the second passivation layer and the first passivation layer, the ruggedness of the semiconductor die can be significantly increased, since moisture can be prevented from penetrating the first passivation layer and the second passivation layer.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The first passivation layer 36 is provided over the active area 46 and extends over the barrier region 48 to a first passivation termination edge 52. The second passivation layer 38 is over the first passivation layer 36 and the substrate 34 and extends to a second passivation termination edge 54. The third passivation layer 40 is over the second passivation layer 38 and similarly extends to the second passivation termination edge 54. The contact pads 42 may be provided on the second passivation layer 38 and be exposed to the outside environment via one or more openings in the third passivation layer 40. While not shown, metallization layers within the first passivation layer 36 and the second passivation layer 38 may couple the contact pads to one or more semiconductor devices in the active area 46.
The first passivation termination edge 52 is inset from the substrate termination edge 44 by a first distance D1. In various embodiments, the first distance D1 may be between 1 μm and 150 μm. The second passivation termination edge 54 is inset from the substrate termination edge 44 by a second distance D2. In various embodiments, the second distance D2 may be between 0.5 μm and 50 μm. Notably, the second distance D2 is less than the first distance D1 such that the second passivation layer 38 and the third passivation layer 40 overlap the first passivation layer 36. Accordingly, the first passivation termination edge 52 is shielded from the surrounding environment by the second passivation layer 38 and the third passivation layer 40. Providing the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 in this manner increases the ruggedness of the semiconductor die 32 by preventing moisture ingress into the active area 46. In one embodiment, a difference between the first distance D1 and the second distance D2 is greater than 0.5 μm and less than 100 μm. In general, the difference between the first distance D1 and the second distance D2 may be greater than x and less than y. In various embodiments, x may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, and up to but not including 50 μm. For any of these embodiments y may be 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, and up to 100 μm.
While only three passivation layers are shown, the principles discussed herein may be applied to any number of passivation layers without departing from the principles of the present disclosure. Further, the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 may comprise multiple layers themselves. Finally, the principles of the present disclosure may be applied to as little as two passivation layers. That is, the third passivation layer 40 is optional in the embodiment discussed above. Additionally, while the substrate 34 is shown as a single layer, the substrate 34 may include multiple layers (e.g., a carrier layer and one or more epitaxial layers on top of the carrier layer). In these embodiments, the barrier region 48 may be provided through one or more of the epitaxial layers, but not the carrier layer. In one embodiment, the substrate 34 may comprise gallium nitride (GaN). In other embodiments, the substrate 34 may comprise silicon (Si), silicon carbide (SiC), or any other semiconductor material system.
In one embodiment, the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 comprise stoichiometric and non-stoichiometric formulations of alumina, silica, silicon nitride, silicon oxynitride, silicon dioxide, and/or zirconium oxide. Further, the composition of the first passivation layer 36, the second passivation layer 38, and the third passivation layer 40 may alternate in some embodiments. Separately applying the passivation layers and/or alternating the composition of the passivation layers may reduce the presence of defects (e.g., pinholes) in the layers that traverse more than one of the layers to prevent exposing the active area 46 to the outside environment.
In the embodiment shown in
As discussed above, the buildup of an electric field at the termination edge of any of the passivation layers may contribute to moisture and/or ion ingress as it may attract particles towards the active area 46 and thus encourage delamination thereof. In an effort to mitigate this effect,
In addition to mitigating the ingress of moisture and/or ions to the active area of the semiconductor die 32, the charge redistribution path 58 may provide other operational benefits as well. While the charge redistribution path 58 shown in
While the charge redistribution paths are discussed above with respect to semiconductor die, the principles described herein may also be applied to other devices such as monolithic microwave integrated circuits.
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
Namishia, Daniel, Radulescu, Fabian, Hardiman, Chris, Lee, Kyoung-Keun, Sheppard, Scott Thomas
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