To provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision. A reference voltage generation circuit includes nonvolatile storage elements formed of single layer polysilicon. The nonvolatile storage elements each include a mos transistor including a floating gate, a mos transistor including a floating gate, and a mos transistor including a floating gate.
|
6. A nonvolatile storage element comprising:
a first mos transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second mos transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a pn junction portion configured to form a pn junction between the first gate and the second gate; and
a silicide formed on the pn junction portion, wherein
the nonvolatile storage element includes at least one of a structure in which the conductivity type of the first gate is different from a conductivity type of the first source region in the first mos transistor, and a structure in which the conductivity type of the second gate is different from a conductivity type of the second source region in the second mos transistor.
8. A reference voltage generation circuit comprising a plurality of nonvolatile storage elements each of which comprising:
a first mos transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second mos transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a pn junction portion configured to form a pn junction between the first gate and the second gate; and
a silicide formed on the pn junction portion,
the plurality of the nonvolatile storage elements including at least a first nonvolatile storage element configured to serve as a depletion type mos transistor and a second nonvolatile storage element configured to serve as an enhancement type mos transistor, and
the first nonvolatile storage element and the second nonvolatile storage element being connected in series between a first power source terminal and a second power source terminal.
7. A nonvolatile storage element comprising:
a first mos transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second mos transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a pn junction portion configured to form a pn junction between the first gate and the second gate;
a silicide formed on the pn junction portion; and
a third mos transistor including a third gate connected to the second gate, a third source region, a third drain region, and a third bulk region, the third gate being of the other conductive type, the third source region, the third drain region, and the third bulk region being connected to each other, wherein
the nonvolatile storage element includes at least one of a structure in which the conductivity type of the first gate is different from a conductivity type of the first source region in the first mos transistor, a structure in which the conductivity type of the second gate is different from a conductivity type of the second source region in the second mos transistor, and a structure in which the conductivity type of the third gate is different from a conductivity type of the third source region in the third mos transistor.
13. A reference voltage generation circuit comprising a plurality of nonvolatile storage elements each of which comprising:
a first mos transistor including a first source region, a first drain region, and a first gate, the first gate being of one conductive type of P type or N type and being in a floating state;
a second mos transistor including a second gate, a second source region, a second drain region, and a second bulk region, the second gate being of another conductive type of P type or N type, the second source region, the second drain region, and the second bulk region being connected to each other;
a pn junction portion configured to form a pn junction between the first gate and the second gate;
a silicide formed on the pn junction portion; and
a third mos transistor including a third gate connected to the second gate, a third source region, a third drain region, and a third bulk region, the third gate being of the other conductive type, the third source region, the third drain region, and the third bulk region being connected to each other,
the plurality of the nonvolatile storage elements including at least a first nonvolatile storage element configured to serve as a depletion type mos transistor and a second nonvolatile storage element configured to serve as an enhancement type mos transistor, and
the first nonvolatile storage element and the second nonvolatile storage element being connected in series between a first power source terminal and a second power source terminal,
wherein at least one of the first gate, the second gate and the third gate of the first nonvolatile storage element is of a different conductive type from the conductive type of at least one of the first gate, the second gate and the third gate of the second volatile storage element in at least some regions.
1. A reference voltage generation circuit comprising:
a first mos transistor including a first source terminal, a first drain terminal, and a first gate terminal in a floating state;
a second mos transistor including a second gate terminal connected to the first gate terminal, a second source terminal, a second drain terminal, and a second bulk terminal, the second source terminal, the second drain terminal, and the second bulk terminal being connected to the first source terminal and being connected to each other;
a third mos transistor including a third source terminal, a third drain terminal, and a third gate terminal in a floating state;
a fourth mos transistor including a fourth gate terminal connected to the third gate terminal, a fourth source terminal, a fourth drain terminal, and a fourth bulk terminal, the fourth source terminal, the fourth drain terminal, and the fourth bulk terminal being connected to the third drain terminal and being connected to each other;
a first power source terminal; and
a second power source terminal configured to have a lower voltage than a voltage of the first power source terminal when the first mos transistor and the third mos transistor are N-channel mos transistors, and to have a higher voltage than the voltage of the first power source terminal when the first mos transistor and the third mos transistor are P-channel mos transistors,
wherein the first drain terminal is connected to the first power source terminal, the third source terminal is connected to the second power source terminal, and the first source terminal is connected to the third drain terminal; or
wherein the third drain terminal is connected to the first power source terminal, the first source terminal is connected to the second power source terminal, and the first drain terminal is connected to the third source terminal.
2. The reference voltage generation circuit according to
3. The reference voltage generation circuit according to
4. The reference voltage generation circuit according to
5. The reference voltage generation circuit according to
9. The reference voltage generation circuit according to
10. The reference voltage generation circuit according to
11. The reference voltage generation circuit according to
12. The reference voltage generation circuit according to
|
|||||||||||||||||||||||||||||||||
This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. 2017-071027 filed on Mar. 31, 2017, and Japanese Patent Application No. 2018-030944 filed on Feb. 23, 2018, the entire contents of which are incorporated by reference herein.
The present invention relates to a nonvolatile storage element and a reference voltage generation circuit.
Generally, in semiconductor devices incorporating a reference voltage generation circuit, manufacturing variations in threshold values Vth of respective transistors, resistance values of respective resistance elements, and the like included in the reference voltage generation circuit can cause a reference voltage Vref assumed in design to vary significantly from a desired value. Thus, semiconductor devices requiring a stable reference voltage Vref require a highly precise reference voltage generation circuit. To correct reference voltage variation in the reference voltage generation circuit caused due to manufacturing variations, semiconductor devices incorporate many auxiliary transistors for adjusting a reference voltage by correcting a wiring layer or are configured such that the reference voltage can be adjusted by a laser trimmer after manufacturing. However, correcting the reference voltage variation in the reference voltage generation circuit by such configurations leads to problems such as an increase in a layout area of the reference voltage generation circuit and an increase in the number of steps for performing voltage adjustment. Accordingly, to solve such problems, various reference voltage generation circuits have been proposed.
JP 04-65546 B2 discloses an ordinary reference voltage generation circuit. JP 04-65546 B2 proposes a reference voltage generation circuit having a structure in which, by using constant current characteristics of a depletion type MOSFET (metal oxide film semiconductor field-effect transistor) having a gate G and a source region S connected to each other, a voltage generated in an enhancement type MOSFET that has a gate G and a drain region D connected to each other and operates at the constant current is used as a reference voltage Vref.
When Vth_d represents a threshold voltage of the depletion type transistor Md and Vth_e represents a threshold voltage of the enhancement type transistor Me, the reference voltage Vref can be represented as a sum of an absolute value of the threshold voltage Vth_d and an absolute value of the threshold voltage Vth_e, i.e., “Vref =|Vth_d|+|Vth_eV|”.
However, the reference voltage generation circuit 100 is influenced by manufacturing variations in current/voltage characteristics of the depletion type transistor Md and current/voltage characteristics of the enhancement type transistor Me. Thus, as circuits configured such that a highly precise reference voltage can be taken out without being influenced by any manufacturing variations, JP 2002-368107 A and JP 2013-246627 A disclose reference voltage generation circuits using a FET type nonvolatile storage element. The reference voltage generation circuits as disclosed in JP 2002-368107 A and JP 2013-246627 A have substantially the same structure as the reference voltage generation circuit 100 illustrated in
According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first MOS transistor including a first source terminal, a first drain terminal, and a first gate terminal in a floating state; a second MOS transistor including a second gate terminal connected to the first gate terminal, a second source terminal, a second drain terminal, and a second bulk terminal, the second source terminal, the second drain terminal, and the second bulk terminal being connected to the first source terminal and being connected to each other; a third MOS transistor including a third source terminal, a third drain terminal, and a third gate terminal in a floating state; a fourth MOS transistor including a fourth gate terminal connected to the third gate terminal, a fourth source terminal, a fourth drain terminal, and a fourth bulk terminal, the fourth source terminal, the fourth drain terminal, and the fourth bulk terminal being connected to the third drain terminal and being connected to each other; a first power source terminal; and a second power source terminal configured to have a lower voltage than a voltage of the first power source terminal when the first MOS transistor and the third MOS transistor are N-channel MOS transistors, and to have a higher voltage than the voltage of the first power source terminal when the first MOS transistor and the third MOS transistor are P-channel MOS transistors, wherein the first drain terminal is connected to the first power source terminal, the third source terminal is connected to the second power source terminal, and the first source terminal is connected to the third drain terminal; or wherein the third drain terminal is connected to the first power source terminal, the first source terminal is connected to the second power source terminal, and the first drain terminal is connected to the third source terminal.
According to another aspect of the present invention, there is provided a nonvolatile storage element including: a first MOS transistor including a first source terminal, a first drain terminal, and a first gate terminal, the first gate terminal being of one conductive type of P type or N type and being in a floating state; a second MOS transistor including a second gate terminal, a second source terminal, a second drain terminal, and a second bulk terminal, the second gate terminal being of an other conductive type of P type or N type, the second source terminal, the second drain terminal, and the second bulk terminal being connected to each other; a PN junction portion configured to form a PN junction between the first gate terminal and the second gate terminal; and a silicide formed on the PN junction portion.
According to still another aspect of the present invention, there is provided a reference voltage generation circuit including a plurality of the nonvolatile storage elements according to the above-mentioned aspect of the present invention, the plurality of the nonvolatile storage elements including at least a first nonvolatile storage element configured to serve as a depletion type MOS transistor and a second nonvolatile storage element configured to serve as an enhancement type MOS transistor, and the first nonvolatile storage element and the second nonvolatile storage element being connected in series between a first power source terminal and a second power source terminal.
The nonvolatile storage elements forming the reference voltage generation circuits disclosed in JP 2002-368107 A and JP 2013-246627 A are those using two layers of polysilicon, as used in so-called nonvolatile memories such as an EEPROM. Such nonvolatile storage elements using two layers of polysilicon require a complicated exclusive forming process, thus increasing manufacturing cost, and not being versatile for use.
It is an object of embodiments to provide a nonvolatile storage element capable of being formed by an ordinary CMOS process using single layer polysilicon without requiring exclusive forming process and a reference voltage generation circuit with high versatility and high precision.
[First Embodiment]
A reference voltage generation circuit according to a first embodiment of the present invention will be described with reference to
The reference voltage generation circuit according to the present embodiment includes two or more nonvolatile storage elements formed by one layer of polysilicon (hereinafter referred to as “single layer polysilicon”). As illustrated in
A first area is a MOSFET area MFA. The MOSFET area MFA includes a MOS transistor 11 formed of a MOSFET. The MOS transistor 11 includes the floating gate G1 formed of polysilicon. The floating gate G1 is formed above the P-well region 112 via a gate insulating film 113 formed on a semiconductor substrate 14. The MOS transistor 11 includes a drain region D1 formed on one of both sides below the floating gate G1 via the gate insulating film 113 and a source region S1 formed on the other one of both sides below the floating gate G1. The drain region D1 is an N+ region formed inside the P-well region 112, and is connected to a terminal Td. The source region S1 is an N+ region formed inside the P-well region 112, and is connected to a terminal Tc. The P-well region 112 is connected to a terminal Tb via a P+ region 114 formed in a part of the P-well region 112. Additionally, the N-well region 142a formed on the semiconductor substrate 14 adjacently to the P-well region 112 is connected to a terminal Ta via an N+ region formed in a part of the N-well region 142a. The nonvolatile storage element Ma is element-isolated from other parts of the nonvolatile storage element Ma and other elements by the element isolation regions 143a to 143h. The floating gates G1, G2, and G3 are not directly connected to any electrode for electric contact therewith, and are, as the names suggest, in a floating state.
A second area is a control gate area CGA. The control gate area CGA includes a MOS transistor 12 formed of a MOSFET. The MOS transistor 12 includes the floating gate G2 formed of polysilicon. The floating gate G2 is formed above the P-well region 122 different from the P-well region 112 of the MOSFET area MFA via a gate insulating film 123. The gate insulating film 123 and the gate insulating film 113 of the MOSFET area MFA may be the same or different in kind and film thickness. The MOS transistor 12 in the control gate area CGA includes a drain region D2 formed on one of both sides below the floating gate G2 via the gate insulating film 123 and a source region S2 formed on the other one of both sides below the floating gate G2. The drain region D2 is an N+ region formed inside the P-well region 122. The source region S2 is an N+ region formed inside the P-well region 122. The drain region D2 is connected to a P+ region 124a that is formed inside the P-well region 122 and that is a contact portion of the P-well region 122. The source region S2 is connected to a P+ region 124b that is formed inside the P-well region 122 and that is a contact portion of the P-well region 122. The drain region D2, the source region S2, and the P+ regions 124a and 124b are connected to each other via a terminal Te. Additionally, the N-well region 142d formed on the semiconductor substrate 14 adjacently to the P-well region 122 is connected to a terminal Tf via an N+ region formed in a part of the N-well region 142d.
A third area is an electric charge injection area CIA. The electric charge injection area CIA includes a MOS transistor 13 formed of a MOSFET. The MOS transistor 13 includes the floating gate G3 formed of polysilicon. The floating gate G3 is formed above the P-well region 132 different from those of the MOSFET area MFA and the control gate area CGA via a gate insulating region 133. The gate insulating film 133 and at least one of the gate insulating film 113 of the MOSFET area MFA or the gate insulating film 123 of the control gate area CGA may be the same or different in kind and film thickness. The MOS transistor 13 in the electric charge injection area CIA includes a drain region D3 formed on one of both sides below the floating gate G3 via the gate insulating film 133 and a source region S3 formed on the other one of both sides below the floating gate G3. The drain region D3 is an N+ region formed inside the P-well region 132. The source region S3 is an N+ region formed inside the P-well region 132. In the electric charge injection area CIA, the drain region D3 is connected to a P+ region 134a that is formed inside the P-well region 132 and that is a contact portion of the P-well region 132, similarly to the control gate area CGA. The source region S3 is connected to a P+ region 134b that is formed inside the P-well region 132 and that is a contact portion of the P-well region 132. The drain region D3, the source region S3, and the P+ regions 134a and 134b are connected to each other via a terminal Tg. Additionally, the N-well region 142f formed on the semiconductor substrate 14 adjacently to the P-well region 132 is connected to a terminal Th via an N+ region formed in a part of the N-well region 142f.
The floating gate G1 used in the MOSFET area MFA, the floating gate G2 used in the control gate area CGA, and the floating gate G3 used in the electric charge injection area CIA are connected by the same polysilicon. A connection portion 15a connecting the floating gate G1 and the floating gate G2 across the MOSFET area MFA and the control gate area CGA is provided on the element isolation region 143d. A connection portion 15b connecting the floating gate G2 and the floating gate G3 across the control gate area CGA and the electric charge injection area CIA is provided on the element isolation region 143f. The floating gates G1, G2, and G3 and the connection portions 15a and 15b are formed of the same polysilicon.
In the MOSFET area MFA, a PN junction portion 144a is formed between the P-well region 112 and the deep N-well region 111, and a PN junction portion 144b is formed between the deep N-well region 111 and the semiconductor substrate 14. In the control gate area CGA, a PN junction portion 144c is formed between the P-well region 122 and the deep N-well region 121, and a PN junction portion 144d is formed between the deep N-well region 121 and the semiconductor substrate 14. In the electric charge injection area CIA, a PN junction portion 144e is formed between the P-well region 132 and the deep N-well region 131, and a PN junction portion 144f is formed between the deep N-well region 131 and the semiconductor substrate 14.
Roles of the respective areas MFA, CGA, and CIA are as follows: the MOSFET area MFA is an area configured to work as a MOSFET during operation of the reference voltage generation circuit; the control gate area CGA is an area configured to control potentials of the floating gate G1 of the MOSFET area MFA and the floating gate G3 of the electric charge injection area CIA; and the electric charge injection area CIA is an area configured to inject/discharge electric charge into/from the floating gate G3. In the respective areas MFA, CGA, and CIA, the gate insulating films 113, 123, and 133 are located between the floating gates G1, G2, and G3 and the semiconductor substrate 14, whereby electric charge injected into the floating gates G1, G2, and G3 are confined. Thus, depending on an amount of the electric charge confined in the floating gates G1, G2, and G3, the current/voltage characteristics of the MOS transistor 11 in the MOSFET area MFA become variable. In other words, a device formed by the structure as illustrated in
The nonvolatile storage element Ma can be formed by a so-called ordinary CMOS process, without using any special process. Note that a predetermined level of voltage is set to be applied to the respective terminals Ta to Th of the nonvolatile storage element Ma.
The threshold voltage Vth of the MOS transistor 11 provided in the MOSFET area MFA of the nonvolatile storage element Ma is controlled by the amount of electric charge injected into the floating gate G1. As illustrated in
As illustrated in
On the other hand, as illustrated in
In this manner, the nonvolatile storage element Ma can inject/discharge electric charge via the gate insulating film 133 provided in the electric charge injection area CIA by controlling voltages to be applied to the terminals Te and Tf provided in the control gate area CGA and the respective terminals Tg and Th provided in the electric charge injection area CIA. Note that although the present example has described the example of injection/discharge of electric charge using the positive pulse voltage, both a positive pulse voltage and a negative pulse voltage may be used to control injection/discharge of electric charge into/from the floating gates G1, G2, and G3. The nonvolatile storage element Ma does not use the MOSFET area MFA for injecting/discharging electric charge.
Next will be a description of the reference voltage generation circuit using the nonvolatile storage element according to the present embodiment. The reference voltage generation circuit according to the present embodiment is a circuit configured to generate a reference voltage by using a plurality of single layer polysilicon type nonvolatile storage elements. The reference voltage generation circuit according to the present embodiment uses the nonvolatile storage elements by bringing into two states: enhancement type transistor(s) and depletion type transistor(s). The nonvolatile storage element(s) used as the enhancement type transistor (s) and the nonvolatile storage element (s) used as the depletion type transistor(s) are the same in size and structure as element.
The reference voltage generation circuit according to the present embodiment is a circuit configured to eliminate manufacturing variation that occurs due to difference between characteristics of the respective circuit elements forming the circuit. The reference voltage generation circuit according to the present embodiment includes at least one or more depletion type transistors and at least one or more enhancement type transistors to which a current that is the same as or relevant to a current that flows to the one or more depletion type transistors flows. The one or more depletion type transistors and the one or more enhancement type transistors forming the reference voltage generation circuit according to the present embodiment are single-layer polysilicon type nonvolatile storage elements. Herein, the term “relevant current” means a current correlated with the current that flows to the one or more depletion type transistors. For example, the “relevant current” may be a current that is “X” times the current that flows to the one or more depletion type transistors, a current obtained by adding a current value Y to the current that flows to the one or more depletion type transistors, or a current having a more complicated relationship with the current than the two examples. In other words, the “relevant current” is a current represented by a function using, as a parameter, a value of the current that flows to the one or more depletion type transistors.
As illustrated in
The nonvolatile storage element Ma1 and the nonvolatile storage element Ma2 are connected in series between a high voltage supply terminal Vdd to which high voltage is supplied and a low voltage supply terminal Vss to which low voltage is supplied. Hereinafter, the sign “Vdd” is also used as the sign of a high voltage output from the high voltage supply terminal Vdd, and the sign “Vss” is also used as the sign of a low voltage output from the low voltage supply terminal Vss. The drain region D1 of the nonvolatile storage element Ma1 is connected to the high voltage supply terminal Vdd via the terminal Td, and the source region S1 of the nonvolatile storage element Ma2 is connected to the low voltage supply terminal Vss via the terminal Tc. The source region S1 of the nonvolatile storage element Ma1 and the source region S2, the drain region D2, and the P+ regions 124a and 124b (see
Furthermore, the source region S1, the source region S2, the drain region D2, and the P+ regions 124a and 124b of the nonvolatile storage element Ma1 are connected to the drain region D1, the source region S2, the drain region D2, and the P+ regions 124a and 124b of the nonvolatile storage element Ma2 via the terminals Tc and Te of the nonvolatile storage element Ma1 and the terminals Td and Te of the nonvolatile storage element Ma2.
Still furthermore, the voltage output terminal OUT is connected to a connection portion between the source region S1 of the nonvolatile storage element Ma1 and the drain region D1 of the nonvolatile storage element Ma2. In
In the reference voltage generation circuit 1, the nonvolatile storage element Ma2 on a lower stage side (a low voltage supply terminal Vss side) is adjusted into an enhancement state, and the nonvolatile storage element Ma1 on an upper stage side (a high voltage supply terminal Vdd side) is adjusted into a depletion state. The nonvolatile storage elements Ma1 and Ma2 both include a control gate (for example, the P-well region 122 of the control gate area CGA) and floating gates (for example, the floating gates G1, G2, and G3 of the respective areas). Thereby, the nonvolatile storage elements Ma1 and Ma2 can perform writing and erasing, and can hold a rewritten state for a long period. The threshold voltage of a depletion type transistor becomes negative, whereas the threshold voltage of an enhancement type transistor becomes positive. Thus, the plurality of nonvolatile storage elements provided in the reference voltage generation circuit 1 of the present embodiment include at least the nonvolatile storage element Ma1 having a negative threshold voltage and the nonvolatile storage element Ma2 having a positive threshold voltage.
An element area of each of the nonvolatile storage elements Ma1 and Ma2 provided in the reference voltage generation circuit 1 may be from 1000 μm2 to 1 mm2. The nonvolatile storage elements Ma1 and Ma2 do not have any array structure, even when having any such element area. Note that, although the present example uses signs of MOS transistors in
Constituent elements of the reference voltage generation circuit 1 can be made to correspond as follows.
The MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of a first MOS transistor. The source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of a first source terminal. The drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of a first drain terminal. The floating gate G1 of the MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of a first gate terminal.
The MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of a second MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of a second source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of a second drain terminal. The floating gate G2 of the MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of a second gate terminal. The P-well region 122 of the nonvolatile storage element Ma1 corresponds to one example of a second bulk terminal.
The MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of a third MOS transistor. The source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of a third source terminal. The drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of a third drain terminal. The floating gate G1 of the MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of a third gate terminal.
The MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of a fourth MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of a fourth source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of a fourth drain terminal. The floating gate G2 of the MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of a fourth gate terminal. The P-well region 122 of the nonvolatile storage element Ma2 corresponds to one example of a fourth bulk terminal.
In the reference voltage generation circuit 1, the MOS transistors 11 of the nonvolatile storage elements Ma1 and Ma2 are N-channel MOS transistors, and the low voltage supply terminal Vss has a lower voltage than the voltage of the high voltage supply terminal Vdd. Thus, in the reference voltage generation circuit 1, the high voltage supply terminal Vdd corresponds to one example of a first power source terminal, and the low voltage supply terminal Vss corresponds to one example of a second power source terminal. Furthermore, in the reference voltage generation circuit 1, the drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma1 is connected to the high voltage supply terminal Vdd via the terminal Td, and the source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma2 is connected to the low voltage supply terminal Vss via the terminal Tc. The source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma1 is connected to the drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma2 via the terminals Tc and Td.
As will be described below, there are two adjustment methods to adjust the nonvolatile storage elements Ma1 and Ma2 of the reference voltage generation circuit 1 illustrated in
First, as illustrated in
First, as illustrated in
States of the switches SW1 to SW9 in a state where the reference voltage generation circuit 1 illustrated in
SW1: VDD
SW2: VSS
SW3: ON-state (connected to a connection node N1 between one terminal of the switch SW5 and the terminal Tc)
SW4: OFF-state (open)
SW5: ON-state (connected)
SW6: ON-state (connected)
SW7: ON-state (connected to a connection node N2 between one terminal of the switch SW6 and the terminal Td)
SW8: OFF-state (open)
SW9: VSS
When the nonvolatile storage element Ma1 is in a depletion state and the nonvolatile storage element Ma2 is in an enhancement state in the state illustrated in
An adjustment sequence by the first adjustment method illustrated in
<Adjustment Sequence (1)>
The nonvolatile storage element Ma2 is brought into an enhancement state (the threshold value is set to be larger than a desired reference voltage VREF). The states of the switches SW1 to SW9 in the state of transition to the enhancement direction (in other words, the state where the threshold value is adjusted to the plus direction) are as follows:
SW1: VSS
SW2: VSS
SW3: VSS
SW4: Optional (OFF-state (open) in
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VPP
SW8: ON-state (connected)
SW9: VSS
SW1: VSS
SW2: VSS
SW3: VSS
SW4: Optional (OFF-state (open) in
SW5: OFF-state (open)
SW6: ON-state (connected)
SW7: ON-state (connected to N2)
SW8: OFF-state (open)
SW9: VSS
<Adjustment Sequence (2)>
The nonvolatile storage element Ma2 is caused to transition to a depletion direction (in other words, the threshold voltage is adjusted to the minus direction) to gradually reduce the threshold voltage, and the nonvolatile storage element Ma2 is brought into the desired enhancement state (the threshold voltage is made equal to the desired reference voltage VREF), thereby adjusting so that the desired reference voltage VREF is output. As in
SW1: VSS
SW2: VSS
SW3: VSS
SW4: Optional (OFF-state (open) in
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VSS
SW8: ON-state (connected)
SW9: VPP
<Adjustment Sequence (3)>
The nonvolatile storage element Ma1 is once brought into an enhancement state. At this time, the nonvolatile storage element Ma2 in the desired enhancement state is not connected to the nonvolatile storage element Ma1. States of the switches SW1 to SW9 in the state where the nonvolatile storage element Ma1 is caused to transition to the enhancement direction (in other words, the state where the threshold voltage is adjusted to the plus direction) are as follows:
SW1: VSS
SW2: VSS
SW3: VPP
SW4: ON-state (connected)
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VSS
SW8: Optional (OFF-state (open) in
SW9: VSS
<Adjustment Sequence (4)>
By bringing the nonvolatile storage element Ma1 into the desired depletion state, an adjustment is made so that a desired reference voltage VREF is output. The states of the switches SW1 to SW9 in the state where the nonvolatile storage element Ma1 is caused to transition to the depletion direction (in other words, the state where the threshold voltage of the nonvolatile storage element Ma1 is adjusted to the minus direction) are as follows:
SW1: VSS
SW2: VPP
SW3: VSS
SW4: ON-state (connected)
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VSS
SW8: Optional (OFF-state (open) in
SW9: VSS
SW1: VDD
SW2: VSS
SW3: ON-state (connected to the connection node N1 between one terminal of the switch SW5 and the terminal Tc)
SW4: OFF-state (open)
SW5: ON-state (connected)
SW6: ON-state (connected)
SW7: ON-state (connected to the connection node N2 between one terminal of the switch SW6 and the terminal Td)
SW8: OFF-state (open)
SW9: VSS
As illustrated in
Additionally, adjustment sequences by the second adjustment method illustrated in
<Adjustment Sequence (1)>
SW1: VSS
SW2: VSS
SW3: VPP
SW4: ON-state (connected)
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VSS
SW8: Optional (OFF-state (open) in
SW9: VSS
<Adjustment Sequence (2)>
By bringing the nonvolatile storage element Ma1 into the desired depletion state, an adjustment is made so that a desired reference current IREF flows. The transition of the nonvolatile storage element Ma1 into the desired depletion state is performed while monitoring and confirming a reference current IREF. When the reference current IREF becomes larger than the desired current value, the above-described <Adjustment Sequence (1)> is again performed. The states of the switches SW1 to SW9 in the state where the transition to the depletion direction is performed (in other words, the state where the threshold voltage of the nonvolatile storage element Ma1 is adjusted to the minus direction) are as follows:
SW1: VSS
SW2: VPP
SW3: VSS
SW4: ON-state (connected)
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VSS
SW8: Optional (OFF-state (open) in
SW9: VSS
SW1: VDD
SW2: VSS
SW3: ON-state (connected to the connection node N1 between one terminal of the switch SW5 and the terminal Tc)
SW4: OFF-state (open)
SW5: ON-state (connected)
SW6: OFF-state (open)
SW7: VSS
SW8: Optional (OFF-state (open) in
SW9: VSS
<Adjustment Sequence (3)>
The nonvolatile storage element Ma2 is caused to transition into the enhancement state (the threshold voltage of the nonvolatile storage element Ma2 is made larger than the reference voltage VREF). The states of the switches SW1 to SW9 in the state of transition to the enhancement direction (in other words, the threshold voltage of the nonvolatile storage element Ma2 is adjusted to the plus direction) are as follows:
SW1: VSS
SW2: VSS
SW3: VSS
SW4: Optional (OFF-state (open) in
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VPP
SW8: ON-state (connected)
SW9: VSS
SW1: VSS
SW2: VSS
SW3: VSS
SW4: Optional (OFF-state (open) in
SW5: OFF-state (open)
SW6: ON-state (connected)
SW7: ON-state (connected to the connection node N2 between one terminal of the switch SW6 and the terminal Td)
SW8: OFF-state (open)
SW9: VSS
<Adjustment Sequence (4)>
By bringing the nonvolatile storage element Ma2 into the desired enhancement state, an adjustment is made so that a desired reference voltage VREF is output. As illustrated in
SW1: VSS
SW2: VSS
SW3: VSS
SW4: Optional (OFF-state (open) in
SW5: OFF-state (open)
SW6: OFF-state (open)
SW7: VSS
SW8: ON-state (connected)
SW9: VPP
The reference voltage generation circuit 1 includes at least one or more depletion type MOS transistors and at least one or more enhancement type MOS transistors in which a current that flows to the enhancement type MOS transistors is the same as or relevant to a current that flows to the depletion type MOS transistors, and each of the MOS transistors is a nonvolatile storage element.
As illustrated in
Next, at step S102, writing operation is performed, and processing is moved to step S103. Specifically, at step S102, the writing operation is performed in at least one of the plurality of nonvolatile storage elements.
Next, at step S103, a reference voltage is generated, and the processing is ended.
The reference voltage generation circuit 1 includes at least one or more depletion type MOS transistors and at least one or more enhancement type MOS transistors in which a current that flows to the enhancement type transistors is the same as or relevant to a current that flows to the depletion type MOS transistors, and each of the MOS transistors is a nonvolatile storage element.
As illustrated in
Next, at step S112, erasing operation is performed, and processing is moved to step S113. Specifically, at step S112, the erasing operation is performed in at least one of the plurality of nonvolatile storage elements.
Next, at step S113, a reference voltage is generated, and the processing is ended.
The reference voltage VREF to be generated is the same as that in a circuit using depletion MOS and enhancement MOS transistors. However, adjustment of the reference voltage VREF to be generated can be optionally performed by the nonvolatile storage elements. Additionally, since the same nonvolatile storage elements are used, variation in process can also be prevented.
[Second Embodiment]
A reference voltage generation circuit according to a second embodiment of the invention will be described with reference to
The reference voltage generation circuit according to the present embodiment uses two or more nonvolatile storage elements that can be driven as PMOS transistors formed of single layer polysilicon. In the nonvolatile storage element Ma according to the above first embodiment, the MOS transistor provided in the MOSFET area MFA is a NMOS transistor (see
In the MOSFET area MFA of the present embodiment is provided a MOS transistor 21 formed of a MOSFET. The MOS transistor 21 includes a floating gate G21 formed of polysilicon. The floating gate G21 is formed of single layer polysilicon. The floating gate G21 is formed above an N-well region 212 via a gate insulating film 213. The MOS transistor 21 includes a drain region D21 formed on one of both sides below the floating gate G21 via the gate insulating film 213 and a source region S21 formed on the other one of both sides below the floating gate G21. The drain region D21 is a P+region formed inside the N-well region 212, and is connected to a terminal Td. The source region S21 is a P+ region formed inside the N-well region 212, and is connected to a terminal Tc. The nonvolatile storage element Mb is element-isolated from other parts of the nonvolatile storage element Mb and other elements by element-isolating regions 143a and 143c to 143h. The floating gate G21 is not directly connected to any electrode for electric contact therewith, and is, as the name suggests, in a floating state. The control gate area CGA and the electric charge injection area CIA other than the MOSFET area MFA have the same structure as the control gate area CGA and the electric charge injection area CIA of the nonvolatile storage element Ma according to the first embodiment. Thus, respective structural components of the control gate area CGA and the electric charge injection area CIA of the present embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description thereof will be omitted.
Next will be a description of the reference voltage generation circuit using the nonvolatile storage element according to the present embodiment. The reference voltage generation circuit according to the present embodiment is a circuit configured to generate a reference voltage by using a plurality of nonvolatile storage elements configured to operate as single-layer polysilicon type PMOS transistors. The reference voltage generation circuit according to the present embodiment uses the nonvolatile storage elements by bringing into two states: enhancement type transistor(s) and depletion type transistor(s). The nonvolatile storage element (s) used as the enhancement type transistor (s) and the nonvolatile storage element(s) used as the depletion type transistor(s) are same in size and structure as element.
The reference voltage generation circuit according to the present embodiment is a circuit configured to eliminate manufacturing variation in reference voltage that occurs due to difference of characteristics between respective circuit elements forming the circuit. The reference voltage generation circuit according to the present embodiment includes at least one or more depletion type transistors and at least one or more enhancement type transistors to which there flows a current that is the same as or relevant to a current that flows to the depletion type transistor. The one or more depletion type transistors and the one or more enhancement type transistors forming the reference voltage generation circuit according to the present embodiment are nonvolatile storage elements configured to operate as single-layer polysilicon type PMOS transistors.
As illustrated in
The nonvolatile storage element Mb1 and the nonvolatile storage element Mb2 are connected in series between a high voltage supply terminal Vdd to which high voltage is supplied and a low voltage supply terminal Vss to which low voltage is supplied. The source region S21 of the nonvolatile storage element Mb1 is connected to the high voltage supply terminal Vdd via the terminal Tc, and the drain region D21 of the nonvolatile storage element Mb2 is connected to the low voltage supply terminal Vss via the terminal Td. The source region S21 of the nonvolatile storage element Mb1 and the source region S2, the drain region D2, and the P+ regions 124a and 124b (see
Furthermore, the drain region D21 of the nonvolatile storage element Mb1 and the source region S21 of the nonvolatile storage element Mb2 are connected to each other via the terminal Td and the terminal Tc. To a connection portion between the drain D21 and the source region S21 is connected the voltage output terminal OUT. In
In the reference voltage generation circuit 2, the nonvolatile storage element Mb2 on the lower stage side (the low voltage supply terminal Vss side) is adjusted into an enhancement state, and the nonvolatile storage element Mb1 on the upper stage side (the high voltage supply terminal Vdd side) is adjusted into a depletion state. The nonvolatile storage elements Mb1 and Mb2 both include a control gate (for example, the P-well region 122 of the control gate area CGA) and floating gates (for example, the floating gates G21, G2, and G3 of the respective areas). Thereby, the nonvolatile storage elements Mb1 and Mb2 can perform writing and erasing, and can hold a rewritten state for a long period. Since the MOS transistor 21 is formed of a PMOS transistor, the threshold voltage of the depletion type transistor is positive, and the threshold voltage of the enhancement type transistor is negative. Thus, the plurality of nonvolatile storage elements Mb1 and Mb2 provided in the reference voltage generation circuit 2 of the present embodiment include at least the nonvolatile storage element Mb1 having a positive threshold voltage and the nonvolatile storage element Mb2 having a negative threshold voltage.
An element area of each of the nonvolatile storage elements Mb1 and Mb2 provided in the reference voltage generation circuit 2 may be from 1000 μm2 to 1 mm2. The nonvolatile storage elements Mb1 and Mb2 do not have any array structure, even when having any such element area.
Constituent elements of the reference voltage generation circuit 2 can be made to correspond as follows.
The MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the first MOS transistor. The source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the first source terminal. The drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the first drain terminal. The gate G21 of the MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the first gate terminal.
The MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the second MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the second source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the second drain terminal. The gate G2 of the MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the second gate terminal. The P-well region 122 of the nonvolatile storage element Mb1 corresponds to one example of the second bulk terminal.
The MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the third MOS transistor. The source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the third source terminal. The drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the third drain terminal. The gate G21 of the MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the third gate terminal.
The MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the fourth MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the fourth source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the fourth drain terminal. The gate G2 of the MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the fourth gate terminal. The P-well region 122 of the nonvolatile storage element Mb2 corresponds to one example of the fourth bulk terminal.
In the reference voltage generation circuit 2, the MOS transistor 21 of the nonvolatile storage elements Mb1, Mb2 is a P-channel MOS transistor, and the low voltage supply terminal Vss has a lower voltage than the voltage of the high voltage supply terminal Vdd. Thus, in the reference voltage generation circuit 2, the high voltage supply terminal Vdd corresponds to one example of the second power source terminal, and the low voltage supply terminal Vss corresponds to one example of the first power source terminal. Furthermore, in the reference voltage generation circuit 2, the drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb2 is connected to the low voltage supply terminal Vss via the terminal Td, and the source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb1 is connected to the high voltage supply terminal Vdd via the terminal Tc. The drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb1 is connected to the source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb2 via the terminals Td and Tc.
The states of switches SW1 to SW9 in a state where the reference voltage generation circuit 2 illustrated in
SW1: VDD
SW2: VSS
SW3: ON-state (connected to a connection node N1 between one terminal of the switch SW1 and the terminal Tc)
SW4: OFF-state (open)
SW5: ON-state (connected)
SW6: ON-state (connected)
SW7: ON-state (connected to a connection node N2 between one of three terminals of the switch SW7 and the terminal Td)
SW8: OFF-state (open)
SW9: VSS
When the nonvolatile storage element Mb1 is in a depletion state and the nonvolatile storage element Mb2 is in an enhancement state in the state illustrated in
By performing the same adjustment sequences as those of the first example of the first embodiment in the structure illustrated in
[Third Embodiment]
A reference voltage generation circuit according to a third embodiment of the invention will be described with reference to
The reference voltage generation circuit according to the present embodiment is a circuit configured to generate a reference voltage by using a plurality of the nonvolatile storage elements Ma (see
The reference voltage generation circuit according to the present embodiment is a circuit configured to eliminate manufacturing variation in reference voltage that occurs due to difference of characteristics between respective circuit elements forming the circuit. The reference voltage generation circuit according to the present embodiment includes at least one or more depletion type transistors and at least one or more enhancement type transistors to which a current that is the same as or relevant to a current that flows to the depletion type transistors flows. The one or more depletion type transistors and the one or more enhancement type transistors forming the reference voltage generation circuit according to the present embodiment are nonvolatile storage elements configured to operate as single-layer polysilicon type NMOS transistors.
As illustrated in
The nonvolatile storage elements Ma1 and Ma2 are connected in series between the negative high voltage supply terminal −Vdd to which a negative high voltage is supplied and a low voltage supply terminal Vss to which a low voltage is supplied. The source region S1 of the nonvolatile storage element Ma1 is connected to the negative high voltage supply terminal −Vdd via the terminal Tc, and the drain region D1 of the nonvolatile storage element Ma2 is connected to the low voltage supply terminal Vss via the terminal Td. The source region S1 of the nonvolatile storage element Ma1 and the source region S2, the drain region D2, and the P+ regions 124a and 124b (see
Furthermore, the drain region D1 of the nonvolatile storage element Ma1 and the source region S1 of the nonvolatile storage element Ma2 are connected to each other via the terminal Td and the terminal Tc. To a connection portion between the drain D1 and the source region S1 is connected the voltage output terminal OUT. In
In the reference voltage generation circuit 3, the nonvolatile storage element Ma2 on the lower stage side (the low voltage supply terminal Vss side) is adjusted into an enhancement state, and the nonvolatile storage element Ma1 on the upper stage side (the negative high voltage supply terminal −Vdd side) is adjusted into a depletion state. The nonvolatile storage elements Ma1 and Ma2 both include a control gate (for example, the P-well region 122 of the control gate area CGA) and floating gates (for example, floating gates G1, G2, and G3 of the respective areas). Thereby, the nonvolatile storage elements Ma1 and Ma2 can perform writing and erasing, and can hold a rewritten state for a long period. The threshold voltage of the depletion type transistor is negative, and the threshold voltage of the enhancement type transistor is positive. Thus, the plurality of nonvolatile storage elements Ma1 and Ma2 provided in the reference voltage generation circuit 3 of the present embodiment include at least the nonvolatile storage element Ma1 having a negative threshold voltage and the nonvolatile storage element Ma2 having a positive threshold voltage.
An element area of each of the nonvolatile storage elements Ma1 and Ma2 provided in the reference voltage generation circuit 3 may be from 1000 μm2 to 1 mm2. The nonvolatile storage elements Ma1 and Ma2 do not have any array structure, even when having any such element area.
Constituent elements of the reference voltage generation circuit 3 can be made to correspond as follows.
The MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of the first MOS transistor. The source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of the first source terminal. The drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of the first drain terminal. The floating gate G1 of the MOS transistor 11 of the nonvolatile storage element Ma2 corresponds to one example of the first gate terminal.
The MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of the second MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of the second source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of the second drain terminal. The floating gate G2 of the MOS transistor 12 of the nonvolatile storage element Ma2 corresponds to one example of the second gate terminal. The P-well region 122 of the nonvolatile storage element Ma2 corresponds to one example of the second bulk terminal.
The MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of the third MOS transistor. The source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of the third source terminal. The drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of the third drain terminal. The floating gate G1 of the MOS transistor 11 of the nonvolatile storage element Ma1 corresponds to one example of the third gate terminal.
The MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of the fourth MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of the fourth source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of the fourth drain terminal. The floating gate G2 of the MOS transistor 12 of the nonvolatile storage element Ma1 corresponds to one example of the fourth gate terminal. The P-well region 122 of the nonvolatile storage element Ma1 corresponds to one example of the fourth bulk terminal.
In the reference voltage generation circuit 3, the MOS transistors 11 of the nonvolatile storage elements Ma1 and Ma2 are N-channel MOS transistors, and the low voltage supply terminal Vss has a higher voltage than the voltage of the negative high voltage supply terminal −Vdd. Thus, in the reference voltage generation circuit 3, the low voltage supply terminal Vss corresponds to one example of the first power source terminal, and the negative high voltage supply terminal −Vdd corresponds to one example of the second power source terminal. Furthermore, in the reference voltage generation circuit 3, the drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma2 is connected to the low voltage supply terminal Vss via the terminal Td, and the source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma1 is connected to the negative voltage supply terminal −Vdd via the terminal Tc. The source region S1 of the MOS transistor 11 of the nonvolatile storage element Ma2 is connected to the drain region D1 of the MOS transistor 11 of the nonvolatile storage element Ma1 via the terminals Tc and Td.
The states of switches SW1 to SW9 in a state where the reference voltage generation circuit 3 illustrated in
SW1: −VDD
SW2: VSS
SW3: ON-state (connected to a connection node N1 between one terminal of the switch SW1 and the terminal Tc)
SW4: OFF-state (open)
SW5: ON-state (connected)
SW6: ON-state (connected)
SW7: ON-state (connected to a connection node N2 between one of three terminals of the switch SW7 and the terminal Td)
SW8: OFF-state (open)
SW9: VSS
When the nonvolatile storage element Ma1 is in a depletion state and the nonvolatile storage element Ma2 is in an enhancement state in the state illustrated in
By performing the same adjustment sequences as those of the first example of the first embodiment in the structure illustrated in
[Fourth Embodiment]
A reference voltage generation circuit according to a fourth embodiment of the invention will be described with reference to
The reference voltage generation circuit according to the present embodiment is a circuit configured to generate a reference voltage by using a plurality of nonvolatile storage elements Mb (see
The reference voltage generation circuit according to the present embodiment is a circuit configured to eliminate manufacturing variation in reference voltage that occurs due to difference of characteristics between respective circuit elements forming the circuit. The reference voltage generation circuit according to the present embodiment includes at least one or more depletion type transistors and at least one or more enhancement type transistors to which a current flows that is the same as or relevant to a current that flows to the depletion type transistor. The one or more depletion type transistors and the one or more enhancement type transistors forming the reference voltage generation circuit according to the present embodiment are nonvolatile storage elements configured to operate as single-layer polysilicon type PMOS transistors.
As illustrated in
The nonvolatile storage elements Mb1 and Mb2 are connected in series between the negative high voltage supply terminal −Vdd to which a negative high voltage is supplied and a low voltage supply terminal Vss to which a low voltage is supplied. The drain region D21 of the nonvolatile storage element Mb1 is connected to the negative high voltage supply terminal −Vdd via the terminal Td, and the source region S21 of the nonvolatile storage element Mb2 is connected to the low voltage supply terminal Vss via the terminal Tc. The source region S21 of the nonvolatile storage element Mb1 and the source region S2, the drain region D2, and the P+ regions 124a and 124b (see
Furthermore, the source region S21 of the nonvolatile storage element Mb1 and the drain region D21 of the nonvolatile storage element Mb2 are connected to each other via the terminal Tc and the terminal Td. To the connection portion between the source region S21 of the nonvolatile storage element Mb1 and the drain region D21 of the nonvolatile storage element Mb2 is connected the voltage output terminal OUT.
In the reference voltage generation circuit 4, the nonvolatile storage element Mb2 on the lower stage side (the low voltage supply terminal Vss side) is adjusted into an enhancement state, and the nonvolatile storage element Mb1 on the upper stage side (the negative high voltage supply terminal −Vdd side) is adjusted into a depletion state. The nonvolatile storage elements Mb1 and Mb2 both include a control gate (for example, the P-well region 122 of the control gate area CGA) and floating gates (for example, the floating gates G21, G2, and G3 of the respective areas). Thereby, the nonvolatile storage elements Mb1 and Mb2 can perform writing and erasing, and can hold a rewritten state for a long period. Since the MOS transistor 21 is formed of a PMOS transistor, the threshold voltage of the depletion type transistor is positive, and the threshold voltage of the enhancement type transistor is negative. Thus, the plurality of nonvolatile storage elements Mb1 and Mb2 provided in the reference voltage generation circuit 4 of the present embodiment include at least the nonvolatile storage element Mb1 having a positive threshold voltage and the nonvolatile storage element Mb2 having a negative threshold voltage.
An element area of each of the nonvolatile storage elements Mb1 and Mb2 provided in the reference voltage generation circuit 4 may be from 1000 μm2 to 1 mm2. The nonvolatile storage elements Mb1 and Mb2 do not have any array structure, even when having any such element area.
Constituent elements of the reference voltage generation circuit 4 can be made to correspond as follows.
The MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the first MOS transistor. The source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the first source terminal. The drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the first drain terminal. The floating gate G21 of the MOS transistor 21 of the nonvolatile storage element Mb2 corresponds to one example of the first gate terminal.
The MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the second MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the second source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the second drain terminal. The floating gate G2 of the MOS transistor 12 of the nonvolatile storage element Mb2 corresponds to one example of the second gate terminal. The P-well region 122 of the nonvolatile storage element Mb2 corresponds to one example of the second bulk terminal.
The MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the third MOS transistor. The source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the third source terminal. The drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the third drain terminal. The floating gate G21 of the MOS transistor 21 of the nonvolatile storage element Mb1 corresponds to one example of the third gate terminal.
The MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the fourth MOS transistor. The source region S2 of the MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the fourth source terminal. The drain region D2 of the MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the fourth drain terminal. The floating gate G2 of the MOS transistor 12 of the nonvolatile storage element Mb1 corresponds to one example of the fourth gate terminal. The P-well region 122 of the nonvolatile storage element Mb1 corresponds to one example of the fourth bulk terminal.
In the reference voltage generation circuit 4, the MOS transistors 21 of the nonvolatile storage elements Mb1 and Mb2 are P-channel MOS transistors, and the low voltage supply terminal Vss has a higher voltage than the voltage of the negative high voltage supply terminal −Vdd. Thus, in the reference voltage generation circuit 4, the low voltage supply terminal Vss corresponds to one example of the second power source terminal, and the negative high voltage supply terminal −Vdd corresponds to one example of the first power source terminal. Furthermore, in the reference voltage generation circuit 4, the drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb1 is connected to the negative high voltage supply terminal −Vdd via the terminal Td, and the source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb2 is connected to the low voltage supply terminal Vss via the terminal Tc. The drain region D21 of the MOS transistor 21 of the nonvolatile storage element Mb2 is connected to the source region S21 of the MOS transistor 21 of the nonvolatile storage element Mb1 via the terminals Td and Tc.
The states of switches SW1 to SW9 in a state where the reference voltage generation circuit 4 illustrated in
SW1: −VDD
SW2: VSS
SW3: ON-state (connected to a connection node N1 between one terminal of the switch SW5 and the terminal Tc)
SW4: OFF-state (open)
SW5: ON-state (connected)
SW6: ON-state (connected)
SW7: ON-state (connected to a connection node N2 between one terminal of the switch SW6 and the terminal Td)
SW8: OFF-state (open)
SW9: VSS
When the nonvolatile storage element Mb1 is in a depletion state and the nonvolatile storage element Mb2 is in an enhancement state in the state illustrated in
By performing the same adjustment sequences as those of the first example of the first embodiment in the structure illustrated in
[Fifth Embodiment]
Next will be a description of a reference voltage generation circuit using single-layer polysilicon nonvolatile storage elements having higher electric charge holding characteristics. Nonvolatile storage elements used in analog devices such as a reference voltage generation circuit require higher electric charge holding characteristics than nonvolatile storage elements treated as information of “1” or “0” in a nonvolatile memory or the like. In a fifth embodiment, polarities (P type/N type) of the floating gates of the nonvolatile storage elements described in the first to fourth embodiments are optimized to provide a reference voltage generation circuit excellent in electric charge holding characteristics. Hereinafter, a description will be given by exemplifying the structure of the reference voltage generation circuit according to the first embodiment. However, the same advantageous effects can also be obtained by applying the present embodiment to the structures of the reference voltage generation circuits according to the second to fourth embodiments.
The fifth embodiment optimizes the floating gate polarity of a nonvolatile storage element used as a depletion type transistor and the floating gate polarity of a nonvolatile storage element used as an enhancement type transistor, from the viewpoint of respective electric charge holding characteristics.
In the respective areas MFA, CGA, and CIA illustrated in
Here is an example of a case in which, for example, the threshold voltage in the state where there is no electric charge injected in the floating gate is 1 V when using the N-type floating gate, and 2 V when using the P-type floating gate. Using such a device, a reference voltage Vref of 3 V is output. When forming a reference voltage generation circuit 5 as illustrated in
When 3 V as the reference voltage Vref is output while allowing a nA (nanoampere) order micro current to flow (in other words, when the MOS transistor 11 of each of the nonvolatile storage elements Ma1 and Ma1 operates at around the threshold voltage), it is necessary that, in the nonvolatile storage element Ma1 operated at a gate-source voltage Vgs of 0 V, positive electric charge is previously injected into the floating gate G1 so that the threshold voltage becomes slightly negative. On the other hand, in the nonvolatile storage element Ma2 operated at a gate-source voltage Vgs of 3 V, negative electric charge needs to be previously injected into the floating gate G1 so that the threshold voltage becomes smaller than the reference voltage Vref by a value slightly smaller than 3 V. At this time, the floating gate G1 of the nonvolatile storage element Ma1 is set to N type, and the floating gate G1 of the nonvolatile storage element Ma2 used as the enhancement type transistor is set to P type. In this manner, the amount of electric charge to be injected into each of the nonvolatile storage elements Ma1 and Ma2 can be reduced, whereby the amount of electric charge leaking out from within the floating gates G1 and G2 is reduced, thus enabling improvement in the electric charge holding characteristics of the reference voltage generation circuit 5.
Next will be a description of the polarity of the floating gate (hereinafter referred to as “floating gate polarity”) of the control gate area CGA. The floating gate polarity of the control gate area CGA serves to reduce an electric field applied on the gate insulating film 123 of the control gate area CGA in the state where electric charge is injected in the floating gate G2. The reason for this will be as below.
In the control gate area CGA, the value of an insulating film capacitance C2 of the gate insulating film 123 needs to be sufficiently large compared to that in the MOSFET area MFA and the electric charge injection area CIA. In other words, the gate insulating film 123 needs to be made larger in area than the gate insulating films 113 and 133 of the other two areas MFA and CIA. Due to this, since the gate insulating film 123 of the control gate area CGA becomes a main path of electric charge leakage, an electric field applied to the gate insulating film 123 is made small. Reducing the electric field applied to the gate insulating film 123 of the control gate area CGA in the electric charge injected state enables significant improvement in the electric charge holding characteristics of the reference voltage generation circuit 5.
More specifically, for example, in the reference voltage generation circuit 5 configured to output a reference voltage Vref, illustrated in
Lastly, a description will be given of the floating gate polarity of the electric charge injection area. The gate insulating film 133 of the electric charge injection area CIA allows a tunnel current to flow therethrough when electric current is injected, and therefore tends to become more defective than the gate insulating films 113 and 123 of the other areas MFA and CGA. Accordingly, the gate insulating film 133 of the electric charge injection area CIA can be a path of electric charge leakage, although it is small in area than the gate insulating film 123 of the control gate area CGA. Even in the electric charge injection area CIA, from exactly the same perspective as in the control gate area CGA illustrated in
Here, in the reference voltage generation circuit 5 configured to output the reference voltage Vref, illustrated in
It can be seen that the electric charge holding characteristics have been significantly influenced by the floating gate polarities. Regarding the electric charge holding characteristics of the present example, the best combination of the floating gate polarities in the nonvolatile storage element of the enhancement type transistor side is a combination of P type in the MOSFET area MFA, N type in the control gate area CGA, and N type in the electric charge injection area CIA. Additionally, the best combination of the floating gate polarities in the nonvolatile storage element of the depletion type transistor side is a combination obtained by inverting the polarities of the enhancement type transistor side. Specifically, the best combination of the floating gate polarities in the nonvolatile storage element of the depletion type transistor side is a combination of N type in the MOSFET area MFA, P type in the control gate area CGA, and P type in the electric charge injection area CIA.
The polarities (P-type) of the floating gates of the MOSFET area MFA in
As illustrated in
MOS transistor 12 and a silicide 16 formed on the PN junction portion 17.
As illustrated in
In addition, as illustrated in
Thus, it is preferable that the nonvolatile storage element Ma according to the present embodiment include at least one of the structure in which the conductivity type of the floating gate G1 is different from the conductivity type of the source region S1 in the MOS transistor 11 and the structure in which the conductivity type of the floating gate G2 is different from the conductivity type of the source region S2 in the MOS transistor 12.
The nonvolatile storage element Ma according to the present embodiment further includes a MOS transistor 13 (one example of the third MOS transistor) including a floating gate G3 that is connected to the floating gate G2 of the MOS transistor 12 and is the other conductive type of P type or N type (one example of the third gate), as well as a source region S3 (one example of the third source region), a drain region D3 (one example of the third drain region), and a P-well region 132 (one example of a third bulk region) that are connected to each other.
As illustrated in
In addition, as illustrated in
Thus, it is preferable that the nonvolatile storage element Ma according to the present embodiment include at least one of the structure in which the conductivity type of the floating gate G1 is different from the conductivity type of the source region S1 in the MOS transistor 11, the structure in which the conductivity type of the floating gate G2 is different from the conductivity type of the source region S2 in the MOS transistor 12, the structure in which the conductivity type of the floating gate G3 is different from the conductivity type of the source region S3 in the MOS transistor 13.
In addition, some or each of the MOSFET area MFA, the control gate area CGA, and the electric charge injection area CIA of the nonvolatile storage elements Ma may include a PMOS based structure including a source region and a drain region of P-type.
For example,
In the nonvolatile storage elements Ma illustrated in
The drain region D12 and the source region S12 are P+ regions formed inside the N-well region 125. The drain region D13 and the source region S13 are P+ regions formed inside the N-well region 135.
In the MOS transistor 31 in the nonvolatile storage element Ma illustrated in
As described above, the nonvolatile storage element Ma according to the present invention may include a structure in which the conductivity type of the floating gate is different from the conductivity type of the source region in at least one of the plurality of MOS transistors.
In this manner, by appropriately optimizing the floating gate polarities of the respective areas MFA, CGA, and CIA, excellent electric charge holding characteristics can be obtained. Note that when changing the floating gate polarity of each one area among the MFA, the CGA, and CIA, it is necessary to previously silicide the surface of polysilicon forming the floating gates G1, G2, and G3, as illustrated in
As described hereinabove, by assembling the same reference voltage generation circuit as the first embodiment by using such nonvolatile storage elements, there can be provided a highly precise and highly versatile reference voltage generation circuit having excellent electric charge holding characteristics and capable of being formed of single layer polysilicon.
1, 2, 3, 4, 5, 100: Reference voltage generation circuit
11, 12, 13, 21, 32, 33: MOS transistor
14: Semiconductor substrate
15a, 15b: Connection portion
16: Silicide
17, 144a, 144b, 144c, 144d, 144e, 144f: PN junction portion
111, 121, 131: Deep N-well region
112, 122, 132, 141a, 141b: P-well region
113, 123, 133, 213: Gate insulating film
114, 124a, 124b, 143a, 134b: P+ region
126a, 126b, 136a, 136b: N+ region
142a, 142b, 142c, 142d, 142e, 142f, 125, 135, 212: N-well region
143a, 143b, 143c, 143d, 143e, 143f, 143g, 143h: Element isolation region
CGA: Control gate area
CIA: Electric charge injection area
D, D1, D2, D3, D12, D13, D21: Drain region
G: Gate
G1, G2, G3, G21: Floating gate
Ma, Ma1, Ma2, Mb, Mb1, Mb2: Nonvolatile storage element
MFA: MOSFET area
S, S1, S2, S3, S12, S13, S21: Source region
SW1 to SW9: Switch
Ta, Tb, Tc, Td, Te, Tf, Tg, Th: Terminal
Sakamoto, Toshiro, Takehara, Satoshi
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 4417263, | Feb 01 1980 | Kabushiki Kaisha Daini Seikosha | Semiconductor device |
| 5465231, | May 07 1993 | International Business Machines Corporation | EEPROM and logic LSI chip including such EEPROM |
| 20030107090, | |||
| 20050161745, | |||
| 20060267903, | |||
| 20060281240, | |||
| 20070058441, | |||
| 20090146731, | |||
| 20110115030, | |||
| 20120286343, | |||
| 20140021526, | |||
| 20150187782, | |||
| 20150221372, | |||
| JP2002368107, | |||
| JP2005216909, | |||
| JP2006013336, | |||
| JP2007294846, | |||
| JP2013246627, | |||
| JP2015011454, | |||
| JP465546, | |||
| JP6334190, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Mar 02 2018 | SAKAMOTO, TOSHIRO | Asahi Kasei Microdevices Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 045275 | /0848 | |
| Mar 06 2018 | TAKEHARA, SATOSHI | Asahi Kasei Microdevices Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 045275 | /0848 | |
| Mar 19 2018 | Asahi Kasei Microdevices Corporation | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Mar 19 2018 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
| Apr 05 2023 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Date | Maintenance Schedule |
| Oct 15 2022 | 4 years fee payment window open |
| Apr 15 2023 | 6 months grace period start (w surcharge) |
| Oct 15 2023 | patent expiry (for year 4) |
| Oct 15 2025 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Oct 15 2026 | 8 years fee payment window open |
| Apr 15 2027 | 6 months grace period start (w surcharge) |
| Oct 15 2027 | patent expiry (for year 8) |
| Oct 15 2029 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Oct 15 2030 | 12 years fee payment window open |
| Apr 15 2031 | 6 months grace period start (w surcharge) |
| Oct 15 2031 | patent expiry (for year 12) |
| Oct 15 2033 | 2 years to revive unintentionally abandoned end. (for year 12) |