semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a ubm pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The ubm pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the ubm pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
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4. A semiconductor package, comprising:
a chip;
a conductive pattern disposed over and electrically connected to the chip;
a dielectric layer, disposed over the conductive pattern and comprising a set of openings to expose the conductive pattern; and
a under-ball metallurgy (ubm) pattern, comprising a set of vias in the set of openings and a pad on the set of vias, wherein the pad is electrically connected to the conductive pattern through the set of vias, and a ratio of a total height (H) of the dielectric layer and the pad to a bottom critical dimension (BCD) of the via is equal to or larger than 0.2 (H/BCD=0.2 or H/BCD>0.2).
1. A semiconductor package, comprising:
a chip;
a redistribution circuit structure, disposed over and electrically connected to the chip and comprising a topmost conductive pattern;
a under-ball metallurgy (ubm) pattern disposed over and electrically connected to the topmost conductive pattern, wherein the ubm pattern comprises a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern;
a passive component mounted to the redistribution circuit structure through the ubm pattern; and
a solder region between the ubm pattern and the passive component.
17. A method of forming a semiconductor package, comprising:
forming a conductive pattern of a redistribution circuit structure over a chip to electrically connect the chip;
forming a dielectric layer comprising a set of openings over the conductive pattern, wherein the set of openings exposes the conductive pattern; and
forming a under-ball metallurgy (ubm) pattern to electrically connect the conductive pattern, wherein the ubm pattern comprises a set of vias in the set of openings and a pad on the set of vias over the dielectric layer, and a ratio of a total height (H) of the dielectric layer and the pad to a bottom critical dimension (BCD) of the via is equal to or larger than 0.2 (H/BCD=0.2 or H/BCD>0.2).
2. The semiconductor package of
3. The semiconductor package of
5. The semiconductor package of
6. The semiconductor package of
7. The semiconductor package of
8. The semiconductor package of
9. The semiconductor package of
11. The semiconductor package of
12. The semiconductor package of
13. The semiconductor package of
14. The semiconductor package of
15. The semiconductor package of
18. The method of
19. The method of
20. The method of
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This application claims the priority benefit of U.S. provisional application Ser. No. 62/578,534, filed on Oct. 30, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on.
Currently, integrated fan-out packages are becoming increasingly popular for their compactness. The integrated fan-out packages typically include a redistribution circuit structure laying over the molded integrated circuit devices such that the integrated circuit devices may be accessed.
Aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or over a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath”, “below”, “lower”, “over”, “overlying”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
A plurality of conductive posts 102 and the chip 104 are provided over the dielectric layer DI. The chip 104 is mounted onto the dielectric layer DI having the conductive posts 102 formed thereon. A die attach film (DAF) (not shown) is locate between the chip 104 and the dielectric layer DI for adhering the chip 104 onto the dielectric layer DI. The chip 104 is surrounded by the conductive posts 102. The chip 104 is, for example, a semiconductor die. The chip 104 may be a logic device die such as a Central Processing Unit (CPU) die, a Micro Control Unit (MCU) die, a Graphic Processing Unit (GPU) die, a mobile application die, or the like. The chip 104 includes a semiconductor substrate (not shown) and integrated circuit devices (such as active devices, which may include transistors and/or diodes, for example) in and/or on the semiconductor substrate. The chip 104 may further include an active surface 104a, a plurality of pads 104b distributed on the active surface 104a, a dielectric layer 104c covering the active surface 104a, a plurality of conductive pillars 104d, and a protection layer 104e. The pads 104b are partially exposed by the dielectric layer 104c, the conductive pillars 104d are disposed on and electrically connected to the pads 104b, and the protection layer 104e covers the conductive pillars 104d and the dielectric layer 104c. The conductive pillars 104d are copper pillars or other suitable metal pillars, for example. In some embodiments, the protection layer 104e may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer or other suitable polymers. In some alternative embodiments, the protection layer 104e may be made of inorganic materials.
The chip 104 is encapsulated (molded) in an encapsulating material 106, which surrounds the chip 104. The encapsulating material 106 is formed on the dielectric layer DI to encapsulate the conductive posts 102 and the chip 104. The encapsulating material 106 may include a molding compound, a molding underfill, a resin, an epoxy, and/or the like. The bottom surface of the encapsulating material 106 may be leveled with the bottom end of the chip 104. The top surface of the encapsulating material 106 may be level with or higher than the back surface 108A of the chip 104.
The redistribution circuit structure 108 electrically connected to the conductive pillars 104d of the chip 104 and the conductive posts 102 is formed on the top surfaces of the conductive posts 102, the top surface of the encapsulating material 106, the top surfaces of the conductive pillars 104d, and the top surface of the protection layer 110e. As shown in
In some embodiments, a plurality of UBM patterns 126 may be formed in the openings 114 respectively for connecting conductive terminals such as solder balls. The UBM patterns 126 may be formed simultaneously with or separately from the UBM patterns 120. In some embodiments, the UBM pattern 126 has a concave surface, for example. Generally, an improper ratio of a total height of the dielectric layer 110 and the pad (such as a portion of the UBM pattern 126 on the dielectric layer 110) to the bottom critical dimension of the via (such as a portion of the UBM pattern 126 in the dielectric layer 110) may cause the incomplete filling of the via and thus a concave surface of the pad (such as the concave surface of the UBM pattern 126). On contrary, in some embodiments, a ratio of a total height H of the dielectric layer 110 and the pad 124 to the bottom critical dimension BCD of the via 122a (i.e., the opening 106a) is equal to or larger than 0.2 (i.e., H/D=0.2 or H/D>0.2), for example. Therefore, the via 122a may fill the opening 112a completely, and the pad 124 has a substantially flat surface. Accordingly, the set of vias 122 provides a good connection between the pad 124 and the topmost conductive pattern 108b. The number of the UBM patterns 120, 126 and the vias 122a of the UBM patterns 120 is not limited in this disclosure.
Referring to
In some embodiments, the passive component 130 is a discrete passive device that is not formed in a same chip in which the active devices such as transistors and diodes are formed. Accordingly, the passive component 130 may be free from active devices built therein. The passive component 130 is also sometimes referred to as a Surface Mount Device (SMD) since the passive device is mounted on the surface of other package components, rather than being built in the same chip in which the active devices are formed. In some embodiments, the passive component 130 has a plurality of terminals (not shown), through which the passive component 130 is electrically connected to the UBM patterns 120. In some embodiments, the passive component 130 is a capacitor, an inductor, a resistor, or another type of passive device. The passive component 130 may be silicon based, wherein the passive device therein is formed starting from a semiconductor substrate such as silicon substrate. The passive component 130 may also be ceramic based. The passive component 130 may be used to tune the performance of the respective PoP structure.
Referring to
After the contact openings O are formed in the dielectric layer DI, a plurality of conductive terminals 134 are placed in the contact openings O, and the conductive terminals 134 are electrically connected to the conductive posts 102. As illustrated in
In some embodiments, the UBM pattern includes a set of vias arranged in an array and a pad disposed on and electrically connecting to the set of vias. Therefore, the UBM pattern may have a substantially flat and smooth surface, on which a depth of a concave portion or a height of a convex portion is less than 1 μm if present. Accordingly, the solder region formed on the UBM pattern is prevented from forming a cavity therein, which would be inspected by the x-ray inspection or burst to cause pressure violently variation during torture test. In other words, quality assurance or regulatory affairs issues caused by the cavity in the solder region between the UBM pattern and the passive component are prevented. In addition, the passive component can be jointed to the UBM pattern easily due to the smooth surface of the UBM pattern, and the stress between the pad of the UBM pattern and the topmost conductive pattern is lowered. Therefore, joint between the UBM pattern and the passive component can be improved, and the performance of the package can be also improved.
In accordance with some embodiments of the disclosure, a semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
In accordance with alternative embodiments of the disclosure, a semiconductor package includes a chip, a conductive pattern, a dielectric layer and a UBM pattern. The conductive pattern is disposed over and electrically connected to the chip. The dielectric layer is disposed over the conductive pattern and includes a set of openings to expose the conductive pattern. The UBM pattern includes a set of vias in the set of openings and a pad on the set of vias, wherein the pad is electrically connected to the conductive pattern through the set of vias, and a ratio of a total height (H) of the dielectric layer and the pad to a bottom critical dimension (BCD) of the via is equal to or larger than 0.2 (H/BCD=0.2 or H/BCD>0.2).
In accordance with yet alternative embodiments of the disclosure, a method of forming a semiconductor package includes the following steps. A conductive pattern of a redistribution circuit structure is formed over a chip to electrically connect the chip. A dielectric layer including a set of openings is formed over the conductive pattern, wherein the set of openings exposes the conductive pattern. A UBM pattern is formed to electrically connect the conductive pattern, wherein the UBM pattern includes a set of vias in the set of openings and a pad on the set of vias over the dielectric layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.
Tsai, Hao-Yi, Kuo, Tin-Hao, Lo, Teng-Yuan, Chang, Mao-Yen, Pan, Kuo-Lung, Lee, Tzung-Hui, Ting, Hao-Chun
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