A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.
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1. A method for fabricating semiconductor device, comprising:
providing a substrate having a first region and a second region;
forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region;
forming a first liner on the first fin-shaped structure and the second fin-shaped structure;
forming a first buffer layer on the first liner;
removing the first buffer layer on the first region;
forming an insulating layer on the first fin-shaped structure and the second fin-shaped structure; and
performing a curing process to combine the first buffer layer and the insulating layer into one unit while the first liner is on the first fin-shaped structure and the second fin-shaped structure and a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.
2. The method of
forming the first buffer layer on the first liner;
forming a patterned mask on the second region; and
using the patterned mask to remove part of the first buffer layer on the first region.
3. The method of
4. The method of
5. The method of
8. The method of
removing the patterned mask;
forming a second buffer layer on the first region and the second region;
forming an insulating layer on the second buffer layer;
performing the curing process after forming the insulating layer.
9. The method of
10. The method of
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1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method for fabricating fin-shaped structures having different widths.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
However, the design of fin-shaped structure in current FinFET fabrication still resides numerous bottlenecks which induces current leakage of the device and affects overall performance of the device. Hence, how to improve the current FinFET fabrication and structure has become an important task in this field.
According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first buffer layer on the first fin-shaped structure and the second fin-shaped structure; removing the first buffer layer on the first region; and performing a curing process so that a width of the first fin-shaped structure is different from a width of the second fin-shaped structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Referring to
According to an embodiment of the present invention, the fin-shaped structures 20 and the base 22 could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.
Alternatively, the fin-shaped structures 20 and the base 22 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12, and through an etching process, the pattern of the patterned mask is transferred to the substrate 12 to form the fin-shaped structures 20 and the base 22. Moreover, the formation of the fin-shaped structures 20 and the base 22 could also be accomplished by first forming a patterned hard mask (not shown) on the substrate 12, and a semiconductor layer composed of silicon germanium is grown from the substrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structures 20 and the base 22. These approaches for forming fin-shaped structure are all within the scope of the present invention.
Next, an in-situ steam generation (ISSG) process is conducted to form a liner 30 on the fin-shaped structures 20 and the base 22. Preferably, the liner 30 is made of material including but not limited to for example silicon oxide and the liner 30 is not only disposed on the sidewalls of the fin-shaped structures 20 and the base 22 but also on the surface of the substrate 12.
Next, an atomic layer deposition (ALD) process is conducted to form a liner 32 on the fin-shaped structures 20 on first region 14 and second region 16 and also on the base 22 on third region 18, and a buffer layer 34 is formed on the surface of the liner 32 thereafter. In this embodiment, the liner 32 preferably includes silicon oxide and the buffer layer 34 is preferably a silicon buffer film (SBF) or more specifically an amorphous silicon layer, but not limited thereto.
Next, as shown in
Next, as shown in
It should be noted that the etching process conducted in
Next, as shown in
Next, as shown in
Next, as shown in
It should be noted that since no buffer layer 34 is disposed on the fin-shaped structures 20 on the first region 14 while a single layer of buffer layer 34 is disposed on the fin-shaped structures 20 on the second region 16, more of the fin-shaped structures 20 on the first region 14 would be consumed while less of the fin-shaped structures 20 on the second region 16 would be consumed during the curing process 48 so that the width of each of the fin-shaped structures 20 on the first region 14 would be slightly less than the width of each of the fin-shaped structures 20 on the second region 16 after the curing process 48. Since the size of the base 22 on third region 18 is significantly greater than the size of the fin-shaped structures 20 on either first region 14 or second region 16, the width of the base 22 preferably remains unchanged relative to the fin-shaped structures 20 on either first region 14 or second region 16 after the curing process 48 even if no buffer layer 34 were disposed on the base 22. Moreover, it should be noted that the buffer layer 34 made of amorphous silicon is preferably transformed into silicon oxide during the curing process 48 thereby combining or uniting with the insulating layer 46 into one unit. As a result, the buffer layer 34 becomes invisible in
Next, as shown in
Referring to
Next, as shown in
Similar to the aforementioned embodiment, since only a single buffer layer 34 is disposed on the fin-shaped structures 20 on the first region 14 while two buffer layers 34, 54 are disposed on the fin-shaped structures 20 on the second region 16, more of the fin-shaped structures 20 on the first region 14 would be consumed and less of the fin-shaped structures 20 on the second region 16 would be consumed during the curing process 58 so that the width of each of the fin-shaped structures 20 on the first region 14 would be slightly less than the width of each of the fin-shaped structures 20 on the second region 16 after the curing process 58. Since the size of the base 22 on third region 18 is significantly greater than the size of each of the fin-shaped structures 20 on both first region 14 and second region 16, the width of the base 22 preferably remains unchanged relative to the fin-shaped structures 20 on the first region 14 and the second region 16 after the curing process 58. Moreover, the buffer layers 34, 54 made of amorphous silicon are preferably transformed into silicon oxide during the curing process 58 and combined with the insulating layer 56 into one unit. As a result, the buffer layers 34, 54 become invisible in
Next, as shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Chen, Hsin-Yu, Lin, Chun-Hao, Hsieh, Shou-Wei
Patent | Priority | Assignee | Title |
11581438, | Aug 12 2020 | United Microelectronics Corp. | Fin structure for fin field effect transistor and method for fabrication the same |
11862727, | Aug 12 2020 | United Microelectronics Corp. | Method for fabricating fin structure for fin field effect transistor |
Patent | Priority | Assignee | Title |
10121880, | Jan 07 2016 | Semiconductor Manufacturing International (Shanghai) Corporation; SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION | Fin field-effect transistor and fabrication method thereof |
7947551, | Sep 28 2010 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a shallow trench isolation structure |
9130014, | Nov 21 2013 | United Microelectronics Corp. | Method for fabricating shallow trench isolation structure |
9312188, | Jun 13 2013 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device |
9514990, | Aug 12 2014 | Samsung Electronics Co., Ltd. | Methods for manufacturing semiconductor devices having different threshold voltages |
9865710, | Mar 31 2015 | STMicroelectronics, Inc. | FinFET having a non-uniform fin |
20070212874, | |||
20100197096, | |||
20140370672, | |||
20150076617, | |||
20160190142, | |||
20160233088, | |||
20160315085, | |||
20170200810, | |||
20170278928, |
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