An image sensor includes a photoelectric device generating an electric charge from light; a feedback device generating a reset voltage using a predetermined reference voltage; and a pixel circuit generating a pixel voltage using the reset voltage and the electric charge, setting the reset voltage to the reference voltage using the feedback device a first period, and outputting the pixel voltage and the reset voltage during a second period.
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12. An image sensor, comprising:
a photoelectric device configured to generate an electric charge from light;
a feedback device configured to generate a reset voltage using a predetermined reference voltage; and
a pixel circuit configured to generate a pixel voltage using the reset voltage and the electric charge, set the reset voltage to the reference voltage using the feedback device during a first period, and output the pixel voltage and the reset voltage during a second period,
wherein the first period and the second period have a same duration, and the second period occurs after the first period.
1. An image sensor, comprising:
a photoelectric device configured to generate an electric charge from light;
a feedback device configured to generate a reset voltage using a predetermined reference voltage; and
a pixel circuit configured to generate a pixel voltage using the reset voltage and the electric charge, set the reset voltage to the reference voltage using the feedback device during a first period, and output the pixel voltage and the reset voltage during a second period,
wherein the pixel circuit comprises a reset transistor and a driving transistor,
wherein the feedback device comprises an operational amplifier including a first input terminal connected to an output of the driving transistor, a second input terminal receiving the reference voltage, and an output terminal providing the reset voltage to the reset transistor.
14. An image sensor, comprising:
a pixel array, including a plurality of pixels arranged along a plurality of row fines and a plurality of column lines, each of the plurality of pixels having a photoelectric device receiving light and generating an electric charge, a feedback device generating a reset voltage, and a pixel circuit generating a pixel voltage using the electric charge;
a row driver configured to set the reset voltage to a predetermined reference voltage by activating the feedback device included in each of the plurality of pixels connected to a first row the among the plurality of row lines during a single horizontal period and control each of the plurality of pixels connected to a second row line different from the first row line to output the pixel voltage and the reset voltage during the single horizontal period; and
a sampling circuit configured to detect the pixel voltage and the reset voltage from each of the plurality of pixels connected to the second row line during the single horizontal period,
wherein the feedback device comprises an operation amplifier comprising a first input terminal receiving the pixel voltage, a second input terminal receiving the reference voltage, and an output terminal providing the reset voltage.
2. The image sensor of
3. The image sensor of
4. The image sensor of
5. The image sensor of
6. The image sensor of
7. The image sensor of
8. The image sensor of
9. The image sensor of
10. The image sensor of
13. The image sensor of
15. The image sensor of
a floating diffusion node accumulating the electric charge;
a reset transistor receiving the reset voltage output by the feedback device through a drain terminal and setting an electric potential of the floating diffusion node to the reset voltage in response to a reset control signal input by the row driver;
a driving transistor generating the pixel voltage according to the electric potential of the floating diffusion node;
a first selection transistor connected to the feedback device and setting the reset voltage to the reference voltage; and
a second selection transistor outputting the pixel voltage and the reset voltage.
16. The image sensor of
17. The image sensor of
18. The image sensor of
19. The image sensor of
20. The image sensor of
21. The image sensor of
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This application claims the benefit of priority to Korean Patent Application No. 10-2016-0159662, filed on Nov. 28, 2016 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.
1. Technical Field
The present inventive concept relates to an image sensor.
2. Discussion of Related Art
Semiconductor-based image sensors generate electrical signals from received light and may include a pixel array having a plurality of pixels and a circuit driving the pixel array. Semiconductor-based image sensors have been widely used in smartphones, tablet PCs, laptop computers, televisions, and cameras. Each pixel in the pixel area may include multiple photoelectric devices generating an electric charge from light having different colors. However, when each pixel of an image sensor includes these multiple photoelectric devices, the images captured by the image sensor may be adversely affected by noise.
At least one exemplary embodiment of the present inventive concept may provide an image sensor capable of minimizing an effect of a noise component and accurately reading out a pixel voltage and a reset voltage.
According to an exemplary embodiment of the present inventive concept, an image sensor includes a photoelectric device configured to generate an electric charge from light; a feedback device configured to generate a reset voltage using a predetermined reference voltage; and a pixel circuit configured to generate a pixel voltage using the reset voltage and the electric charge, set the reset voltage to the reference voltage using the feedback device during a first period, and output the pixel voltage and the reset voltage during a second period.
According to an exemplary embodiment of the present inventive concept, an image sensor comprises a pixel array, including a plurality of pixels arranged along a plurality of row lines and a plurality of column lines, each of the plurality of pixels having a photoelectric device receiving light and generating an electric charge, a feedback device generating a reset voltage, and a pixel circuit generating a pixel voltage using the electric charge and the reset voltage; a row driver configured to set the reset voltage to a predetermined reference voltage by activating the feedback device included in each of the plurality of pixels connected to a first row line among the plurality of row lines during a single horizontal period, and control each of the plurality of pixels connected to a second row line different from the first row line to output the pixel voltage and the reset voltage during the single horizontal period; and a sampling circuit configured to detect the pixel voltage and the reset voltage from each of the plurality of pixels connected to the second row line during the single horizontal period.
According to an exemplary embodiment of the present inventive concept, an image sensor comprises a pixel array including a plurality of pixels arrayed along a plurality of row lines and a plurality of column lines; a memory device configured to store a reset voltage detected from the plurality of pixels; a row driver configured to sequentially select a first row line and a second row line among the plurality of row lines during each horizontal period; a sampling circuit configured to reset first pixels connected to the first row line and detect a reset voltage from the first pixels while the first row line is selected, and detect a pixel voltage from second pixels connected to the second row line while the second row line is selected; and an arithmetic circuit configured to calculate a difference between the pixel voltage detected from the second pixels and the reset voltage of the second pixels stored in the memory device.
According to an exemplary embodiment of the present inventive concept, a driving apparatus for driving an image sensor is provided. The driving apparatus includes a driving circuit configured to drive the image sensor. The driving circuit sets a reset voltage applied to a first pixel of a first row of the image sensor to a reference voltage during a first period. The driving circuit outputs the reset voltage and a first pixel voltage of the first pixel during a second period. The driving circuit outputs the reset voltage applied to a second pixel of a second row of the image sensor and a second pixel voltage of the second pixel during the first period.
The present inventive concept will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
Hereinafter, exemplary embodiments of the present inventive concept will be described with reference to the attached drawings.
With reference to
The pixel array 10 includes a plurality of pixels PX arranged along a plurality of row lines and a plurality of column lines. Each of the plurality of pixels PX includes a photoelectric device, such as a photodiode PD, receiving light and generating an electric charge from the received light. In an exemplary embodiment of the inventive concept, each of the plurality of pixels PX includes two or more photoelectric devices. In an embodiment, the two or more photoelectric devices included in a single pixel PX receive light having different colors and generate an electric charge from the received light. The two or more photoelectric devices included in the single pixel PX may be alternately stacked.
In an exemplary embodiment, each of the plurality of pixels PX includes a pixel circuit for generating a pixel voltage from an electric charge generated by a photoelectric device. In an exemplary embodiment, the pixel circuit includes a plurality of transistors. In an embodiment where a single pixel PX includes two or more photoelectric devices, each pixel PX includes two or more pixel circuits, in order to process an electric charge generated in each of the two or more photoelectric devices. In an exemplary embodiment where a first photoelectric device and a second photoelectric device are alternately stacked in a single pixel PX, the pixel circuit includes a first pixel circuit connected to the first photoelectric device and a second pixel circuit connected to the second photoelectric device. The first pixel circuit generates a first pixel voltage and the second pixel circuit generates a second pixel voltage. The first pixel circuit and the second pixel circuit may be implemented to be circuits having different structures.
In an embodiment, the sensor circuit 20 includes a row driver 21, a read-out circuit 22, and a timing controller 23. The sensor circuit 20 may control the pixel array 10 according to a command transmitted by the image processor 30. The row driver 21 may drive the plurality of pixels PX in row line units of the pixel array 10, according to a command input by the timing controller 23. In an exemplary embodiment, at least one row line is selected from among row lines included in the pixel array 10 by the row driver 21. The read-out circuit 22 is configured to detect a pixel voltage and a reset voltage from pixels PX connected to the at least one row line selected by the row driver 21, and generate image data. In an exemplary embodiment, an amount of time required for the row driver 21 to drive a single row line of the pixel array 10 is defined as a horizontal period. In an embodiment, the total time required for the row driver 21 to drive all the rows of the pixel array 10 is defined as a frame period. Thus, in an embodiment in which the number of row lines is m (m is a natural number of 2 or more), a single frame period includes m horizontal periods.
In an embodiment, the read-out circuit 22 includes a sampling circuit for detecting the pixel voltage and the reset voltage, as well as an analog-to-digital converter (ADC) for converting the detected voltages into digital values. In an embodiment, the sampling circuit includes a correlated double sampler (CDS). The CDS may detect the pixel voltage and the reset voltage from the pixels PX connected to a row line selected by the row driver 21.
The timing controller 23 may be operated by a command input by the image processor 30. The image processor 30 may control the row driver 21 and the read-out circuit 22 using the timing controller 23. In addition, the image processor 30 may generate an image based on image data output by the read-out circuit 22, and output the image to a display device, or store the image in a storage device, such as a memory device.
With reference to
The pixel array 40 includes a plurality of pixels PX. The plurality of pixels PX may be arranged in a plurality of row lines and a plurality of column lines. In an embodiment, the integrated circuit chip 50 includes the row driver 21, the read-out circuit 22, the timing controller 23, and the image processor 30 as illustrated in
In an exemplary embodiment, the memory 60 is provided as a single semiconductor package with the integrated circuit chip 50. The memory 60 may be implemented as a dynamic random-access memory (DRAM) or a static random-access memory (SRAM), and may be implemented as a non-volatile memory, in an exemplary embodiment. Data required for an operation of the integrated circuit chip 50 and a reset voltage detected from pixels PX during a frame period may be stored in the memory 60. In an embodiment, the integrated circuit chip 50 detects the reset voltage from the pixels PX during a frame period, and stores the detected reset voltage in the memory 60. The reset voltage stored in the memory 60 may include a reset noise component. In an embodiment, the integrated circuit chip 50 generates image data using the pixel voltage detected from the pixels PX during a frame period and the reset voltage stored in the memory 60. Since image data is generated using the pixel voltage and the reset voltage detected during the same frame period, a true CDS may be implemented in a pixel circuit having a three-transistor (3T) structure that excludes a transfer transistor.
With reference to
Pixels 100A and 100B may be arrayed in an m×n matrix (m and n are natural numbers of 2 or more) in a pixel array. In an embodiment, an isolation region 101 for preventing crosstalk is interposed between the pixels 100A and 100B disposed adjacently to each other. In an embodiment, light having different colors passes through a first color filter 160A and a second color filter 160B, respectively included in a first pixel 100A and a second pixel 100B, disposed adjacently to each other. In an exemplary embodiment, the first color filter 160A allows red light to pass therethrough, to be transmitted to the second photoelectric device 120, while the second color filter 160B allows blue light to pass therethrough to be transmitted to the second photoelectric device 120.
Each of the pixels 100A and 100B include the first photoelectric device 110 and the second photoelectric device 120, disposed in a stacking direction (a vertical direction in
In an embodiment, the first photoelectric device 110 includes an upper electrode layer 111 and a lower electrode layer 112, facing each other, and a color selection layer 113 interposed therebetween. In an embodiment, the color selection layer 113 generates an electric charge from light due to a photoelectric effect, and may include an organic material. In an embodiment, the color selection layer 113 includes a p-type layer, in which a main carrier is provided as a hole, and an n-type layer, in which a main carrier is provided as an electron. In an embodiment, the color selection layer 113 reacts with light having a specific wavelength and generates an electric charge. In an exemplary embodiment, the color selection layer 113 reacts with green light and generates an electric charge. In this case, light having any color except green is transmitted to the second photoelectric device 120 by color filters 160A and 160B. In an embodiment, the color selection layer 113 filters out green light and allows red and blue light to pass.
The upper electrode layer 111 and the lower electrode layer 112 may be formed using a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or tin oxide (SnO2), or a translucent material, such as a metal thin film. In an exemplary embodiment, the upper electrode layer 111 has a work function higher than or equal to that of the lower electrode layer 112. In an embodiment, the work function is a minimum thermodynamic work (energy) needed to remove an electron from a solid to a point in a vacuum immediately outside the solid surface.
The first pixel circuit 130 is connected to the first photoelectric device 110, and generates a first pixel voltage from an electric charge generated by the first photoelectric device 110. The second pixel circuit 140 is connected to the second photoelectric device 120, and generates a second pixel voltage from an electric charge generated by the second photoelectric device 120.
The first pixel circuit 130 is connected to the first photoelectric device 110 by a via electrode 150. The via electrode 150 may be provided as a micro through silicon via (μTSV). In an embodiment, the via electrode 150 includes an insulating portion 151 and a conductive portion 152. In an embodiment, the conductive portion 152 extends along a side wall of a pixel (e.g., 100A or 110B), and connects the first photoelectric device 110 to the first pixel circuit 130. The insulating portion 151 may be formed using an insulating material, such as silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), or hafnium oxide (HfOx). In an exemplary embodiment, one surface or side of the conductive portion 152 is connected to the lower electrode layer 112 of the first photoelectric device 110. In the embodiment, the other surface or side of the conductive portion 152 is connected to a circuit device among a plurality of circuit devices included in the first pixel circuit 130. In an exemplary embodiment, the conductive portion 152 is directly connected to a floating diffusion node included in the first pixel circuit 130. Thus, an electric charge generated in the first photoelectric device 110 does not pass through a transfer transistor, and may be directly accumulated at the floating diffusion node. In other words, the first pixel circuit 130 may be provided as a pixel circuit having a 3T structure. In an embodiment, the second pixel circuit 140, connected to the second photoelectric device 120, is provided as a pixel circuit having a four-transistor (4T) structure, which includes the transfer transistor.
In a pixel circuit having the 4T structure, a reset voltage is detected first in a single frame using the transfer transistor, and the pixel voltage is then detected later. In a pixel circuit having the 3T structure without the transfer transistor, the pixel voltage and the reset voltage are detected during different frame periods. Thus, in a case where noise components generated in a reset operation are different in respective frames, if a reset noise component is not properly processed, the reset voltage and the pixel voltage may not be accurately detected. In at least one embodiment of the present inventive concept, improper processing of the reset noise component may be avoided using a frame memory or a feedback technique.
A driving transistor 130D may be operated as a source follower amplifier, and may generate the pixel voltage using an electric charge accumulated in the floating diffusion node 131.
In an exemplary embodiment, the driving transistor 130D includes source/drain regions 132 and 133, a gate electrode 134, and a lightly doped region 135. The gate electrode 134 includes an electrode layer 134A and a gate insulating layer 134B. The lightly doped region 135 is formed between the source/drain regions 132 and 133, thereby implementing the driving transistor 130D as a native transistor having a threshold voltage close to 0V.
The floating diffusion node 131 may be formed in such a manner that an n-type impurity is injected into a well region 103 doped with a p-type impurity. Thus, a pn junction may be formed between the floating diffusion node 131 and the well region 103. As an electric potential of the floating diffusion node 131 is increased, a level of a leakage current may be increased in a direction opposite the pn junction. In order to reduce the level of a leakage current, the reset voltage of the first pixel circuit 130 may be set to be relatively low, and a depletion-mode transistor may be used as the driving transistor 130D. In this case, however, characteristics of the depletion-mode transistor, which is relatively vulnerable to low-frequency noise, may be problematic.
In an exemplary embodiment, the native transistor may be used as the driving transistor 130D, in order to solve the problem described above. Since, in terms of the native transistor, a channel region between the source/drain regions 132 and 133 is implemented as the lightly doped region 135, a noise problem caused by random dopant fluctuation may be solved. Since the native transistor is provided as a transistor without a threshold voltage, a driving transistor may be operated, even at a relatively low reset voltage.
The pixel circuit, according to the exemplary embodiment illustrated in
The driving transistor DX may be operated as a source follower buffer amplifier using an electric charge accumulated in the floating diffusion node FD. In an embodiment, the selection transistor SX is operated by a selection control signal SEL, input by a row driver (e.g., 21), and performs switching and addressing operations. In an embodiment, when the selection control signal SEL is input from the row driver and the selection transistor SX is turned on, a pixel voltage or a reset voltage is output to a column line COL connected to the selection transistor SX. The pixel voltage or the reset voltage may be detected by a sampling circuit included in a read-out circuit (e.g., 22).
The reset transistor RX is operated by a reset control signal RG, which is input by the row driver. The reset transistor RX may reset a voltage of the floating diffusion node FD by the reset control signal RG. In each of the exemplary embodiments illustrated in
In the exemplary embodiment illustrated in
In the exemplary embodiment illustrated in
With reference to
In an embodiment, the transfer transistor TX transmits an electric charge accumulated in the photoelectric device PD to the floating diffusion node FD in response to a transfer control signal TG transmitted from a row driver. The photoelectric device PD may use an electron as a main carrier. Operations of the reset transistor RX, the driving transistor DX, and the selection transistor SX may be similar to that described above with reference to
With reference to
The pixel array 210 may include a plurality of row lines ROW that extend in a direction, and column lines COL intersecting the row lines ROW. The row lines ROW and the column lines COL may be connected to pixels PX11 to PXmn, while each of the pixels PX11 to PXmn may include at least one photoelectric device and at least one pixel circuit. In an exemplary embodiment, each of the pixels PX11 to PXmn, includes at least one pixel circuit in which a floating diffusion FD node is directly connected to a photoelectric device PD without a transfer transistor TX, as illustrated in the exemplary embodiment of
As described above, in the pixel circuit, according to the exemplary embodiment illustrated in
The image sensor 200, according to an exemplary embodiment, may adopt various methods for effectively removing a noise component generated in the pixel circuit in which the floating diffusion FD is directly connected to the photoelectric device PD.
First, with reference to
In a case where a pixel circuit, according to the exemplary embodiment illustrated in
As a result, in the pixel circuit, according to the exemplary embodiment illustrated in
In an embodiment, with reference to
In an exemplary embodiment, the problem described above may be solved using various methods. With reference to the exemplary embodiment illustrated in
First,
In the exemplary embodiment illustrated in
In a case where an electric charge accumulation time (a shutter time) is taken as being three horizontal periods, in the exemplary embodiment illustrated in
In the exemplary embodiment illustrated in
With reference to
A first selection transistor SX1 and a second selection transistor SX2 are controlled by a first selection control signal SEL1 and a second selection control signal SEL2, respectively, and are connected to a feedback device FBA and a sampling circuit CDS. In an embodiment, the feedback device FBA is or includes at least one operational amplifier. An output terminal of the first selection transistor SX1 is connected to an inverting terminal of the operational amplifier included in the feedback device FBA. The output terminal of the second selection transistor SX2 may be connected to the inverting terminal of the sampling circuit CDS by a first switch SW1. In an exemplary embodiment, while a pixel is operated in the FBR mode, the first selection transistor SX1 is turned on, and the second selection transistor SX2 is turned off. In the embodiment, while the pixel is operated in the RIO mode, the first selection transistor SX1 is turned off, and the second selection transistor SX2 is turned on.
A reference voltage VREF is input to a non-inverting terminal of the operational amplifier included in the feedback device FBA, and the output terminal of the feedback device FBA is connected to a drain terminal of the reset transistor RX. In an exemplary embodiment, while the feedback device FBA is activated and the first selection transistor SX1 and the reset transistor RX are turned on, a feedback loop is formed by a drain terminal of the reset transistor RX, thereby fixing a node voltage of a floating diffusion node FD. Thus, while the pixel is operated in the FBR mode, a reset voltage of the pixel is set to be the reference voltage VREF by the feedback device FBA. In addition, the FBR mode and the RIO mode are implemented in different sampling periods, thereby sufficiently securing an operating time of the feedback device FBA. Thus, a reset noise component generated during a reset operation may be effectively removed.
In an embodiment, first, with reference to
While the feedback device FBA is operated in the FBR mode, the feedback device FBA inputs a feedback voltage for setting a pixel output as the reference voltage VREF into the drain terminal of the reset transistor RX. Since, in an exemplary embodiment, the FBR mode is separated from the RIO mode, sufficient time may be secured to operate in the FBR mode. In the FBR mode, the reset transistor RX is turned on. Thus, an electric potential of the floating diffusion node FD is reset as a value made by adding a threshold voltage of a driving transistor to the reference voltage VREF, and the pixel output is fixed to be the reference voltage VREF, thereby removing a reset noise component.
While the pixels connected to the [i+k]th row line ROWi+k are operated in the FBR mode during a single sampling period, the pixels connected to the [i]th row line ROWi are operated in the R/O mode during the same single sampling period. With reference to
In each of the pixels operated in the R/O mode, the electric potential of the floating diffusion node FD is changed by an electric charge generated in the photoelectric device PD. In a circuit, according to the exemplary embodiment illustrated in
The sampling circuit CDS may generate an analog output SOUT by comparing a ramp voltage VRMP and the pixel voltage VPIX, changed to have a predetermined slope. An output terminal of the sampling circuit CDS may be connected to a column counter. The column counter may count the number of clocks in a section in which a level of the ramp voltage VRMP is greater than a level of the pixel voltage VPIX, thereby converting the analog output SOUT into digital data.
In a case where readout of the pixel voltage VPIX has completed, the first switch SW1 is turned off, and the second switch SW2 is turned on, so that the reference voltage VREF is input into the inverting terminal of the sampling circuit CDS. Each of the pixels is first operated in the FBR mode, and then operated in the RIO mode. Thus, the reference voltage VREF is equal to the reset voltage output, in a case where the reset transistor RX resets the electric potential of the floating diffusion FD. The sampling circuit CDS may generate the analog output SOUT by comparing the ramp voltage VRMP and the reference voltage VREF. The column counter may count the number of clocks in a section in which a level of the ramp voltage VRMP is greater than a level of the reference voltage VREF, thereby converting the analog output SOUT into digital data.
With reference to
With reference to
In the R/O mode, the second selection transistor SX2 is turned on, while the reset transistor RX and the first selection transistor SX1 are turned off. The photoelectric device PD accumulates a hole generated by light in the floating diffusion FD. Thus, a level of the pixel voltage VPIX is higher than a level of the reference voltage VREF, as illustrated in
The image sensor, according to the exemplary embodiment described with reference to
With reference to
With reference to
The image sensor calculates a difference between the pixel voltage and the reset voltage detected in each of the first pixels during a single frame period in such a manner that a difference between the pixel voltage detected at time t4 from the first pixels, and the reset voltage of the first pixels detected at time t1 and stored in the frame memory is calculated. The image sensor may include an arithmetic circuit (e.g., a subtractor) for calculating the difference. Thus, since a reset noise component generated during a reset operation is equally reflected in the reset voltage and the pixel voltage, a true CDS may be implemented without separately removing the reset noise component.
With reference to
With reference to a first horizontal period H1, a floating diffusion node included in each of the mth pixels connected to the mth row line ROWm in the first sampling section RST are reset, while a sampling circuit detects the reset voltage of each of the mth pixels. In an embodiment, a level of the reset voltage of each of the mth pixels is higher than that of an ideal reset voltage VRST,ideal due to a positive (+) noise component. The reset voltage detected by the sampling circuit may be converted into a digital value by an analog-to-digital converter, and may be stored in the frame memory. In the second sampling section PIX, the pixel voltage is detected from each of the first pixels connected to the first row line ROW1. The pixel voltage detected in the first pixels may be converted into a digital value by the analog-to-digital converter.
The image sensor calculates a difference between the pixel voltage detected in the first pixels and the reset voltage of the first pixels stored in the frame memory. The reset voltage of the first pixels stored in the frame memory may be provided as a value detected at time t1 and stored in the frame memory. Thus, the image sensor may calculate a difference between the reset voltage and the pixel voltage detected in a single frame period. Since the reset noise component generated during the reset operation is equally reflected in the reset voltage and the pixel voltage, the true CDS may be implemented. The difference between the reset voltage and the pixel voltage may be calculated in a digital domain.
In the first sampling section RST of a second horizontal period H2, the reset voltage of the first pixels connected to the first row line ROW1 is detected. In an embodiment, the level of the reset voltage of the first pixels detected in the second horizontal period H2 is lower than that of the ideal reset voltage VRST,ideal due to a negative (−) noise component. The reset voltage of the first pixels detected in the second horizontal period H2 may be stored in the frame memory. In other words, the reset voltage of the first pixels previously stored in the frame memory is updated to be the reset voltage of the first pixels detected in the second horizontal period H2.
An operation of the image sensor, according to the exemplary embodiment illustrated in
With reference to
The image sensor detects a pixel voltage PIX-ROW1 (F1) from the first pixels connected to a first row line ROW1 during a first frame period F1. The image sensor calculates a difference between the pixel voltage PIX-ROW1 (F1) and a reset voltage RST-ROW1 (F1) stored in the frame memory FM, in a digital domain. An entirety of the pixel voltage PIX-ROW1 (F1) and the reset voltage RST-ROW1 (F1) is a voltage detected from the first pixels during the first frame period F1 of the first row line ROW1. Thus, the pixel voltage PIX-ROW1 (F1) and the reset voltage RST-ROW1 (F1) may include the same reset noise component, which may be removed by a CDS.
When the CDS for the first pixels connected to the first row line ROW1 has completed, the image sensor performs the CDS for second pixels connected to a second row line ROW2. With reference to
Before the pixel voltage PIX-ROW2 (F1) detected from the second pixels is detected, the reset voltage RST-ROW1 (F2) of each of the first pixels is detected in a second frame period F2. The reset voltage RST-ROW1 (F2) may be stored in the frame memory. Thus, the reset voltage RST-ROW1 (F1) of each of the first pixels previously stored may be updated.
When the CDS for the second pixels connected to the second row line ROW2 has completed, the image sensor performs the CDS for third pixels, connected to a third row line ROW3. In other words, the image sensor calculates a difference between a pixel voltage PIX-ROW3 (F1) of each of the third pixels and a reset voltage RST-ROW3 (F1) stored in the frame memory in the digital domain. In addition, the image sensor may detect the reset voltage RST-ROW2 (F2) of each of the second pixels entering the second frame period F2 to store in the frame memory, thus updating the reset voltage RST-ROW2 (F1) of each of the second pixels previously stored. By applying the operation described above to all row lines, the difference between the pixel voltage and the reset voltage detected in a single frame period may be calculated, and the reset noise component may be removed.
First, with reference to
In an embodiment, the feedback device FBA includes an operational amplifier receiving a reference voltage VREF at a non-inverting terminal and a pixel voltage VPIX at an inverting terminal. A reset noise component included in the reset voltage in a reset operation may be reduced by the feedback device FBA. Output of a sampling circuit CDS detecting the reset voltage may be input to a counter CNT. In an embodiment, the counter CNT compares the reset voltage with a ramp voltage VRMP and counts a clock signal, thus converting the reset voltage into a digital value and storing the digital value in a frame memory. Hereinafter, a description will be provided with reference to
With reference to
With reference to
In the exemplary embodiment illustrated in
In an exemplary embodiment, the reset voltage is stored in the frame memory with the reset noise component. However, dispersion of the reset voltage may be reduced using the feedback device FBA and the auto-zero switches AZ1 and AZ2, thus reducing the time DRST required for the counter CNT to convert the reset voltage into a digital value. Since the reset noise component is reflected in the pixel voltage to be subsequently detected, as well as in the reset voltage, the reset noise component may be removed by calculating the difference between the pixel voltage and the reset voltage. Thus, a true CDS may be implemented.
With reference to
The processor 1040 may perform a certain operation, a command, or task. The processor 1040 may be implemented by a central processing unit (CPU) or a microprocessor unit (MCU), and may communicate with the memory 1030, the I/O device 1020, the image sensor 1010, and other devices connected to the port 1050, through a bus 1060.
The memory 1030 may be provided as a storage medium, storing data necessary for operations of the computer device 1000, or multimedia data. The memory 1030 may include a volatile memory, such as a random access memory (RAM), or a non-volatile memory, such as a flash memory. In addition, the memory 1030 may include at least one of a solid state drive (SSD), a hard disk drive (HDD), and an optical disk drive (ODD), as a storage device. The I/O device 1020 may include an input device, such as a keyboard, a mouse, and a touchscreen, and an output device, such as a display and an audio output unit, provided to a user.
The image sensor 1010 may be connected to the processor 1040 through the bus 1060 or through other communications units. The processor 1040 may perform a function of the image processor 30 illustrated in
In other words, the image sensor 1010 may include a plurality of pixels, where two or more pixels disposed adjacently to each other form a group of pixels. Pixel circuits included in each of the pixels in a single pixel group may share a single column line, thus detecting a pixel voltage from the pixel circuits included in the same pixel during each scan period. Thus, since, in a case in which the pixel voltage is detected, a coupling component generated in an organic photodiode and a semiconductor photodiode, alternately stacked in the pixels, may be effectively removed, an occurrence of fixed pattern noise in a horizontal direction may be suppressed. In addition, since the pixel voltage may be prevented from being detected from the pixel circuits included in different pixels in each scan period, a process of rearranging image data may be simplified.
As set forth above, according to at least one exemplary embodiment of the present inventive concept, a feedback reset operation and a read-out operation are simultaneously performed in pixels connected to respective different row lines during a horizontal period. Thus, since sufficient time required for each of the feedback reset operation and the read-out operation may be secured, a noise component having a reset voltage may be effectively removed, and a high-speed read-out operation may be implemented. In addition, an effect of a reset noise component may be minimized in such a manner that the reset voltage is stored in a frame memory in advance, and a pixel voltage detected during a read-out operation is compared with the reset voltage stored in the frame memory.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments without departing from the scope of the present inventive concept.
Keel, Min-Sun, Koh, Kyoungmin, Ha, Sanghoon
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