An electrostatic discharge (esd) protection apparatus includes: an esd circuit, arranged to perform esd protection, wherein the esd circuit includes a first field effect transistor (fet) arranged to release esd energy; a detection circuit, arranged to perform detection to control the esd protection apparatus to selectively operate in one of a normal mode and a discharge mode; and a logic circuit, arranged to withstand any oscillation due to resistance-inductance-capacitance (RLC) characteristics of the detection circuit. In the detection circuit, different subsets of a plurality of resistors are respectively combined with a portion of a first serial connection circuit, an entirety of the first serial connection circuit, and a second fet to form different serial connection circuits, to configure the second fet to approach a state of being completely turned off in the normal mode.
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1. An electrostatic discharge (esd) protection apparatus, comprising:
an esd circuit, coupled between a first reference voltage wire and a second reference voltage wire of the esd protection apparatus, the esd circuit arranged to perform esd protection between the first reference voltage wire and the second reference voltage wire, wherein the first reference voltage wire is electrically connected to a first reference voltage, the second reference voltage wire is electrically connected to a second reference voltage, and the esd circuit comprises:
a first field effect transistor (fet), arranged to release esd energy, wherein a gate terminal of the first fet is used as a control terminal of the esd circuit;
a detection circuit, coupled between the first reference voltage wire and the second reference voltage wire, the detection circuit arranged to perform detection between the first reference voltage wire and the second reference voltage wire, in order to control the esd protection apparatus to selectively operate in one of a normal mode and a discharge mode, wherein the detection circuit comprises:
a plurality of fets, wherein a gate terminal and a drain terminal of each fet of the plurality of fets are electrically connected to each other in order to simulate a two-terminal element, and a plurality of two-terminal elements simulated by the plurality of fets are serially-coupled to each other in order to form a first series circuit;
a second fet, arranged to generate a detection signal based on circuit arrangements in the detection circuit, wherein the control terminal receives a derivative signal of the detection signal; and
a plurality of resistors, wherein different subsets of the plurality of resistors are respectively combined with a portion of the first series circuit, an entirety of the first series circuit and the second fet to form different series circuits, in order to configure the second fet to approach a completely turned-off state in the normal mode; and
a logic circuit, coupled between the esd circuit and the detection circuit, the logic circuit arranged to generate the derivative signal and to withstand any oscillation resulting from resistance-inductance-capacitance (RLC) characteristics in the detection circuit, wherein an output terminal of the logic circuit is electrically connected to the control terminal, in order to output the derivative signal to the control terminal.
2. The esd protection apparatus of
3. The esd protection apparatus of
a first resistor and a second resistor, wherein the first resistor, the second resistor, and X-th to last two-terminal elements in the first series circuit are serially-coupled to one another in order to form a second series circuit, wherein the symbol X represents an integer larger than 1;
a third resistor, wherein the third resistor and the first series circuit are serially-coupled to each other in order to form a third series circuit; and
a fourth resistor, wherein the first resistor, the second fet and the fourth resistor are serially-coupled to one another in order to form a fourth series circuit.
5. The esd protection apparatus of
6. The esd protection apparatus of
7. The esd protection apparatus of
8. The esd protection apparatus of
9. The esd protection apparatus of
the first subset of the plurality of resistors comprises:
a first resistor and a second resistor, wherein the first resistor, the second resistor, and X-th to last two-terminal elements in the first series circuit are serially-coupled to one another in order to form the second series circuit, wherein the symbol X represents an integer larger than 1;
the second subset of the plurality of resistors comprises:
a third resistor, wherein the third resistor and the first series circuit are serially-coupled in order to form the third series circuit; and
the third subset of the plurality of resistors comprises:
the first resistor and a fourth resistor, wherein the first resistor, the second fet and the fourth resistor are serially-coupled in order to form the fourth series circuit.
10. The esd protection apparatus of
11. The esd protection apparatus of
a first inverter, having an input terminal and an output terminal, wherein the input terminal of the first inverter is electrically connected to the second fet in order to receive the detection signal.
12. The esd protection apparatus of
13. The esd protection apparatus of
a second inverter, having an input terminal and an output terminal, wherein the input terminal of the second inverter is electrically connected to the output terminal of the first inverter;
wherein the logic circuit is coupled between the control terminal of the esd circuit and the output terminal of the second inverter.
14. The esd protection apparatus of
a first inverter and a second inverter, wherein an input terminal of the first inverter is electrically connected to an output terminal of the second inverter, an input terminal of the second inverter is electrically connected to an output terminal of the first inverter, and the input terminal of the second inverter is coupled to the detection signal via an output terminal of the detection circuit, wherein the control terminal is coupled to the output terminal of the second inverter.
15. The esd protection apparatus of
a third inverter, having an input terminal and an output terminal, wherein the input terminal of the third inverter is electrically connected to the output terminal of the second inverter, and the output terminal of the third inverter is electrically connected to the control terminal.
16. The esd protection apparatus of
a level shifter, arranged to perform level shifting operations, wherein the level shifter has an input terminal and an output terminal, the input terminal of the level shifter is coupled to the detection signal via an output terminal of the detection circuit, and the output terminal of the level shifter is electrically connected to the control terminal;
wherein the esd protection apparatus utilizes the level shifter to block any oscillation resulting from resistance-inductance-capacitance (RLC) characteristics in the detection circuit.
17. The esd protection apparatus of
18. The esd protection apparatus of
19. The esd protection apparatus of
20. The esd protection apparatus of
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The present invention relates to circuit protections, and more particularly, to an electrostatic discharge (ESD) protection apparatus.
A transistor can be used to release ESD energy applied to a target circuit, in order to prevent the target circuit from being damaged. This ESD protection mechanism may have some problems, however. For example, improper controls may cause the transistor to operate incorrectly, resulting in current leakage problems at the transistor.
When incorrect operations of the transistor lead to extra power consumption, the power for driving the target circuit will also correspondingly be increased. When there are N target circuits in an integrated circuit (IC) (wherein N can be any integer larger than 1, such as 200), the total power consumption will be N times the power consumption mentioned above, wherein one of the target circuits may need to be protected by at least one (e.g. one or more) replica of the transistor. In this way, the related art ESD protection mechanism may cause electronic devices equipped with the above IC to have high IC power consumption. Hence, there is a need for a novel mechanism to improve the existing ESD protection control mechanism.
An objective of the present invention is to provide an ESD protection apparatus in order to solve the problems existing in the related arts.
Another objective of the present invention is to provide an ESD protection apparatus in order to reduce current leakage and power consumption.
According to at least one embodiment of the present invention, an ESD protection apparatus is provided. The ESD protection apparatus comprises an ESD circuit, a detection circuit and a logic circuit. The ESD circuit is coupled between a first reference voltage wire and a second reference voltage wire of the ESD protection apparatus. The ESD circuit is arranged to perform ESD protection between the first reference voltage wire and the second reference voltage wire. The first reference voltage wire is electrically connected to a first reference voltage, the second reference voltage wire is electrically connected to a second reference voltage, and the ESD circuit comprises a first field effect transistor (FET). The first FET is arranged to release ESD energy, wherein a gate terminal of the first FET is used as a control terminal of the ESD circuit. The detection circuit is coupled between the first reference voltage wire and the second reference voltage wire. The detection circuit is arranged to perform detection between the first reference voltage wire and the second reference voltage wire for controlling the ESD protection apparatus to selectively operate in one of a normal mode and a discharge mode. The detection circuit comprises a plurality of FETs, a second FET and a plurality of resistors. A gate terminal and a drain terminal of each FET of the plurality of FETs are electrically connected to each other in order to simulate a two-terminal element, and a plurality of two-terminal elements simulated by the plurality of FETs are serially-coupled to each other in order to forma first series circuit. The second FET is arranged to generate a detection signal based on circuit arrangements in the detection circuit, wherein the control terminal receives a derivative signal of the detection signal. Different subsets of the plurality of resistors are respectively combined with a portion of the first series circuit, an entirety of the first series circuit and the second FET to form different series circuits, in order to configure the second FET to approach a completely turned-off state in the normal mode. The logic circuit is coupled between the ESD circuit and the detection circuit. The logic circuit is arranged to generate the derivative signal and to withstand any oscillation resulting from resistance-inductance-capacitance (RLC) characteristics in the detection circuit, wherein an output terminal of the logic circuit is electrically connected to the control terminal, in order to output the derivative signal to the control terminal.
The ESD protection apparatus of the present invention may solve problems of the related arts without introducing unwanted side effects, or in a way that is less likely to introduce a side effect. For example, the ESD protection apparatus of the present invention may tightly turn off the second FET in the normal mode, making the amount of current leakage in the first FET very tiny. Compared with related art mechanisms, the ESD protection apparatus of the present invention may greatly reduce the power consumption.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
As shown in
According to this embodiment, the ESD circuit 10 may be arranged to perform ESD protection between the first reference voltage wire RVW1 and the second reference voltage wire RVW2. The first FET FET1 may be arranged to release ESD energy, wherein the gate terminal of the first FET FET1 may be used as a control terminal of the ESD circuit 10, such as the terminal at the right-hand side of the node ND. Further, the detection circuit 110 may be arranged to perform detection between the first reference voltage wire RVW1 and the second reference voltage wire RVW2, in order to control the ESD protection apparatus 100 to selectively operate in one of a normal mode and a discharge mode. In the normal mode, the ESD protection apparatus 100 may stay in an inactive state in order to allow a target circuit (such as that mentioned above) to perform its normal functions, wherein the detection module 105 may control the first FET FET1 to remain in the turned-off state without the current leakage problem of the related art. In another example, in the discharge mode, the ESD protection apparatus 100 may stay in an active state, especially by releasing the ESD energy via the first FET FET1, in order to prevent the target circuit from being damaged.
In order to prevent the current leakage problem, the present invention provides a properly designed circuit mechanism, such as the mechanism shown in
In one example, each above-mentioned series circuit is electrically connected between the first reference voltage wire RVW1 and the second reference voltage wire RVW2. The plurality of resistors may comprise a first resistor, a second resistor, a third resistor and a fourth resistor.
For better comprehension, the resistors R1, R2, R3 and R4 may be examples of the first resistor, the second resistor, the third resistor, and the fourth resistor, respectively. The first resistor R1, the second resistor R2, and the X-th two-terminal element to the last two-terminal element in the first series circuit (e.g. the X-th FET FETS(X) in the plurality of FETs to the last FET FETS (Xmax) in the plurality of FETs, counted starting from the uppermost one) is serially-coupled to each other in order to form a second series circuit, wherein the symbol “Xmax” represents the total of the plurality of FETs and the symbol X represents an integer larger than 1, e.g. X=2. Further, the third resistor R3 and the first series circuit (e.g. the FETS FETS(1), FETS(2), FETS(3), and FETS(4)) are serially-coupled to each other in order to forma third series circuit. In addition, the first resistor R1, the second FET FET2 and the fourth resistor R4 are serially-coupled to form a fourth series circuit. In this way, it can be seen from the mechanism shown in
As shown in
The logic circuit 120 may be arranged to generate the derivative signal and withstand any oscillation resulting from the resistance-inductance-capacitance (RLC) characteristics in the detection circuit 110, wherein an output terminal of the logic circuit 120 (e.g. the terminal at the left-hand side of the node ND) is electrically connected to the control terminal of the FET FET1 (e.g. the terminal at the right-hand side of the node ND), in order to output the derivative signal to the control terminal of the FET FET1.
One of the first inverter INV11 and second inverter INV12 in the logic circuit 120 may receive the output signal of the other of the first inverter INV11 and the second inverter INV12. For example, an input terminal of the first inverter INV11 is electrically connected to an output terminal of the second inverter INV12, and an input terminal of the second inverter INV12 is electrically connected to an output terminal of the first inverter INV11. Further, the input terminal of the second inverter INV12 may be coupled to the detection signal S1 via the output terminal of the detection circuit 110 (e.g. the terminal at the left-hand side of the node NB), and more specifically, via the inverters INV1 and INV2 that are coupled to the terminal at the node NB1. Further, the control terminal (e.g. the terminal at the right-hand side of the node ND) may be coupled to the output terminal of the second inverter INV12 in the logic circuit 120 (e.g. the terminal at the left-hand side of the node NC). For example, a third inverter INV13 in the logic circuit 120 has an input terminal and an output terminal, wherein the input terminal of the third inverter INV13 (e.g. the terminal at the right-hand side of the node NC) is electrically connected to the output terminal of the second inverter INV12 (e.g. the terminal at the left-hand side of the node NC), and the output terminal of the third inverter INV13 (e.g. the terminal at the left-hand side of the node ND) is electrically connected to the control terminal (e.g. the terminal at the right-hand side terminal of the node ND).
According to this embodiment, regarding configuring the second FET FET2 to approach the completely turned-off state in the normal mode, when a non-ESD pulse is applied between the first reference voltage wire RVW1 and the second reference voltage wire RVW2, the duration of current leakage of the first FET FET1 in the normal mode in response to the non-ESD pulse is less than 0.2 nanoseconds, which is less than in the related art techniques. Further, when a non-ESD pulse (such as that mentioned above) is applied between the first reference voltage wire RVW1 and the second reference voltage wire RVW2, the amount of leakage current of the first FET FET1 in the normal mode in response to the non-ESD pulse is less than 200 milliamperes, which is much less than in the related art techniques.
Based on the circuit mechanism of the logic circuit 120 shown in
Regarding configuring the second FET FET2 to approach the completely turned-off state in the normal mode, when the non-ESD pulse is applied between the first reference voltage wire RVW1 and the second reference voltage wire RVW2, the amount of current leakage of the first FET FET1 in the normal mode in response to the non-ESD pulse (which is typically 800 microamperes or 0.8 milliamperes) may be at least smaller than 1 milliampere. Hence, in the mechanism of the present invention, the amount of current leakage of the first FET FET1 is much less than in the related art techniques.
According to some embodiments, in order to tightly turn off the second FET FET2 in the normal mode, the circuit mechanism in the detection circuit 110 may be designed according to the following equations:
VCC−(Isub4*R3)>VCC−(Isub3*R1) (1);
(IR3*R3)+4Vth<(IR1*(R1+R2))+3Vth (2);
wherein the symbol “VCC” represents the driving voltage; the italic symbols “R1”, “R2”, “R3” and “R4” respectively represent the resistance values of the resistors R1, R2, R3 and R4; the symbols “Isub3” and “Isub4” respectively represent the current passing through the three FETs FETS(2), FETS(3), and FETS(4) and the current passing through the four FETs FETS(1), FETS(2), FETS(3), and FETS(4); the symbols “IR1” and “IR3” respectively represent the current passing through the resistor R1 and the current passing through the resistor R3; and the symbol “Vth” represents the turned-on voltage threshold of any FET of the FETs FETS(1), FETS(2), FETS(3), and FETS(4). Some features in this embodiment that are similar to those of the previous embodiments are omitted here for brevity.
Some details regarding the curve passing through the origin O shown in
In the mechanism shown in
According to some embodiments, the above-mentioned different series circuit may comprise the second series circuit, the third series circuit and the fourth series circuit. In addition, a first subset of the plurality of resistors (e.g. the resistors R1 and R2) and the portion of the first series circuit (e.g. the FETs FETS(2), FETS(3), and FETS (4)) form the second series circuit; a second subset of the plurality of resistors (e.g. the resistor R3) and the entirety of the first series circuit (e.g. the FETs FETS(1), FETS(2), FETS(3), and FETS(4)) form the third series circuit; and a third subset of the plurality of resistors (e.g. the resistors R1 and R4) and the second FET FET2 form the fourth series circuit. For example, the first subset of the plurality of resistors may comprise two or more resistors, such as the first resistor R1 and the second resistor R2; and the second subset of the plurality of resistors may comprise one or more resistors, such as the third resistor R3. In addition, the third subset of the plurality of resistors may comprise two or more resistors, such as the first resistor R1 and the fourth resistor R4. In another example, any resistor in any subset of the three subsets of the plurality of resistors, such as any of the resistors R1, R2, R3 and R4, may be replaced with multiple resistors. Further, in the first subset of the plurality of resistors (e.g. the resistors R1 and R2), there is no resistor belonging to the second subset of the plurality of resistors (e.g. the resistor R3); in the second subset of the plurality of resistors (e.g. the resistor R3), there is no resistor belonging to the first subset of the plurality of resistors (e.g. the resistors R1 and R2); and there is at least one resistor (e.g. the resistor R1) that belongs to the third subset of the plurality of resistors (e.g. resistor R1 and R4) in the first subset of the plurality of resistors (e.g. the resistors R1 and R2).
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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