An electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall of the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative coefficient of thermal expansion (cte).
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21. An electrical device, comprising:
a substrate having a first surface and defining a through hole having a sidewall;
an active circuit layer;
a via disposed in the through hole and comprising:
an insulation ring disposed on the first surface of the substrate and adjacent to the sidewall of the through hole; and
one or more conductive portions including a first conductive cup disposed in the insulation ring, the first conductive cup being in direct contact with the active circuit layer; and
a patterned conductive layer having a negative coefficient of thermal expansion (cte) disposed on the first surface of the substrate,
wherein the patterned conductive layer is electrically insulated from the conductive portions of the via.
14. An electrical device, comprising:
a substrate having a first surface that defines at least a portion of a recess, and a second surface opposite to the first surface;
an active circuit layer disposed on the second surface; and
a via disposed in the recess, the via comprising:
an insulation ring disposed on the first surface and adjacent to a sidewall of the recess;
a first conductive cup disposed in the insulation ring, the first conductive cup being in direct contact with the active circuit layer;
a second conductive cup disposed in the first conductive cup, wherein a coefficient of thermal expansion (cte) of the second conductive cup is negative; and
an insulation layer disposed in the second conductive cup; and
a stress adjusting layer disposed on and in contact with the first surface of the substrate, and wherein a cte of the stress adjusting layer is negative.
1. An electrical device, comprising:
a substrate having a first surface and defining a recess in the first surface;
an active circuit layer; and
a via disposed in the recess, the via comprising:
an insulation layer disposed on the first surface of the substrate and extending at least to a sidewall of the recess;
a first conductive layer disposed adjacent to the insulation layer and extending over at least a portion of the first surface of the substrate, the first conductive layer being in direct contact with the active circuit layer;
a second conductive layer disposed adjacent to the first conductive layer and extending over at least a portion of the first surface of the substrate, the second conductive layer having a negative coefficient of thermal expansion (cte); and
a stress adjusting layer disposed on and in contact with the first surface of the substrate, and wherein a cte of the stress adjusting layer is negative.
8. An electrical device, comprising:
a substrate having a first surface that defines at least a portion of a recess, and a second surface opposite to the first surface;
an active circuit layer disposed on the second surface of the substrate; and
a via disposed in the recess, the via comprising:
a first insulation layer disposed adjacent to a sidewall of the recess;
a first conductive layer disposed adjacent to the first insulation layer, wherein a coefficient of thermal expansion (cte) of the first conductive layer is positive, and the first conductive layer is in direct contact with the active circuit layer;
a second conductive layer disposed adjacent to the first conductive layer, and wherein a cte of the second conductive layer is negative,
a second insulation layer disposed adjacent to the second conductive layer, wherein a cte of the second insulation layer is positive and wherein the second conductive layer surrounds the second insulation layer; and
a stress adjusting layer disposed on and in contact with the first surface of the substrate, and wherein a cte of the stress adjusting layer is negative.
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The present disclosure relates to an electrical device and a method of manufacturing the same.
A semiconductor device package may include a semiconductor device having a substrate (e.g. a silicon substrate). The silicon substrate may include a through-silicon via (TSV) structure. The TSV structure may include a conductive structure surrounded by a passivation layer. Delamination may occur at or close to a boundary between the conductive structure and the passivation layer due to coefficient of thermal expansion (CTE) mismatch. Delamination issues can adversely affect reliability of the semiconductor device package.
In one or more embodiments, an electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall defining the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative CTE.
In one or more embodiments, an electrical device includes a substrate and a via. The substrate has a first surface that defines at least a portion of a recess, and a second surface opposite to the first surface. The via is disposed in the recess. The via includes a first insulation layer disposed adjacent to a sidewall of the recess; a first conductive layer disposed adjacent to the insulation layer, wherein a CTE of the first conductive layer is positive; a second conductive layer disposed on the first conductive layer, and wherein a CTE of the second conductive layer is negative, a second insulation layer disposed on the second conductive layer, wherein a CTE of the second insulation layer is positive and wherein the second conductive layer surrounds the second insulation layer.
In one or more embodiments, an electrical device includes a substrate, an active circuit layer and a via. The substrate includes a first surface defining at least a portion of a recess, and a second surface opposite to the first surface. The active circuit layer is disposed on the second surface. The via is disposed in the recess. The via includes an insulation ring disposed one the first surface and adjacent to a sidewall defining the recess; a first conductive cup in the insulation ring; a second conductive cup in the first conductive cup, and wherein a CTE of the second conductive cup is negative, an insulation layer disposed in the second conductive cup.
In one or more embodiments, an electrical device includes a substrate, a via and a patterned conductive layer. The substrate has a first surface and defines a through hole. The via is disposed in the through hole and includes one or more conductive portions. The patterned conductive layer has a negative CTE and is disposed on the first surface. The patterned conductive layer is electrically insulated from the conductive portions of the via.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements. Embodiments of the present disclosure will be readily apparent from the following detailed description taken in conjunction with the accompanying drawings.
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.
The substrate 10 has a surface 101u (also referred to herein as a “first surface”) and defines a recess 101r in the surface 101u. The substrate 10 has a surface 101b (also referred to herein as a “second surface”) opposite to the surface 101u. The substrate 10 defines a through hole 101h (e.g. at least a portion of which is constituted by the recess 101r). The via 30 includes an insulation layer 40, an insulation layer 42, a conductive layer 80 and a conductive layer 82. The via 30 is disposed in the recess 101r. In some embodiments, the via 30 is disposed in the through hole 101h.
The insulation layer 40 is disposed on the surface 101u of the substrate 10 and extends at least to a sidewall 101s of the recess 101r. The insulation layer 40 is disposed adjacent to the sidewall 101s of the recess 101r. In one or more embodiments, the insulation layer 40 includes a ring portion (also referred to herein as an “insulation ring”) having a ring shape. The insulation layer 40 is disposed on the surface 101u and is adjacent to the sidewall 101s of the recess 101r. The insulation ring may be disposed in the recess 101r. The conductive layer 80 may include a first cup portion (also referred to herein as a “first conductive cup”) having a cup shape disposed in the ring portion of the insulation layer 40. The conductive layer 82 may include a second cup portion (also referred to herein as a “second conductive cup”) having a cup shape disposed in the first cup portion of the conductive layer 80. The CTE of the second cup portion of the conductive layer 82 is less than 0 (is negative, namely contracts upon heating). The insulation layer 42 is disposed in the second cup portion of the conductive layer 82. The CTE of the insulation layer 42 is greater than 0 (is positive, namely expands upon heating). The CTE of the conductive layer 80 is greater than 0 (is positive). In one or more embodiments, the stress adjusting layer 84 is electrically insulated from conductive portions of the via 30 (e.g. from the first conductive layer 80 and the second conductive layer 82). In one or more embodiments, the stress adjusting layer 84 is a patterned conductive layer.
The conductive layer 80 is disposed adjacent to the insulation layer 40 and extends over at least a portion of the surface 101u. A conductive layer 82 is disposed adjacent to the conductive layer 80 and is extends over at least a portion of the surface 101u.
The stress adjusting layer 84 is disposed on the first surface 101u. The stress adjusting layer 84 has a negative CTE. The conductive layer 82 is disposed on the conductive layer 80. In some embodiments, a thickness of one of the stress adjusting layer 84 and conductive layer 82, each of the stress adjusting layer 84 and conductive layer 82, or both of the stress adjusting layer 84 and conductive layer 82 may range from about 1 nanometer (nm) to about 5 nm. Stress caused by thermal expansion of the insulation layer 40 during a heating operation may cause warpage of the electrical device 1. Contraction of the conductive layer 82 may constrain or at least partially cancel out the stress caused by the thermal expansion of the insulation layer 40 during the heating operation. The contraction of the conductive layer 82 may help to avoid the warpage of the electrical device 1.
In one or more embodiments, a material of the conductive layer 82 and the stress adjusting layer 84 may include, for example, graphene, or other suitable conductive materials having a negative CTE (e.g. a negative value with a magnitude at room temperature of at least about 1×10−8 K−1, at least about 1×10−7 K−1, or at least about 1×10−6 K−1). In one or more embodiments, the conductive layer 82 and the stress adjusting layer 84 are made from a same material. The active circuit layer 20 is disposed on the surface 101b. In one or more embodiments, the active circuit layer 20 may include a layer of a die/chip. The active circuit layer 20 is electrically connected to the conductive layer 80. The insulation layer 42 is disposed on the conductive layer 82. The conductive layer 82 surrounds the insulation layer 42. The stress adjusting layer 84 disposed on the surface 101u of substrate 10 may mitigate the warpage of the electrical device 1. The conductive layer 82 (which may include graphene) has a relatively high thermal conductivity which facilitates heat dissipation.
In some embodiments, the conductive layer 80 includes a layer 801 and a seed layer 802. In one or more embodiments, a material of the conductive layer 80 may include, for example, copper (Cu), another metal, an alloy, or other suitable conductive materials. In some embodiments, the substrate 10 includes silicon (Si), a glass, a ceramic, a metal (such as, for example, Cu, nickel (Ni), a silver (Ag) tin (Sn) alloy (Ag/Sn), palladium (Pd), or another suitable metal), a lead frame, polypropylene (PP), a polyimide (PI), an Ajinomoto Build-up Film (ABF), or other suitable insulating materials. In some embodiments, the substrate 10 includes a semiconductor material.
In one or more embodiments, a material of the conductive layer 12 may include, for example, aluminum (Al), another conductive metal or alloy, or other suitable conductive materials. In one or more embodiments, a material of the insulation layers 40 and 42 may include, for example, a solder mask, PP, a PI, an ABF, an epoxy, a molding compound, a liquid type (or solid type) photosensitive material, a glass, a ceramic, or other suitable materials. In one or more embodiments, a material of the dielectric layer 11 may include, for example, an oxide layer, a nitride layer or other suitable conductive materials. A conductive layer 82 having a negative CTE (such as graphene) may compensate for a CTE mismatch between the components in the electrical device 1. The conductive layer 82 may mitigate the warpage of the semiconductor device package 1.
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As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. Thus, the term “approximately equal” in reference to two values can refer to a ratio of the two values being within a range between and inclusive of 0.9 and 1.1.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
Two surfaces or sides can be deemed to be aligned if a displacement between the two surfaces is no greater than 0.5 μm, no greater than 1 μm, no greater than 5 μm, no greater than 10 μm, or no greater than 15 μm.
As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.
As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the present disclosure. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
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