A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.
|
13. A memory device, comprising:
a semiconductor substrate having an upper surface and first, second and third areas, wherein portions of the upper surface in the first and third areas are recessed relative to a portion of the upper surface in the second area;
a memory cell that includes:
a first source region and a first drain region formed in the substrate under the recessed portion of the upper surface in the first area of the substrate, with a first channel region of the substrate extending between the first source region and the first drain region,
a polysilicon floating gate disposed vertically over and insulated from a first portion of the first channel region,
a polysilicon word line gate disposed vertically over and insulated from a second portion of the first channel region,
a polysilicon erase gate disposed vertically over and insulated from the first source region, and
a metal control gate disposed vertically over and insulated from the floating gate;
a logic device that includes:
a second source region and a second drain region formed in the second area of the substrate, with a second channel region of the substrate extending between the second source region and the second drain region, and
a metal gate disposed vertically over and insulated from the second channel region;
a high voltage device that includes:
a third source region and a third drain region formed in the substrate under the recessed portion of the upper surface in the third area of the substrate, with a third channel region of the substrate extending between the third source region and the third drain region, and
a polysilicon gate disposed vertically over and insulated from the third channel region.
1. A method of making a memory device on a semiconductor substrate having an upper surface and first, second and third areas, comprising:
recessing portions of the upper surface in the first and third areas relative to a portion of the upper surface in the second area;
forming a memory cell by:
forming a first source region and a first drain region in the substrate under the recessed portion of the upper surface in the first area of the substrate, with a first channel region of the substrate extending between the first source region and the first drain region,
forming a polysilicon floating gate disposed vertically over and insulated from a first portion of the first channel region,
forming a poly silicon word line gate disposed vertically over and insulated from a second portion of the first channel region,
forming a polysilicon erase gate disposed vertically over and insulated from the first source region, and
forming a metal control gate disposed vertically over and insulated from the floating gate;
forming a logic device by:
forming a second source region and a second drain region in the second area of the substrate, with a second channel region of the substrate extending between the second source region and the second drain region, and
forming a metal gate disposed vertically over and insulated from the second channel region;
forming a high voltage device by:
forming a third source region and a third drain region in the substrate under the recessed portion of the upper surface in the third area of the substrate, with a third channel region of the substrate extending between the third source region and the third drain region, and
forming a poly silicon gate disposed vertically over and insulated from the third channel region.
3. The method of
4. The method of
5. The method of
7. The method of
forming a layer of polysilicon over and insulated from the substrate; and
selectively removing portions of the polysilicon layer in the first area leaving behind the polysilicon word line gate and the polysilicon erase gate, and in the third area leaving behind the polysilicon gate.
8. The method of
forming SiGe on the upper surface of the substrate over the first, second and third drain regions and over the second and third source regions.
9. The method of
forming an insulation layer over the upper surface in the first, second and third areas;
removing the insulation layer from the first and third areas but not from the second area;
oxidizing the upper surface in the first and third areas but not in the second area.
10. The method of
the word line gate is insulated from the substrate by a first insulation having a first thickness;
the floating gate is insulated from the substrate by a second insulation having a second thickness;
the polysilicon gate is insulated from the substrate by a third insulation having a third thickness; and
the first thickness is less than the second thickness, and the second thickness is less than the third thickness.
11. The method of
performing an implantation that simultaneously forms the first drain region in the first area, the second source and the second drain regions in the second area, and the third source and the third drain regions in the third area.
12. The method of
15. The device of
16. The device of
17. The device of
19. The device of
SiGe disposed directly on the upper surface of the substrate over the first, second and third drain regions and over the second and third source regions.
20. The device of
the word line gate is insulated from the substrate by a first insulation having a first thickness;
the floating gate is insulated from the substrate by a second insulation having a second thickness;
the polysilicon gate is insulated from the substrate by a third insulation having a third thickness;
the first thickness is less than the second thickness, and the second thickness is less than the third thickness.
21. The device of
|
This application claims the benefit of U.S. Provisional Application No. 62/594,976, filed Dec. 5, 2017, and which is incorporated herein by reference.
The present invention relates to non-volatile memory devices.
Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 discloses a split gate non-volatile memory cell.
The memory cells are arranged in an array to form a device, with columns of such memory cells separated by columns of isolation regions. Isolation regions are portions of the substrate in which insulation material is formed. Logic (core) devices and high voltage devices can be formed on the same chip as the memory array, often formed sharing some of the same processing steps. Those dedicated areas of the substrate in which logic device and high voltage devices are formed will be referred to herein as the logic and high voltage areas, respectively.
One issue with conventional split gate memory cells is the height of the memory cells on the substrate is greater than that of the devices in the logic and high voltage areas. Yet, it can be challenging to reduce the height of the memory cells while still preserving desired performance. The present invention is a novel technique for forming a split gate non-volatile memory device on the same chip as logic and high voltage devices, with the memory cells utilizing control gates having a metal material with conventional ONO (oxide/nitride/oxide) or OHKO (oxide/HK/oxide) under the control gate as the coupling dielectrics to the floating gate.
The aforementioned problems and needs are addressed by a method of making a memory device on a semiconductor substrate having an upper surface and first, second and third areas, includes recessing portions of the upper surface in the first and third areas relative to a portion of the upper surface in the second area, forming a memory cell, forming a logic device and forming a high voltage device. The forming of the memory cell includes forming a first source region and a first drain region in the substrate under the recessed portion of the upper surface in the first area of the substrate, with a first channel region of the substrate extending between the first source region and the first drain region, forming a polysilicon floating gate disposed over and insulated from a first portion of the first channel region, forming a polysilicon word line gate disposed over and insulated from a second portion of the first channel region, forming a polysilicon erase gate disposed over and insulated from the first source region, and forming a metal control gate disposed over and insulated from the floating gate. The forming of the logic device includes forming a second source region and a second drain region in the second area of the substrate, with a second channel region of the substrate extending between the second source region and the second drain region, and forming a metal gate disposed over and insulated from the second channel region. The forming of the high voltage device includes forming a third source region and a third drain region in the substrate under the recessed portion of the upper surface in the third area of the substrate, with a third channel region of the substrate extending between the third source region and the third drain region, and forming a polysilicon gate disposed over and insulated from the third channel region.
A memory device includes a semiconductor substrate having an upper surface and first, second and third areas, wherein portions of the upper surface in the first and third areas are recessed relative to a portion of the upper surface in the second area, a memory cell, a logic device and a high voltage device. The memory cell includes a first source region and a first drain region formed in the substrate under the recessed portion of the upper surface in the first area of the substrate, with a first channel region of the substrate extending between the first source region and the first drain region, a polysilicon floating gate disposed over and insulated from a first portion of the first channel region, a polysilicon word line gate disposed over and insulated from a second portion of the first channel region, a polysilicon erase gate disposed over and insulated from the first source region, and a metal control gate disposed over and insulated from the floating gate. The logic device includes a second source region and a second drain region formed in the second area of the substrate, with a second channel region of the substrate extending between the second source region and the second drain region, and a metal gate disposed over and insulated from the second channel region. The high voltage device includes a third source region and a third drain region formed in the substrate under the recessed portion of the upper surface in the third area of the substrate, with a third channel region of the substrate extending between the third source region and the third drain region, and a polysilicon gate disposed over and insulated from the third channel region.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
The present invention solves the above mentioned problems by forming the control gates using a metal material or a polysilicon material and high K dielectric, and recessing the height of the substrate upper surface portion on which the memory cells are formed, as well as other techniques described herein. Referring to
As further shown in
Nitride and oxide etches are then performed to remove the nitride layer 34 and oxide layer 32/32a. An oxide layer 36 is formed on the substrate surface (e.g., by thermal oxidation). A polysilicon (poly) layer 38 is formed on the oxide layer 36. A masking step is used to form photoresist 40, and remove the photoresist 40 only from the logic area. A poly etch is performed to remove the exposed poly layer 38 in the logic area. The resulting structure is shown in
After the photoresist 40 is removed, insulation areas (e.g., preferably well-known shallow trench insulation—STI) are formed in the substrate 30 between the cell, logic and HV areas. STI is oxide formed in trenches in the substrate. STI is preferably formed by a masking and etch process that selectively etches through poly layer 38 and oxide layer 36, and into the substrate. The trenches are then filled with oxide 42, as shown in
After photoresist 50 is removed, oxide spacers 52 are formed on the sidewalls of the structures by oxide deposition and etch. Alternately, spacers 52 could be formed as oxide-nitride spacers. A poly etch is used to define what will be the control gate and to remove the exposed portions of the poly layer 38 in the cell and HV areas. Photoresist 54 is formed over all areas but removed from the HV area. An implantation process is performed to implant the well region of the HV area substrate, as shown in
Photoresist 60 is formed over the structure, and removed except for the area between stacks S1 and S2 (and portions of stacks S1/S2), as shown in
A layer of polysilicon 72 is then deposited on the structure. An oxide layer 74 is formed on the poly layer 72. Photoresist 76 is formed on the structure, and removed from the cell and logic areas. An oxide etch is used to remove the oxide layer 74 from the cell and logic areas, as shown in
After a logic well implant in the logic area, a thin oxide layer 80 (interfacial layer—IL) is formed on the substrate in the logic area. This is followed by a high K metal gate layer HKMG formation, which comprises an insulation layer 82 of a high K material (i.e. having a dielectric constant K greater than that of oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other adequate materials, etc.), and a metal layer 84 such as TiN. A dummy poly layer 86 is then formed on the metal layer 84. One or more insulating layers 88 are formed on the dummy poly layer 86 which will be used as a hard mask. A photolithography masking step is performed to remove portions of the newly formed layers in the logic area, except stacks ST thereof, as shown in
Photoresist 90 is formed on the structure, and certain portions thereof removed by a masking step (i.e., portions in the cell and HV areas). Etches are performed to remove the underlying layers down to either the substrate or an oxide on the substrate, to define the poly gates 72a in the HV area, and the word line gates 72b in the cell area, as shown in
A poly etch is used to remove the dummy poly 86 from the logic area, which was left exposed by the CMP. A metal deposition and CMP are then performed to form a metal block 106 over the TiN layer 84 and high K material layer 82 in the logic area, as shown in
The final structure is shown in
The above described formation technique has many advantages, including that the number of masking steps is minimized. The cell formation is decoupled with the HKMG formation process for the logic area, eliminating any risk of contamination. The thickness of the oxide under the word line gates 72b can be independently adjusted for flexibility (e.g., the thickness of the oxide under the word line gates 72b can be less than that under the floating gate 38, which can be less than that under the HV gate 72a). The top height of the various devices are even with each other (i.e., the top surfaces of the control gates 46, metal gate 106 and HV gate 72a are co-planar), which is achieved by recessing the substrate surface in the cell and HV areas, and using metal and a high-K insulator to form the memory cell control gates.
It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cells of the present invention. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa. The terms “forming” and “formed” as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed. Lastly, the O/HK/O layer under the control gates could be replaced with an oxide/nitride/oxide layer (ONO).
It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
Do, Nhan, Su, Chien-Sheng, Yang, Jeng-Wei, Wu, Man-Tang, Chen, Chun-Ming
Patent | Priority | Assignee | Title |
11316024, | Sep 30 2020 | Silicon Storage Technology, Inc.; Silicon Storage Technology, Inc | Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same |
11621335, | Sep 30 2020 | Silicon Storage Technology, Inc. | Method of making split-gate non-volatile memory cells with erase gates disposed over word line gates |
11652162, | Apr 20 2016 | Silicon Storage Technology, Inc. | Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps |
11869950, | Aug 05 2020 | Korea Advanced Institute of Science and Technology | Steep-slope field-effect transistor and fabrication method thereof |
Patent | Priority | Assignee | Title |
10535671, | Nov 29 2016 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell boundary structure for embedded memory |
5242848, | Apr 09 1991 | Silicon Storage Technology, Inc. | Self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device |
6747310, | Oct 07 2002 | Silicon Storage Technology, Inc | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication |
6861698, | Jan 24 2002 | Silicon Storage Technology, Inc | Array of floating gate memory cells having strap regions and a peripheral logic device region |
7046552, | Mar 17 2004 | Silicon Storage Technology, Inc | Flash memory with enhanced program and erase coupling and process of fabricating the same |
7119396, | Oct 08 2004 | Silicon Storage Technology, Inc | NROM device |
7151042, | Feb 02 2005 | Macronix International Co., Ltd. | Method of improving flash memory performance |
7315056, | Jun 07 2004 | Silicon Storage Technology, Inc | Semiconductor memory array of floating gate memory cells with program/erase and select gates |
7326614, | Apr 01 2002 | Silicon Storage Technology, Inc. | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby |
7439133, | Jan 02 2006 | Skymedi Corporation | Memory structure and method of manufacturing a memory array |
7834390, | Feb 08 2008 | Renesas Electronics Corporation | Nonvolatile semiconductor memory device and method of manufacturing the same |
7868375, | Aug 06 2007 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
7927994, | Dec 06 2010 | Silicon Storage Technology, Inc. | Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing |
8008702, | Feb 20 2008 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-transistor non-volatile memory element |
8101477, | Sep 28 2010 | Infineon Technologies AG | Method for making semiconductor device |
8138524, | Nov 01 2006 | Silicon Storage Technology, Inc | Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby |
8173514, | Feb 22 2008 | Taiwan Semiconductor Manufacturing Company, Ltd | Method of manufacturing semiconductor device |
8334560, | Sep 02 2009 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reverse disturb immune asymmetrical sidewall floating gate devices |
8664059, | Apr 26 2012 | GLOBALFOUNDRIES U S INC | Non-volatile memory device formed by dual floating gate deposit |
8669607, | Nov 01 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for non-volatile memory cells with increased programming efficiency |
8878281, | May 23 2012 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for non-volatile memory cells |
9082865, | Mar 13 2012 | Samsung Electronics Co., Ltd. | Split-gate type nonvolatile memory device, semiconductor device having split-type nonvolatile memory device embedded therein, and methods of forming the same |
9093546, | Nov 19 2012 | Renesas Electronics Corporation | Method of manufacturing semiconductor device and semiconductor device |
9123822, | Aug 02 2013 | Silicon Storage Technology, Inc | Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same |
9219134, | Nov 07 2012 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
9230977, | Jun 21 2013 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded flash memory device with floating gate embedded in a substrate |
9276005, | Dec 04 2014 | Silicon Storage Technology, Inc | Non-volatile memory array with concurrently formed low and high voltage logic devices |
9276006, | Jan 05 2015 | Silicon Storage Technology, Inc | Split gate non-volatile flash memory cell having metal-enhanced gates and method of making same |
9287282, | Jan 28 2014 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a logic compatible flash memory |
9349741, | Jul 14 2014 | Taiwan Semiconductor Manufacturing Co., Ltd. | Recessed salicide structure to integrate a flash memory device with a high κ, metal gate logic device |
9368605, | Aug 28 2013 | Omron Corporation | Semiconductor structure including a split gate nonvolatile memory cell and a high voltage transistor, and method for the formation thereof |
9379121, | Jan 05 2015 | Silicon Storage Technology, Inc | Split gate non-volatile flash memory cell having metal gates and method of making same |
9431257, | Jul 14 2014 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicided structure to integrate a flash memory device with a high κ, metal gate logic device |
9431407, | Sep 19 2014 | Silicon Storage Technology, Inc | Method of making embedded memory device with silicon-on-insulator substrate |
9472562, | Apr 28 2015 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
9484261, | Jul 05 2013 | Silicon Storage Technology, Inc | Formation of self-aligned source for split-gate non-volatile memory cell |
9496369, | Jan 22 2015 | Silicon Storage Technology, Inc | Method of forming split-gate memory cell array along with low and high voltage logic devices |
9634019, | Oct 01 2015 | Silicon Storage Technology, Inc | Non-volatile split gate memory cells with integrated high K metal gate, and method of making same |
9793280, | Mar 04 2015 | Silicon Storage Technology, Inc | Integration of split gate flash memory array and logic devices |
9793281, | Jul 21 2015 | Silicon Storage Technology, Inc | Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same |
20050186741, | |||
20090039410, | |||
20090065873, | |||
20090166708, | |||
20090215243, | |||
20090239351, | |||
20090321810, | |||
20100054043, | |||
20100207174, | |||
20110049603, | |||
20120299056, | |||
20130032872, | |||
20130171814, | |||
20130207174, | |||
20130242659, | |||
20130313626, | |||
20140015030, | |||
20140097482, | |||
20140264538, | |||
20150072489, | |||
20150084111, | |||
20150137207, | |||
20150171101, | |||
20150171102, | |||
20150171103, | |||
20150214237, | |||
20150263010, | |||
20160020219, | |||
20160043095, | |||
20160126327, | |||
20160148944, | |||
20160163722, | |||
20160181266, | |||
20160218110, | |||
20170117372, | |||
20170125603, | |||
20180151580, | |||
20180315765, | |||
20200020601, | |||
TW200723543, | |||
TW201338101, |
Date | Maintenance Fee Events |
Oct 22 2018 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Dec 20 2023 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
Date | Maintenance Schedule |
Jul 14 2023 | 4 years fee payment window open |
Jan 14 2024 | 6 months grace period start (w surcharge) |
Jul 14 2024 | patent expiry (for year 4) |
Jul 14 2026 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jul 14 2027 | 8 years fee payment window open |
Jan 14 2028 | 6 months grace period start (w surcharge) |
Jul 14 2028 | patent expiry (for year 8) |
Jul 14 2030 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jul 14 2031 | 12 years fee payment window open |
Jan 14 2032 | 6 months grace period start (w surcharge) |
Jul 14 2032 | patent expiry (for year 12) |
Jul 14 2034 | 2 years to revive unintentionally abandoned end. (for year 12) |