Method for fabricating semiconductor device including contact bars having narrower portions

Abstract

A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

Description

RELATED APPLICATIONS

This application is a Divisional Application of U.S. patent application Ser. No. 15/299,641 filed Oct. 21, 2016, now U.S. Pat. No. 10,366,989, which claims priority to U.S. Provisional Patent Application No. 62/293,625 filed Feb. 10, 2016, the entire disclosure of each of which is incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a structure and a manufacturing method for a contact structure over source/drain regions.

BACKGROUND

With a decrease of dimensions of semiconductor devices, an epitaxial source/drain structure has been widely utilized for fabricating a fin field effect transistor (FinFET). Further, a contact bar (source/drain (S/D) contact layer) is formed over the epitaxial S/D structure to electrically connect the source/drain of the FinFET to an upper layer metal wiring. As the device density increases (i.e., the dimensions of semiconductor device decreases), an electrical separation between the fin structure of one FinFET and the neighboring STI (shallow trench isolation) contact becomes tighter, which may cause a short circuit between the neighboring STI contact and the fin structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 shows an exemplary layout structure of a FinFET device according to one embodiment of the present disclosure.

FIG. 2A shows an exemplary cross sectional view along line X1-X1 of FIG. 1, FIG. 2B shows an exemplary cross sectional view along line X2-X2 of FIG. 1, and FIG. 2C shows an exemplary cross sectional view along line Y1-Y1 of FIG. 1.

FIGS. 3 and 4 show exemplary layout structures of a FinFET device according to other embodiments of the present disclosure.

FIG. 5A shows an exemplary plan view (viewed from the above) illustrating one stage of a sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure. FIG. 5B shows an exemplary cross sectional view along line X3-X3 of FIG. 5A. FIG. 5C is an enlarged view of the gate structure shown in FIG. 5B. FIG. 5D shows an exemplary perspective view illustrating one stage of a sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure.

FIGS. 6-11 show exemplary cross sectional views illustrating various stages of the sequential fabrication process of a semiconductor device according to one embodiment of the present disclosure.

FIG. 12 illustrates an opening width dependency on an etching depth.

FIGS. 13-15 illustrate a flow of designing the contact bars according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.”

FIG. 1 shows an exemplary layout structure of a FinFET device according to one embodiment of the present disclosure. FIG. 1 is a simplified layout structure and only relevant layers are illustrated.

As shown in FIG. 1, fin structures 2 extending in the X direction are arranged in the Y direction, gate structures 4 extending in the Y direction are arranged in the X direction and contact bars (source/drain (S/D) contact layers) 7 extending in the Y direction are arranged in the X direction. The fin structures 2 constitute a channel, a source and a drain of a FinFET. In this disclosure, a source and a drain are interchangeably used and the term source/drain (S/D) means one of a source and a drain.

The gate structure 4 is disposed over the channel of the fin structure 2, and includes a gate dielectric layer and a gate electrode layer. In some embodiments, sidewall spacers are formed on both major sides of the gate structure 4. As shown in FIG. 1, plural gate structures are arranged in the X direction with a constant pitch. Some of the gate structures are dummy gate structures which do not constitute a transistor. In FIG. 1, the gate structure 4A may be a dummy gate structure.

In FIG. 1, three FinFETs TR1, TR2 and TR3 are illustrated. Each of the three FinFETs TR1, TR2 and TR3 includes two fin structures. In such a case, an epitaxially formed semiconductor layer formed on one fin structure is merged with an epitaxially formed semiconductor layer formed on the other fin structure. The number of the fin structures included in one FinFET may be one or three or more. Although two fins are electrically connected by STI contact 7 in FIG. 7, the present embodiments are not limited to the structure of FIG. 1. In some embodiments, single fin constitute one FinFET.

The source and drain include an S/D structure including an epitaxially formed semiconductor layer. The S/D structure further includes a silicide layer formed on the epitaxially formed semiconductor layer. A contact bar 7 is disposed on the S/D structure and electrically connects the S/D structure to an upper conductive layer (vertical connection) and/or another S/D structure (horizontal connection). The contact bars 7 are disposed between the gate structures 4 and over an isolation insulating layer (STI)

Still referring to FIG. 1, at least one of the contact bars, for example, contact bar 7A or 7B includes at least two portions having different widths. The contact bar 7B includes a first portion P1 disposed over the S/D structure of FinFET TR1 (S/D contact portion) and a second portion P2, which overlaps no fin structure and no S/D structure and is disposed over an isolation insulating layer (STI contact portion). A width of the second portion P2 in the X direction is smaller than a width of the first portion P1 in the X direction in plan view. In the present disclosure, the first portion includes adjacent areas adjacent to the S/D structure in the Y direction, where each of the adjacent areas having a length in the Y direction which is the same as the width of the fin structure.

The contact bar 7B further includes a third portion P3 disposed over the S/D structure of the FinFET TR2. A width of the third portion in the X direction is substantially equal to the width of the first portion P2 in the X direction in plan view. Here, the substantially equal width means that two portions are designed to have the same width and the difference of the widths of two portions is within a process variation or a measurement variation known in the art (e.g., a few nm). Further, the width is measured at the middle of each portion.

As shown in FIG. 1, the second portion P2 is located at a region which faces an end of the fin structures (e.g., 2A) of the FinFET TR3.

FIG. 2A shows an exemplary cross sectional view along line X1-X1 of FIG. 1, FIG. 2B shows an exemplary cross sectional view along line X2-X2 of FIG. 1, and FIG. 2C shows an exemplary cross sectional view along line Y1-Y1 of FIG. 1. In FIGS. 2A-2C, fin structures 2A and 2B, gate structures 4A and 4B, S/D structures 5 (5A and 5B) and contact bars 7A, 7B are formed over the substrate 1.

As shown in FIGS. 2A and 2B, the width W2 of the second portion P2 of the contact bar 7B in the X direction measured at the upper face of the second portion P2 is smaller than the width W1 of the first portion P1 in the X direction. Further, as shown in FIG. 2C, the thickness (or depth) D2 of the second portion P2 in the Z direction is smaller than the thickness D1 of the first portion P1 in the Z direction. The thickness D1 of the first portion P1 is defined as the average thickness in the first portion, and is the vertical distance between the upper surface of the contact bar 7B in the first portion and the upper surface of the underlying insulating layer 3 in the first portion. The thickness D2 of the second portion P2 is defined as the average thickness in the second portion, and is the vertical distance between the upper surface of the contact bar 7B in the second portion and the upper surface of the underlying insulating layer 3 in the second portion. In certain embodiments, as shown in FIG. 2A, the second portion P2 of the contact bar 7B has a tapered shape with a bottom width W3 being smaller than the top width W2. In other embodiments, however, no tapered shape is formed.

If the thickness (depth) D2 in the second portion P2 is equal to or greater than the thickness (depth) D1, the distance between the contact bar 7B and the edge of the fin structure 2A decreases, and an electrical separation may become insufficient. Further, if the thickness (depth) D2 in the second portion P2 becomes much greater than the thickness (depth) D1, the distance (H1) between the contact bar 7B and the substrate 1 (and the fin structure 2A) decreases, and an electrical separation may become insufficient. However, as shown in FIGS. 2A and 2C, since the thickness (depth) D2 in the second portion P2 is smaller than the thickness (depth) D1 and the bottom of the contact bar 7B is located above the fin structure 2A, it is possible to sufficiently secure the electrical separation between the contact bar 7B and the fin structure 2A and/or the substrate 1. In particular, with the foregoing structure can prevent the contact bar 7B and the fin structure from contacting to each other due to process variations. Accordingly, it is possible to prevent a short-circuit between the contact bar 7B and the fin structure 2A and/or the substrate 1, and/or to suppress a leakage current between the contact bar 7B and the fin structure 2A and/or the substrate 1.

In some embodiments, the difference between the width W1 and width W2 is in a range from about 1 nm to about 10 nm, and is in a range from about 2 nm to about 4 nm in other embodiments. The difference between the thickness (depth) D1 and thickness (depth) D2 is in a range from about 3 nm to about 30 nm in some embodiments, and is in a range from about 8 nm to about 12 nm in other embodiments.

FIGS. 3 and 4 show exemplary layout structures of a FinFET device according to other embodiments of the present disclosure.

In FIG. 3, each of the contact bars 7 includes a first portion disposed over an S/D structures and a second portion which overlaps no fin structure and no S/D structure. In other words, in FIG. 3, the width of the contact bars 7 is larger (i.e., first portions) only in the regions over the S/D structures.

In FIG. 4, the width of the contact bars 7 is narrower (i.e., second portions) only in the regions where adjacent fin structures are located closer to the S/D structures. For example, contact bars 713 or 714 include second portions in regions where adjacent fin structures 2 are located closer to the S/D structures. A distance in the X direction between the second portion P12 of the contact bar 713 and an end of a fin structure 211 closer to the contact bar 713 in the X direction is equal to or smaller than a first threshold distance S1. The widths of the contact bars 7 disposed over the S/D structures (i.e., the width of the first portion W1) are larger than that of the second portion P12 (i.e., the width of the first portion W1). Similarly, the contact bar 714 has a second portion having a narrower width where the fin structure 212 is closer to the contact bar 714, as shown in FIG. 4. Further, even if the contact bars 7 include portions which overlap no fin structure and no S/D structure, as long as the distance between the contact bar and the closest fin structure is more than the first threshold distance S1, the widths of such portions is set to W1. Accordingly, the contact bars 711, 712, 715 and 716 include no second portion (with a narrow width W2) and have a constant width.

In some embodiments, the contact bar includes a second portion if the contact bar includes a region where adjacent fin structures 2 are located closer to the S/D structures than the first threshold distance S1, and if the contact bar includes such a portion, the contact bar has the width W1 (as the width of the first portion) only over the S/D structure and has the width W2 (as the width of the second portion) in other portions. If the contact bar does not include such a portion, the contact bar has a constant width W1.

The layout structure of FIG. 3 and FIG. 4 may be used in a mixed manner. Further, it is noted that the thickness of the contact bars at the second portions (narrow portions) is smaller than the thickness of the contact bars at the first and third portions (broader portions).

The sequential fabrication operations for manufacturing a semiconductor FinFET device according to one embodiment of the present disclosure will be explained using FIGS. 5A-11.

FIGS. 5A and 5B show one stage of the sequential fabrication operations according to one embodiment of the present disclosure. FIG. 5A shows a plan (top) view and FIG. 5B shows a cross sectional view along line X3-X3 of FIG. 5A.

FIGS. 5A and 5B show a structure of a semiconductor device after metal gate structures are formed. In FIGS. 5A and 5B, metal gate structures 40 are formed over a channel layer, for example, a part of a fin structure 20 formed over a substrate 10. The metal gate structures 40 include first to fourth metal gate structures 40A, 40B, 40C and 40D, and extend in the Y direction and are arranged in the X direction. The thickness of the metal gate structures 40 is in a range from about 5 nm to about 200 nm in some embodiments. Each of the gate structures 40 includes a gate dielectric layer 42, a metal gate electrode 44 and sidewall spacers 46 provided on major sidewalls of metal gate electrode 44. The sidewall spacers 46 are made of at least one of SiN, SiON, AlO and AlON. The film thickness of the sidewall spacers 46 at the bottom of the sidewall spacers is in a range from about 2 nm to about 20 nm in some embodiments, and is in a range from about 4 nm to about 8 nm in other embodiments. Further, source/drain (S/D) regions 25 are formed adjacent to the gate structures, and spaces between the gate structures are filled with a first interlayer dielectric (ILD) layer 50. The first ILD layer 50 includes one or more layers of insulating material, such as SiO₂, SiN, SiON, SiOCN, SiCN or SiCO. In one embodiment, SiO₂ is used. In some embodiments, a silicide layer (not shown) is formed over the S/D regions 25.

FIG. 5C is an enlarged view of the gate structure. The metal gate structure 40 includes one or more layers 45 of metal material, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, and other conductive materials. A gate dielectric layer 42 disposed between the channel layer and the metal gate electrode 44 includes one or more layers of metal oxides such as a high-k metal oxide. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and/or mixtures thereof. In some embodiments, an interface dielectric layer 41 made of, for example silicon dioxide, is formed between the channel layer and the gate dielectric layer 42.

In some embodiments, one or more work function adjustment layers 43 are interposed between the gate dielectric layer 42 and the metal material 45. The work function adjustment layers 43 are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer.

In this embodiment, fin field effect transistors (FinFETs) fabricated by a gate-replacement process are employed.

FIG. 5D shows an exemplary perspective view of a FinFET structure.

First, a fin structure 310 is fabricated over a substrate 300. The fin structure includes a bottom region and an upper region as a channel region 315. The substrate is, for example, a p-type silicon substrate with an impurity concentration in a range from about 1×10¹⁵ cm⁻³ to about 1×10¹⁸ cm⁻³. In other embodiments, the substrate is an n-type silicon substrate with an impurity concentration in a range from about 1×10¹⁵ cm⁻³ to about 1×10¹⁸ cm⁻³. Alternatively, the substrate may comprise another elementary semiconductor, such as germanium; a compound semiconductor including Group IV-IV compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon-on-insulator) substrate.

After forming the fin structure 310, an isolation insulating layer 320 is formed over the fin structure 310. The isolation insulating layer 320 includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. The isolation insulating layer may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN and/or fluorine-doped silicate glass (FSG).

After forming the isolation insulating layer 320 over the fin structure, a planarization operation is performed so as to remove part of the isolation insulating layer 320. The planarization operation may include a chemical mechanical polishing (CMP) and/or an etch-back process. Then, the isolation insulating layer 320 is further removed (recessed) so that the upper region of the fin structure is exposed.

A dummy gate structure is formed over the exposed fin structure. The dummy gate structure includes a dummy gate electrode layer made of poly silicon and a dummy gate dielectric layer. Sidewall spacers 350 including one or more layers of insulating materials are also formed on sidewalls of the dummy gate electrode layer. After the dummy gate structure is formed, the fin structure 310 not covered by the dummy gate structure is recessed below the upper surface of the isolation insulating layer 320. Then, a source/drain region 360 is formed over the recessed fin structure by using an epitaxial growth method. The source/drain region may include a strain material to apply stress to the channel region 315.

Then, an interlayer dielectric layer (ILD) 370 is formed over the dummy gate structure and the source/drain region 360. After a planarization operation, the dummy gate structure is removed so as to make a gate space. Then, in the gate space, a metal gate structure 330 including a metal gate electrode and a gate dielectric layer, such as a high-k dielectric layer, is formed. In FIG. 5D, the view of parts of the metal gate structure 330, sidewalls 330 and the ILD 370 are cut to show the underlying structure.

The metal gate structure 330 and the sidewalls 330, source/drain 360 and the ILD 370 of FIG. 5D substantially correspond to the metal gate structure 40, source/drain regions 25 and first interlayer dielectric layer (ILD) 50, of FIGS. 5A and 5B, respectively.

FIGS. 6-11 show various stages of the sequential fabrication operation of a semiconductor FinFET device according to one embodiment of the present disclosure. FIGS. 6, 7 and 9-11 show exemplary cross sectional views corresponding to line X3-X3 of FIG. 5A and FIG. 8 shows a plan view. It is understood that additional operations can be provided before, during, and after processes shown by FIGS. 6-11, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. Not all layers or features are illustrated in the figures. The order of the operations/processes may be interchangeable.

As shown in FIG. 6, the metal gate electrodes 44 are recessed below the upper surface of the sidewall spacers 46 by a dry and/or a wet etching operation. The remaining height H2 of the recessed gate electrode 44 is in a range from about 25 nm to about 50 nm in some embodiments.

After the gate electrodes 44 are recessed, a blanket layer 61 of a first insulating material is formed, as shown in FIG. 6. The first insulating material includes one or more of SiC, SiON and SiOCN.

A planarization operation, such as an etch-back process or a chemical mechanical polishing (CMP) process, is performed on the blanket layer 61, so that the gate cap insulating layers 60 are formed over the gate electrode 44, as shown in FIG. 7. In certain embodiments, the forming the cap insulating layer 60 is not necessary.

As shown in FIG. 8, a mask pattern MP including openings MP1 and MP2 are formed over the structure of FIG. 7. The width of the opening MP2 is smaller than the width of the opening MP1. In some embodiments, the width of the opening MP2 is about 50-90% of the width of the mask pattern MP1. The mask opening MP2 corresponds to the second portions of FIGS. 1-4. The width of the mask pattern MP1 is equal to or larger than the space between the gate structures. In certain embodiment, width of the mask pattern MP1 can be smaller than the space between the gate structures.

Then, as shown in FIG. 9, the first ILD layer 50 is etched by a dry and/or a wet etching by using the mask pattern MP as an etching mask, thereby forming openings 65 and 65A. In the openings 65, the source/drain structures 25 are exposed at the bottoms of the openings 65. However, in the opening 65A, since the width of the opening 65A is smaller, the etching of the first ILD layer 50A stops at the middle of the first ILD layer 50A. As shown in FIG. 9, the bottom of the opening 65A is located above the edge of the fin structure 20.

In the etching, in particular, dry etching, of ten-nanometer order scale openings, the etching depth is sensitive to the opening width. As shown in FIG. 12, when the width of the opening is relatively large (e.g., WD1), the etching depth does not depend on the width and a substantially constant depth ED1 can be obtained. However, when the width becomes smaller (e.g., WD2), the etching depth becomes smaller, e.g., ED2.

In the present embodiment, by making the width of the opening MP2 for the second portion smaller than the width of the opening MP1, a shallower opening 65A can be fabricated in the first ILD layer 50A.

Subsequently, a blanket layer of a first conductive material 71 is formed, as shown in FIG. 10. The first conductive material 71 includes one or more of W, Co, Ni, or Ti. In one embodiment, W is used.

A planarization operation, such as an etch-back process or a CMP process, is performed on the blanket layer 71, so that the contact bars 70 and 70A are formed over the source/drain regions 25, as shown in FIG. 11. As shown in FIG. 11, the thickness and width of the contact bar 70A in the second portion P2 are smaller than those of the contact bar 70 in the first or third portion P1, P3.

In the foregoing embodiments, by making the width of the second portion smaller, the depth of the opening 65A (and the thickness of the contact bar 70A) is adjusted. In other embodiment, by using two or more patterning operations (lithography and etching), the depth of the second portion can be adjusted. In such a case, the width of the second portion can be the same as that of the first portion. In other words, only the thickness (depth) of the second portion of the contact bar is smaller than that of the first and/or third portion.

It is understood that the device shown in FIG. 11 undergoes further CMOS processes to form various features such as interconnect metal layers, dielectric layers, passivation layers, etc.

FIGS. 13-15 illustrate a flow of designing the contact bars according to one embodiment of the present disclosure.

In the flow chart of FIG. 13, the initial contact bar patterns are placed between gate patterns. Then, as shown in FIG. 14. Portions of the initial contact bar pattern which are closer to any of fin structures in the X direction than the predetermined distance (e.g., the first threshold distance (S1)) are found. In FIG. 14, the circled portions are found. Then, the width of such portions in the X direction is reduced as shown in FIG. 15.

The portions of which widths are not reduced become first or third portions depending on the underlying structures. If the length of the third portion along the Y direction is smaller than a threshold value, the third portion may be replaced with a second portion.

In the present embodiments, by making a thickness of the second portion of the contact bar smaller, it is possible to sufficiently secure the electrical separation between the contact bar and the fin structure and/or the substrate. Accordingly, it is possible to prevent a short-circuit between the contact bar and the fin structure and/or the substrate, and/or to suppress a leakage current between the contact bar and the fin structure and/or the substrate. Further, by simply making the width of the second portion smaller, it is possible to control the depth of the opening in which the contact bar is formed.

It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.

According to one aspect of the present disclosure, a semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar. The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

According to another aspect of the present disclosure, a semiconductor device includes plural fin field effect transistors (FinFETs) and plural contact bars. Each of the plural FinFETs includes a fin structure extending in a first direction, a gate structure extends in a second direction crossing the first direction, and an S/D structure. The plural contact bars are disposed over a first S/D structure among the plural S/D structure and extending in the second direction. The plural contact bars include a first contact bar. The first contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.

In accordance with yet another aspect of the present disclosure, in a method of manufacturing a semiconductor device including fin field effect transistors (FinFETs), gate structures are formed. The gate structures extend in a first direction and are arranged in a second direction crossing the first direction. Source/drain (S/D) structures are formed between adjacent two gate structures. An insulating layer is formed over the source/drain structures. A mask layer is formed over the insulating layer, the mask layer having a mask opening. A part of the insulating layer is removed through the mask opening to form an opening. The opening is filled with a conductive material, thereby forming a contact bar. The mask opening extends in the first direction and includes a first portion disposed over one of the S/D structures and a second portion. The second portion overlaps no fin structure and no S/D structure. A thickness of the second portion is smaller than a thickness of the first portion in a cross sectional view.

The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device including fin field effect transistors (FinFETs), the method comprising:

forming gate structures extending in a first direction and arranged in a second direction crossing the first direction;

forming source/drain (S/D) structures between adjacent two gate structures;

forming an insulating layer over the source/drain structures;

forming a mask layer over the insulating layer, the mask layer having a mask opening;

removing a part of the insulating layer through the mask opening to form an opening; and

filling the opening with a conductive material, thereby forming a contact bar, wherein:

the mask opening extends in the first direction,

the opening includes a first portion disposed over one of the S/D structures and a second portion,

the second portion overlaps no fin structure and no S/D structure, and

a depth of the second portion is smaller than a depth of the first portion in a cross sectional view.

2. The method of claim 1, wherein a width of the second portion in the second direction is smaller than a width of the first portion in the second direction in plan view.

3. The method device of claim 1, wherein:

the opening includes a third portion disposed over another of the S/D structures, and

the width of the second portion in the second direction is smaller than a width of the third portion in the second direction in plan view.

4. The method of claim 3, wherein the width of the third portion is equal to the width of the first portion.

5. The method of claim 3, wherein a depth of the second portion is smaller than a depth of the first portion in the cross sectional view.

6. The method of claim 5, wherein the depth of the second portion is smaller than a depth of the third portion in the cross sectional view.

7. The method of claim 3, wherein the second portion is disposed between the first portion and the third portion.

8. A method of manufacturing a semiconductor device, the method comprising:

forming first, second and third gate structures extending in a first direction and arranged in a second direction crossing the first direction in this order;

forming a first source/drain (S/D) structure between the first gate structure and the second gate structure;

forming an insulating layer between the first gate structure and the second gate structure and between the second gate structure and the third gate structure;

forming a mask layer over the insulating layer, the mask layer having a first mask opening disposed between the first gate structure and the second gate structure and a second mask opening disposed between the second gate structure and the third gate structure; and

removing a part of the insulating layer through the mask opening to form a first opening corresponding to the first mask opening and a second opening corresponding to the second mask opening, wherein:

the first and second mask openings extends in the first direction, and

a width of the first mask opening is greater than a width of the second mask opening in the second direction in plan view, and no source/drain structure is disposed below the second opening.

9. The method of claim 8, wherein the width of the second mask opening is 50-90% of the width of the first mask opening.

10. The method of claim 9, wherein the width of the first opening is equal to or larger than a space between the first and second gate structures.

11. The method of claim 8, wherein the first S/D structure is exposed at a bottom of the first opening and no channel region is disposed below the second opening.

12. The method of claim 8, wherein a depth of the second opening is smaller than a depth of the first opening in a cross sectional view.

13. The method of claim 8, wherein:

the first and second gate structures are formed to be disposed over a fin structure, and the third gate structure is not disposed over the fin structure.

14. The method of claim 13, wherein a bottom of the second opening is located above a top of the fin structure.

15. The method of claim 8, further comprising filling the first and second openings with a conductive material, respectively, thereby forming a first contact bar and a second contact bar.

16. The method of claim 15, wherein the conductive material includes one or more selected from the group consisting of W, Co, Ni and Ti.

17. The method of claim 8, wherein the first to third gate structures are arranged in the second direction with a constant pitch.

18. A method of manufacturing a semiconductor device, the method comprising:

forming a first fin structure and a second fin structure arranged in a first direction and extending in a second direction crossing the first direction;

forming first, second and third gate structures extending in the first direction and arranged in the second direction in this order;

forming a first source/drain (S/D) structure over the first fin structure between the first gate structure and the second gate structure and a second source/drain (S/D) structure over the second fin structure between the second gate structure and the third gate structure;

forming an insulating layer between the first gate structure and the second gate structure and between the second gate structure and the third gate structure;

forming a mask layer over the insulating layer, the mask layer having a first mask opening disposed between the first gate structure and the second gate structure and a second mask opening disposed between the second gate structure and the third gate structure; and

removing a part of the insulating layer through the mask opening to form a first opening corresponding to the first mask opening and a second opening corresponding to the second mask opening, wherein:

the first and second mask openings extends in the first direction,

the second mask opening has a first portion and a second portion,

a width of the second portion is smaller than a width of the first portion in the second direction in plan view.

19. The method of claim 18, wherein the width of the first portion of the second mask opening is equal to a width of the first opening in the second direction.

20. The method of claim 18, wherein the second opening further includes a third portion having a same width as the first portion.