A semiconductor device includes a substrate with an opening formed through the substrate. A first electronic component is disposed over the substrate outside a footprint of the first opening. A second electronic component is disposed over the substrate opposite the first electrical component. A third electronic component is disposed over the substrate adjacent to the first electronic component. The substrate is disposed in a mold including a second opening of the mold over a first side of the substrate. The mold contacts the substrate between the first electronic component and the third electronic component. An encapsulant is deposited into the second opening. The encapsulant flows through the first opening to cover a second side of the substrate. In some embodiments, a mold film is disposed in the mold, and an interconnect structure on the substrate is embedded in the mold film.
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14. A method of making a semiconductor device, comprising:
providing a substrate including a first opening formed through a saw street of the substrate;
disposing a first electronic component over the substrate; and
depositing an encapsulant through the first opening to cover the first electronic component.
21. A semiconductor device, comprising:
a substrate including a first opening formed through a saw street of the substrate;
a first electronic component mounted on the substrate outside a footprint of the first opening; and
an encapsulant deposited around the first electronic component and in the first opening.
7. A method of making a semiconductor device, comprising:
providing a substrate including a first opening formed through the substrate;
disposing a first electronic component over the substrate;
disposing the substrate in a mold; and
depositing an encapsulant into the mold, wherein the encapsulant flows through the first opening to cover the first electronic component.
1. A method of making a semiconductor device, comprising:
providing a substrate including a first opening formed through the substrate;
disposing a first electronic component over the substrate;
disposing a second electronic component over the substrate;
providing a mold including a first chamber;
disposing the substrate in the mold with the first electronic component and second electronic component disposed in the first chamber, wherein a second opening of the mold is disposed over a first side of the substrate;
depositing an encapsulant into the second opening, wherein the encapsulant flows through the first opening to cover the first electronic component, second electronic component, and a second side of the substrate; and
singulating the substrate and encapsulant between the first electronic component and second electronic component.
2. The method of
disposing a mold film in the mold; and
disposing the substrate in the mold with an interconnect structure of the substrate embedded in the mold film.
3. The method of
4. The method of
disposing a third electronic component over the substrate adjacent to the first electronic component; and
disposing the substrate in the mold with the third electronic component disposed in a second chamber of the mold, wherein the second chamber is isolated from the first chamber.
5. The method of
6. The method of
disposing the substrate in the mold with the mold contacting a portion of the substrate between the first electronic component and second electronic component;
forming a masking layer over the portion of the substrate after removing the substrate from the mold;
forming a shielding layer over the encapsulant and masking layer;
removing the masking layer after forming the shielding layer; and
forming an interconnect structure on the portion of the substrate.
8. The method of
9. The method of
disposing a mold film in the mold; and
disposing the substrate in the mold with the first electronic component contacting the mold film.
10. The method of
disposing a second electronic component over the substrate opposite the first electronic component; and
depositing the encapsulant over the second electronic component.
11. The method of
forming a first shielding layer over the first electronic component after depositing the encapsulant; and
forming a second shielding layer over the second electronic component after depositing the encapsulant.
12. The method of
depositing the encapsulant over a first portion of the substrate while a second portion of the substrate remains devoid of the encapsulant; and
disposing an interconnect structure on the second portion of the substrate after depositing the encapsulant.
13. The method of
15. The method of
16. The method of
17. The method of
disposing a second electronic component over the substrate; and
disposing the substrate in a mold, wherein the mold contacts the substrate between the first electronic component and second electronic component.
19. The method of
20. The method of
disposing a second electronic component over the substrate opposite the first electronic component; and
depositing the encapsulant over the first electronic component and second electronic component.
22. The semiconductor device of
23. The semiconductor device of
24. The semiconductor device of
25. The semiconductor device of
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The present application is a continuation of U.S. patent application Ser. No. 15/458,649, now U.S. Pat. No. 10,636,765, filed Mar. 14, 2017, which application is incorporated herein by reference.
The present invention relates in general to semiconductor devices and, more particularly, to system-in-package devices with double-sided molding.
Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., a single light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, or power metal-oxide semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, and various signal processing circuits.
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices or mechanical systems, transforming sunlight to electricity, and creating visual images for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
Manufacturers also desire to simplify formation of complex package types, or to perform steps required for advanced packages in a simpler manner using existing equipment. Simplifying the packaging process, and using existing equipment, allows advanced semiconductor packages to be formed at a lower cost, thus saving money for the manufacturer, and ultimately the consumer of an end product. One challenge with double-sided molding is the need for two different molds, and the additional capital expenditures required to set up the double molding process.
Therefore, a need exists for a simpler and more cost-effective double-sided molding process.
The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a subcomponent of a larger system. For example, electronic device 50 can be part of a tablet, cellular phone, digital camera, or other electronic device. Alternatively, electronic device 50 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, radio frequency (RF) circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.
In
For the purpose of illustration, several types of first level packaging, including bond wire package 56 and flipchip 58, are shown on PCB 52. Additionally, several types of second level packaging, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, land grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, quad flat package 72, embedded wafer level ball grid array (eWLB) 74, and wafer level chip scale package (WLCSP) 76 are shown mounted on PCB 52. In one embodiment, eWLB 74 is a fan-out wafer level package (Fo-WLP) and WLCSP 76 is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages.
By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.
An electrically conductive layer 132 is formed over active surface 130 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 132 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer 132 operates as contact pads electrically connected to the circuits on active surface 130.
Semiconductor wafer 120 undergoes electrical testing and inspection as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 120. Software can be used in the automated optical analysis of semiconductor wafer 120. Visual inspection methods may employ equipment such as a scanning electron microscope, high-intensity or ultra-violet light, or metallurgical microscope. Semiconductor wafer 120 is inspected for structural characteristics including warpage, thickness variation, surface particulates, irregularities, cracks, delamination, and discoloration.
The active and passive components within semiconductor die 124 undergo testing at the wafer level for electrical performance and circuit function. Each semiconductor die 124 is tested for functionality and electrical parameters, as shown in
In
In
In
Substrate 170 includes one or more electrically conductive layers or redistribution layers (RDL) 176 formed using sputtering, electrolytic plating, electroless plating, or other suitable deposition process. Conductive layers 176 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, titanium (Ti), tungsten (W), or other suitable electrically conductive material. Conductive layers 176 include lateral RDL layers to provide horizontal conduction paths across substrate 170. Conductive layers 176 are formed on or between insulating layers 172.
In
One or more openings 180 are formed completely through substrate 170. Openings 180 can be formed by a punch, a mechanical drill, a laser drill, a water drill, a saw blade, by patterning insulating layers 172 and conductive layers 176 as substrate 170 is built-up, or by another suitable process. Opening 180 is formed outside of device region 171, so device layout options are not significantly reduced by the opening. Opening 180 allows a molding compound or encapsulant to flow between the top and bottom sides of substrate 170 during a subsequent molding step.
In
Bump material is also deposited over other portions of bottom surface 177 to form conductive bumps 186. Conductive bumps 186 are formed similarly to conductive bumps 134 above. The material for conductive bumps 186 may be deposited as a paste along with solder paste 182, or using a different material in a separate ball drop step. The bump material and solder paste 182 are reflowed to form conductive bumps 186 and to mechanically and electrically couple discrete devices 184 to conductive layer 176. Solder paste 182 may be reflowed prior to depositing conductive bumps 186 to hold discrete devices 184 in place during the ball drop process.
In
Solder paste 182 is patterned onto top surface 179 of substrate 170, and any desired discrete devices 184 are surface mounted as described above. Semiconductor die 124a and 124b are flip-chip mounted onto top surface 179. Semiconductor die 124a and 124b can implement different functionality desired for the package being created, e.g., semiconductor die 124a might be an application processor, and semiconductor die 124b might be a memory chip that the application processor uses. Conductive bumps 134 are reflowed to mechanically and electrically connect semiconductor die 124 to conductive layer 176. Semiconductor die 124 and discrete devices 184 on top surface 179 are electrically connected to discrete devices 184 and conductive bumps 186 on bottom surface 177 through conductive layers 176 and conductive vias 174.
In
Bottom plate 200a includes a mold film 202 within cavity 200d. Mold film 202 is formed from any suitable material. In some embodiments, an insulating polymer material is used. In one embodiment, mold film 202 extends outside of mold 200 between plates 200a and 200b, and is pulled down to contact bottom plate 200a by using a vacuum connected to bottom plate 200a to remove air between the mold film and bottom plate.
Substrate 160 is disposed within mold 200 over mold film 202. Conductive bumps 186 are pressed into mold film 202, and the conductive bumps displace a portion of the mold film material. In one embodiment, mold film 202 has a low elastic modulus to help conductive bumps 186 be inserted into the film. In
Encapsulant 210 is injected into opening 200c and takes two different paths to cover substrate 170. A first portion of encapsulant 210 follows path 212a to cover top surface 179 including semiconductor die 124 and discrete device 184c. A second portion of encapsulant 210 follows path 212b through opening 180 to cover bottom surface 177 of substrate 170, including covering exposed portions of conductive bumps 186 and discrete devices 184a-184b.
In
Conductive bumps 186 are exposed from and extend over a bottom surface of encapsulant 210 because of the conductive bumps being partially embedded within mold film 202 while encapsulant 210 is deposited. Discrete devices 184a-184b include a shorter height over bottom surface 177 than conductive bumps 186, and are not embedded in mold film 202 during molding. Therefore, encapsulant 210 fully covers discrete devices 184 but not conductive bumps 186. In other embodiments, a device mounted on surface 177, whether a semiconductor die 124, discrete device 184, or other component, may be embedded in mold film 202 in addition to conductive bumps 186 and will be exposed from encapsulant 210 when the molded panel is removed from mold 200. In one embodiment, mold film 202 is a thermal or UV release film for easier removal from encapsulant 210 and conductive bumps 186 in case the mold film sticks to the device.
In
The double-sided molding method employed in forming SIP package 220 requires only a single molding step, saving time and capital expenditure required to set up a manufacturing line with two separate molding steps. A single molding step is also more straightforward from a technical standpoint due to reduced substrate strip warpage and cycle time. Opening 180 at the edge of substrate 170, near sidewalls of mold 200, or in saw streets of the substrate, maintains design flexibility within device region 171.
Substrate 170 with conductive pillars 232 formed, and with semiconductor die 124 and discrete devices 184 disposed on the substrate, is placed into mold 200 with ends of the conductive pillars embedded into mold film 202. Mold film 202 blocks encapsulant 210 from completely covering conductive pillars 232, so the conductive pillars extend from the encapsulant after removal from mold 200. SIP package 230 can be mounted to PCB 52 and electrically connected to traces 54 using solder paste or another suitable mechanism. Conductive pillars 232 increase the potential pitch of interconnect between substrate 170 and PCB 52 relative to conductive bumps 186. Conductive bumps 168 are reflowed, and must be kept a minimum distance apart to reduce the likelihood that two conductive bumps reflow together and short circuit. Conductive pillars 232 are formed in a manner that can be at a tighter pitch without significantly increasing risk of a short circuit.
In
Leadframe 250 is disposed over substrate 170 with conductive pillars 252 oriented toward the substrate and aligned with contact pads of conductive layer 176. Solder paste 254 is printed or otherwise disposed on pillars 252 or conductive layer 176 and reflowed to electrically and mechanically couple leadframe 250 to substrate 170. Substrate 170 is flipped to mount any desired components to top surface 179.
In
In
In one embodiment, extensions 262 and 264 run continuously for the length of each column 259. Extensions 262 and 264 separate each column 259 of device regions 171 into an isolated chamber 266a-266c. Mold 260 includes an opening for each column 259 to inject encapsulant 210 into each column at once. Encapsulant 210 does not flow across the boundary between columns 259 established by extensions 262 and 264, even though the encapsulant freely flows between bottom plate 260a and top plate 260b through openings 180. In other embodiments, extensions 262 and 264 are provided as pillars or other structures that do not fully separate adjacent columns 259. Encapsulant 210 would then flow between adjacent columns 259.
Formation of devices proceeds similarly to
When substrate 170 is placed on bottom plate 270, any discrete device 184 and semiconductor die 124 on bottom surface 177 lie within finger cavity 274 so that bottom surface 177 contacts platforms 272 of the bottom plate. When encapsulant 210 is injected into the mold, cavity 200d of top plate 200b and finger cavity 274 of bottom plate 270 are filled with encapsulant to cover discrete devices 184 and semiconductor die 124. Portions of conductive layer 176 on bottom surface 177 to be used for external interconnection to the final package are in contact with platforms 272. The portions of conductive layer 176 contacting platforms 272 remain devoid of, or exposed from, encapsulant 210 after molding. Platforms 272 in contact with substrate 170 block encapsulant from flowing over the portions of conductive layer 176 to be used for external interconnection.
In
In
In
In
In
While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.
Kim, Yongmin, Lee, Heesoo, Yang, DeokKyung, Choi, Jaehyuk, Ko, YeoChan
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