A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.
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1. A circuit device comprising:
a first output signal line from which a first output signal constituting differential output signals is output;
a second output signal line from which a second output signal constituting the differential output signals is output; and
first to n-th output drivers for differential input and differential output that are coupled to the first output signal line and the second output signal line, n being an integer of 2 or more, wherein
in a first mode, i number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on a first input signal and a second input signal constituting differential input signals, i being an integer of 1≤i≤n,
in a second mode, j number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal, j being an integer of 1≤j≤n and j≠i, and
the first to n-th output drivers include
output drivers of a first group including drive current sources that apply drive currents each having a current value Is, and
output drivers of a second group including drive current sources that apply drive currents each having a current value a×Is, a being an integer of 2 or more.
13. A circuit device comprising:
a first output signal line from which a first output signal constituting differential output signals is output;
a second output signal line from which a second output signal constituting the differential output signals is output; and
first to n-th output drivers for differential input and differential output that are coupled to the first output signal line and the second output signal line, n being an integer of 2 or more, wherein
in a first mode, i number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on a first input signal and a second input signal constituting differential input signals, i being an integer of 1≤i≤n,
in a second mode, j number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal, j being an integer of 1≤j≤n and j≠i, and
each output driver of the first to n-th output drivers includes
a first transistor provided between a node of a power supply at a high potential side and a first node,
a second transistor provided between the first node and the first output signal line,
a third transistor provided between the first node and the second output signal line,
a fourth transistor provided between the first output signal line and a second node,
a fifth transistor provided between the second output signal line and the second node, and
a sixth transistor provided between the second node and a node of a power supply at a low potential side.
4. The circuit device according to
the first to n-th output drivers include output drivers of a third group including drive current sources that apply drive currents each having a current value b×Is, b being an integer of 2 or more and b≠a.
5. The circuit device according to
a bias current circuit that is coupled to the first output signal line and the second output signal line and applies a bias current to the first output signal line and the second output signal line from a power supply at a high potential side.
6. The circuit device according to
each output driver of the first to n-th output drivers includes
a first transistor provided between a node of a power supply at a high potential side and a first node,
a second transistor provided between the first node and the first output signal line,
a third transistor provided between the first node and the second output signal line,
a fourth transistor provided between the first output signal line and a second node,
a fifth transistor provided between the second output signal line and the second node, and
a sixth transistor provided between the second node and a node of a power supply at a low potential side.
7. The circuit device according to
the first to third transistors are P-type transistors, and the fourth to sixth transistors are N-type transistors.
8. The circuit device according to
in the first mode, operations of output drivers other than the i number of output drivers of the first to n-th output drivers are turned off, and
in the second mode, operations of output drivers other than the j number of output drivers of the first to n-th output drivers are turned off.
9. The circuit device according to
an oscillation signal generation circuit that generates an oscillation signal by using a resonator, wherein
the first input signal and the second input signal are signals based on the oscillation signal.
14. The circuit device according to
a bias current circuit that is coupled to the first output signal line and the second output signal line and applies a bias current to the first output signal line and the second output signal line from a power supply at a high potential side.
15. The circuit device according to
the first to third transistors are P-type transistors, and the fourth to sixth transistors are N-type transistors.
16. The circuit device according to
in the first mode, operations of output drivers other than the i number of output drivers of the first to n-th output drivers are turned off, and
in the second mode, operations of output drivers other than the j number of output drivers of the first to n-th output drivers are turned off.
17. The circuit device according to
an oscillation signal generation circuit that generates an oscillation signal by using a resonator, wherein
the first input signal and the second input signal are signals based on the oscillation signal.
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The present application is based on, and claims priority from JP Application Serial Number 2018-166529, filed Sep. 6, 2018, the disclosure of which is hereby incorporated by reference herein in its entirety.
The present disclosure relates to a circuit device, an oscillator, an electronic apparatus, and a vehicle.
The related art of an output circuit that outputs a differential output signal includes, for example, a technology disclosed in JP-A-2007-324799. The output circuit includes a differential output section that amplifies an input differential signal and outputs the amplified differential signal, a current source section that supplies current to the differential output section, a load resistance section that is coupled to the differential output section, and a control unit that sets a current value of the current source section and a resistance value of the load resistance section. The output circuit converts the differential signal into an output signal having a different interface level, and transmits the converted signal through balancing.
In the output circuit described in JP-A-2007-324799, a differential signal having a level conforming to a standard of each interface is output by setting the current value of the current source section and the resistance value of the load resistance section by means of a control unit. However, JP-A-2007-324799 neither discloses nor suggests a technical point of view to cope with various interfaces while suppressing an increase in circuit area.
An advantage of some aspects of the present disclosure is to solve at least a part of the problems described above, and the present disclosure can be implemented as the following aspects or embodiments.
An aspect of the present disclosure relates to a circuit device including a first output signal line from which a first output signal constituting differential output signals is output, a second output signal line from which a second output signal constituting the differential output signals is output, and first to n-th output drivers for differential input and differential output that are coupled to the first output signal line and the second output signal line, n being an integer of 2 or more. In a first mode, i number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on a first input signal and a second input signal constituting differential input signals, i being an integer of 1≤i≤n, and in a second mode, j number of output drivers of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal, j being an integer of 1≤j≤n and j≠i.
Hereinafter, a preferred embodiment of the present disclosure will be described in detail. The present embodiment to be described below does not wrongfully limit the contents of the present disclosure described in the appended Claims, and all configurations described in the present embodiment are not essential as means for solving in the present disclosure.
A configuration example of a circuit device 20 of the present embodiment is shown in
The output drivers DR1 to DRn are first to n-th output drivers. Here, n is an integer of 2 or more. The output drivers DR1 to DRn are drivers for differential input and differential output which are coupled to the output signal lines LQ1 and LQ2. An input signal IN and an input signal INX can be input to the output drivers DR1 to DRn. The input signal IN and the input signal INX are a first input signal and a second input signal, respectively, and are signals to be transmitted through balancing. For example, the input signal IN is a signal at a positive polarity side, and the input signal INX is a signal at a negative polarity side. For example, DR1 to DRn as a plurality of output drivers are commonly coupled to the output signal lines LQ1 and LQ2. The output drivers DR1 to DRn output signals obtained by buffering the input signals IN and INX, as the output signals OUT and OUTX. Specifically, the output drivers DR1 to DRn output, as the output signals OUT and OUTX, signals obtained by converting the input signals IN and INX each having, for example, a voltage amplification range of VDD to VSS so as to have signal waveforms corresponding to various interfaces such as LVDS, PECL, HCSL, and CMOS to be described below.
For example, each of the output drivers DR1 to DRn includes a current source, a differential section, and a load resistance section. For example, a transistor T1 of
In
In the present embodiment, in a first mode, i number of output drivers of the output drivers DR1 to DRn drive the output signal lines LQ1 and LQ2 based on the input signals IN and INX constituting the differential input signals. That is, the i number of output drivers output the output signals OUT and OUTX corresponding to the input signals IN and INX to the output signal lines LQ1 and LQ2. Specifically, the i number of output drivers output the output signals OUT and OUTX each having a signal waveform corresponding to an interface of the first mode to the output signal lines LQ1 and LQ2. Meanwhile, in a second mode, j number of output drivers of the output drivers DR1 to DRn drive the output signal lines LQ1 and LQ2 based on the input signals IN and INX constituting the differential input signals. That is, the j number of output drivers output the output signals OUT and OUTX corresponding to the input signals IN and INX to the output signal lines LQ1 and LQ2. Specifically, the j number of output drivers output the output signals OUT and OUTX each having a signal waveform corresponding to an interface of the second mode to the output signal lines LQ1 and LQ2. Here, i is an integer of 1≤i≤n, and j is an integer of 1≤j≤n and j #1. For example, i=j=1 is not satisfied. However, i=1 and j≥2 may be satisfied, or j=1 and i≥2 may be satisfied. For example, the first mode is an operation mode which realizes one interface of low voltage differential signaling (LVDS), positive emitter coupled logic (PECL), high speed current steering logic (HCSL), and a differential complementary MOS (CMOS). The second mode is an operation mode which realizes an interface different from the one interface. According to the circuit device 20 of the present embodiment having the configuration of
Next, LVDS, PECL, HCSL, and CMOS will be described.
Next, an operation of the circuit device 20 of the present embodiment will be described in detail with reference to
Specifically, in the output drivers DR1 to DR4, a bias voltage BSP1 is applied to the gate of the P-type transistor T1 as the current source. The signals corresponding to the input signals IN are input to the transistors T3 and T5 constituting the differential section, and the signals corresponding to the input signals INX are input to the transistors T2 and T4 constituting the differential section. Specifically, the signals obtained by buffering the input signals IN and INX are input as illustrated in
The bias voltage BSP1 is applied to the gate of the transistor T1 of each of the output drivers DR1 to DR4, and thus, a drive current of, for example, Is=875 μA flows in each output driver of the DR1 to DR4. Accordingly, a drive current of 4×875 μA=3.5 mA in total can flow similarly to the output driver of LVDS of
Meanwhile, in
Specifically, in the output drivers DR1 to DR18, the bias voltage BSP1 is applied to the gate of the transistor T1. The signal corresponding to the input signal IN is input to the transistor T3, and the signal corresponding to the input signal INX is input to the transistor T2. Meanwhile, VSS=GND is applied to the gates of the N-type transistors T4, T5, and T6, and thus, these transistors T4, T5, and T6 are turned off. The bias voltage BSP1 is applied to the gate of the transistor T1 of each of the output drivers DR1 to DR18, and thus, a drive current of 18×875 μA=15.75 mA in total can flow substantially similarly to the output driver of PECL of
The drive current of 18×875 μA=15.75 mA flows in
In
Meanwhile, in the output drivers DR19 to DR20, the transistors T1 and T6 are turned off by respectively applying VDD and VSS to the gates of the transistors T1 and T6. Accordingly, the operations of the output drivers DR19 and DR20 are turned off, and thus, the output signal lines LQ1 and LQ2 can be driven by only the bias current circuit 30 and the output drivers DR1 to DR18 of which the operations are turned on.
Specifically, in the output drivers DR1 to DR17, the bias voltage BSP1 is applied to the gate of the transistor T1. The signal corresponding to the input signal IN is input to the transistor T3 constituting the differential section, and the signal corresponding to the input signal INX is input to the transistor T2 constituting the differential section. Meanwhile, VSS=GND is applied to the gates of the N-type transistors T4, T5, and T6, and thus, these transistors T4, T5, and T6 are turned off. The bias voltage BSP1 is applied to the gate of the transistor T1 of each of the output drivers DR1 to DR17, and thus, the drive current of 17×875 μA=14.875 mA in total can flow substantially similarly to the output driver of HCSL of
The drive current of 17×875 μA=14.875 mA flows in
Meanwhile, in the output drivers DR18 to DR20, the transistors T1 and T6 are turned off by respectively applying VDD and VSS to the gates of the transistors T1 and T6. In the bias current circuit 30, the transistors TB3 and TB4 are also turned off by applying VDD to the gates thereof. Accordingly, the operations of the output drivers DR18 to DR20 and the bias current circuit 30 are turned off, and thus, the output signal lines LQ1 and LQ2 can be driven by only the output drivers DR1 to DR17 of which the operations are turned on.
Specifically, in the output drivers DR1 to DRm, the transistors T1 and T6 are turned on by applying VSS to the gate of the P-type transistor T1 and applying VDD to the gate of the N-type transistor T6. The signals corresponding to the input signals IN are input to the transistors T3 and T5, and the signals corresponding to the input signals INX are input to the transistors T2 and T4. Accordingly, the output drivers DR1 to DRm are operated as buffer circuits of CMOS for differential input and differential output which buffer the input signals IN and INX and output the full swing output signals OUT and OUTX each having the voltage range of VDD to VSS.
Meanwhile, in the output drivers DRm+1 to DR20, the transistors T1 and T6 are turned off by respectively applying VDD and VSS to the gates of the transistors T1 and T6. In the bias current circuit 30, the transistors TB3 and TB4 are also turned off by applying VDD to the gates of the transistors TB3 and TB4. Accordingly, the operations of the output drivers DRm+1 to DR20 and the bias current circuit 30 are turned off, and thus, the output signal lines LQ1 and LQ2 can be driven by only the output drivers DR1 to DRm of which the operations are turned on. In this manner, it is possible to adjust a slew rate in the driving of CMOS. For example, in order to increase the slew rate in the driving of CMOS, the number of output drivers DR1 to DRm that drive the output signal lines LQ1 and LQ2 is increased by increasing m. Meanwhile, in order to decrease the slew rate in the driving of CMOS, the number of output drivers DR1 to DRm that drive the output signal lines LQ1 and LQ2 is decreased by decreasing m.
As stated above, in the circuit device 20 of the present embodiment, the signals corresponding to the input signals IN and INX are input, and the plurality of output drivers DR1 to DRn commonly coupled to the output signal lines LQ1 and LQ2 is provided. In the first mode, the i number of output drivers of the output drivers DR1 to DRn drive the output signal lines LQ1 and LQ2. In the second mode, the j number of output drivers of the output drivers DR1 to DRn drive the output signal lines LQ1 and LQ2. With such a configuration, the output signal lines LQ1 and LQ2 can be driven with the signal waveform conforming to the standards of various interfaces such as LVDS, PECL, HCSL, and CMOS as described in
For example, as a method of a comparative example of the present embodiment, a method in which all the dedicated output drivers of LVDS, PECL, HCSL, and CMOS having the configurations shown in
In the circuit device 20 of the present embodiment, the bias current circuit 30 which is coupled to the output signal lines LQ1 and LQ2 and applies the bias current to the output signal lines LQ1 and LQ2 from VDD which is the power supply at the high potential side is provided. It is possible to realize the operation mode of the PECL or the like as described in
Although it has been described in
The input signals IN and INX are input to the control circuit 40. Specifically, the input signals IN and INX are input to the control blocks CTB1 to CTBn of the control circuit 40. For example, in
The control circuit 40 outputs the signals obtained by buffering the input signals IN and INX to the output drivers DR1 to DRn. For example, the control block CTB1 outputs the signal obtained by buffering the input signals IN and INX to the output driver DR1. The control block CTB2 outputs the signal obtained by buffering the input signals IN and INX to the output driver DR2. Similarly, the control blocks CTB3 to CTBn output the signals obtained by buffering the input signals IN and INX to the output drivers DR3 to DRn. The control circuit 40 outputs a control signal for turning on or off the transistors of the output drivers DR1 to DRn. In the example of
The bias voltage generation circuit 42 generates bias voltages, and supplies the generated bias voltages to the output drivers DR1 to DRn and the bias current circuit 30. For example, the bias voltage generation circuit 42 generates bias voltages BSP1 and BSN, and supplies the generated bias voltages to the gates of the transistors T1 and T6 of the output drivers DR1 to DRn. The bias voltage generation circuit 42 generates a bias voltage BSP2, and supplies the generated bias voltage to the gates of the transistors TB1 and TB2 of the bias current circuit 30.
Next, an arrangement configuration example of the output drivers DR1 to DRn of the present embodiment will be described. For example,
Each output driver of DR1 to DR20 includes a drive current source that applies a drive current having a current value Is. In the example of
With such a configuration, in the example of
In the first and second arrangement configuration examples of
In the present embodiment, the output drivers DR1 to DRn include the output drivers DA1 to DA4 of the first group GR1 including the drive current sources that apply the drive currents each having a current value Is and the output drivers DB1 to DB4 of the second group GR2 including the drive current sources that apply the drive currents each having a current value of a×Is=4×Is. In the example of
As stated above, in
According to the second arrangement configuration example of
In the example of
In the example of
In the example of
In the second arrangement configuration example of
As stated above, in
As shown in
In
In
The pre-buffers PB1 to PB4 and the setting circuit STC of
The resonator 10 is an element that generates mechanical vibration by an electrical signal. For example, the resonator 10 may be realized by a resonator element such as a quartz crystal resonator element. For example, the resonator 10 may be realized by a quartz crystal resonator element that has a cut angle of AT cut or SC cut and performs thickness-shear vibration. For example, the resonator 10 may be a resonator of a simple packaged crystal oscillator (SPXO). Alternatively, the resonator 10 may be a resonator built in a thermostatic crystal oscillator (OCXO) including a thermostatic chamber, or may be a resonator built in a temperature compensated crystal oscillator (TCXO) not including a thermostatic chamber. For example, the resonator 10 of the present embodiment may be realized by various resonator elements such as a resonator element other than the thickness-shear resonator and a piezoelectric resonator element made of a material other than quartz crystal. For example, a surface acoustic wave (SAW) resonator or a micro electro mechanical systems (MEMS) resonator as a silicon resonator formed by using a silicon substrate may be adopted as the resonator 10.
The circuit device 20 is an integrated circuit (IC) manufactured through a semiconductor process, and is a semiconductor chip at which a circuit element is formed on the semiconductor substrate. The circuit device 20 includes the oscillation signal generation circuit 70 and an output circuit 90. The circuit device 20 may include a processing circuit 50, an interface circuit 60, and the bias voltage generation circuit 42.
The oscillation signal generation circuit 70 includes an oscillation circuit 80, and a phase locked loop (PLL) circuit 82. The oscillation circuit 80 oscillates the resonator 10, and generates the oscillation signal OSCK. For example, the oscillation circuit 80 performs driving for oscillating the resonator 10, and generates the oscillation signal OSCK. For example, a Pierce quartz crystal oscillation circuit may be used as the oscillation circuit 80.
The PLL circuit 82 generates the input signals IN and INX for the output circuit 90 based on the oscillation signal OSCK from the oscillation circuit 80. For example, the PLL circuit generates, as the input signals IN and INX, signals obtained by multiplying a frequency of the oscillation signal OSCK, and outputs the generated signals to the output circuit 90. For example, a fractional-N type PLL circuit may be used as the PLL circuit 82. For example, the PLL circuit 82 generates, as input signals IN and INX, signals each having a frequency corresponding to a frequency code set by the processing circuit 50.
The output circuit 90 includes the output drivers DR1 to DRn, and the control circuit 40. The output circuit outputs the output signals OUT and OUTX based on the input signals IN and INX. That is, the output circuit outputs the output signals OUT and OUTX each having the signal waveform of the interface corresponding to the set operation mode. The output signals OUT and OUTX are output to the outside through an external coupling terminal of the oscillator 4. The output circuit 90 may output the output signals OUT and OUTX of multiple channels. For example, the output circuit may output the output signals OUT and OUTX of an operation mode of an interface different for each channel of the multiple channels. For example, on a first channel, the output circuit may output the output signals OUT and OUTX of the operation mode of any of LVDS, PECL, HCSL, and CMOS. On a second channel, the output circuit may output the output signals OUT and OUTX of the operation mode of any of LVDS, PECL, HCSL, and CMOS independent of the first channel.
The bias voltage generation circuit 42 generates the bias voltage for setting the drive currents flowing in the output drivers DR1 to DRn of the output circuit 90. For example, the bias voltage generation circuit 42 may be realized by an analog circuit constituted by an operational amplifier, a transistor, a resistor, or a capacitor.
The processing circuit 50 performs various control processing or setting processing of the circuit device 20. For example, the processing circuit 50 performs setting processing of the operation mode and setting processing of the output channel. The processing circuit 50 performs control processing of each circuit block of the circuit device 20. The processing circuit 50 may perform digital signal processing such as temperature compensation processing, aging correction processing, or digital filter processing. When the temperature compensation processing is performed, a temperature sensor is provided, and the processing circuit 50 performs the temperature compensation processing for compensating for temperature characteristics of the oscillation frequency based on temperature detection information from the temperature sensor, and outputs frequency control data for controlling the oscillation frequency. Specifically, the processing circuit 50 performs the temperature compensation processing for canceling or suppressing variation in oscillation frequency caused by a change in temperature based on temperature detection data changed depending on the temperature and data of temperature compensation coefficient which is an approximation function. That is, even when the temperature is changed, the processing unit performs the temperature compensation processing such that the oscillation frequency is constant. The processing circuit 50 may be realized by a circuit of an application specific integrated circuit (ASIC) using automatic placement and routing such as a gate array. Alternatively, the processing circuit 50 may be realized by a processor such as a digital signal processor (DSP) or a central processing unit (CPU).
The interface circuit 60 is a circuit that realizes an interface such as Inter Integrated Circuit (I2C) or Serial Peripheral Interface (SPI). That is, the interface circuit 60 performs interface processing between the oscillator 4 and an external device. It is possible to set the block frequencies or the output channels of the output signals OUT and OUTX by using the interface circuit 60.
For example, the electronic apparatus 500 is a network-related apparatus such as a base station or a router, a high-accuracy measurement apparatus that measures physical quantities such as a distance, a time, a flow velocity, and a flow rate, a biological information measurement apparatus that measure biological information, or an in-vehicle apparatus. For example, the biological information measurement apparatus is an ultrasonic measurement device, a sphygmograph, or a blood pressure measurement device. The in-vehicle apparatus is an apparatus for automatic driving. The electronic apparatus 500 may be a wearable apparatus such as a head-mounted display device or a timepiece-related apparatus, a robot, a printing device, a projection device, a portable information terminal such as a smartphone, a content providing apparatus that distributes contents, or a video apparatus such as a digital camera or a video camera.
The communication interface 510 receives data from the outside through the antenna ANT, or performs processing for transmitting data to the outside. The processing device 520 which is the processor performs control processing of the electronic apparatus 500 and various digital processing of data transmitted and received through the communication interface 510. For example, the functions of the processing device 520 may be realized by a processor such as a microcomputer. The operation interface 530 is used by a user who performs an input operation, and may be realized by an operation button or a touch panel display. The display unit 540 displays various information, and may be realized by a liquid crystal or organic EL display. The memory 550 stores data, and the functions thereof may be realized by a semiconductor memory such as RAM or ROM.
As described above, the circuit device of the present embodiment includes the first output signal line from which the first output signal constituting the differential output signals is output, the second output signal line from which the second output signal constituting the differential output signals is output, and the first to n-th output drivers (n is an integer of 2 or more) for differential input and differential output coupled to the first output signal line and the second output signal line. In the first mode, the i number of output drivers (i is an integer of 1≤i≤n) of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal constituting the differential input signals. In the second mode, the j number of output drivers (j is an integer of 1≤j≤n and j≠i) of the first to n-th output drivers drive the first output signal line and the second output signal line based on the first input signal and the second input signal.
As stated above, in the present embodiment, the first and second output signal lines and the first and n-th output drivers that drive the first and second output signal lines based on the first and second input signals are provided at the circuit device. In the first mode, the i number of output drivers drive the first and second output signal lines, and thus, the first and second output signal lines can be driven with the signal waveform conforming to the standard of the first interface, for example. Meanwhile, in the second mode, the j number of output drivers drive the first and second output signal lines, and thus, the first and second output signal lines can be driven with the signal waveform conforming to the standard of the second interface, for example. In the present embodiment, since the first and second output signal lines can be driven by setting the output drivers required for each interface among the first to n-th output drivers, it is possible to suppress the increase in circuit area of the circuit device. Accordingly, it is possible to provide the circuit device capable of realizing the operation modes of various interfaces while suppressing the increase in circuit area.
In the present embodiment, the first to n-th output drivers may include the output drivers of the first group including the drive current sources that apply the drive currents each having the current value Is and the output drivers of the second group including the drive current sources that apply the drive currents each having the current value a×Is (a is an integer of 2 or more).
In this manner, it is possible to cope with the operation modes of various interfaces in which the current values of the drive currents are different by turning on the operations of some output drivers of the output drivers of the first group that apply the drive currents each having the current value Is or turning on the operations of some output drivers of the output drivers of the second group that apply the drive currents each having the current value a×Is.
In the present embodiment, n may be 8, and a may be 4. In this manner, the output drivers of the first group that apply the drive currents each having the current value Is and the output drivers of the second group that apply the drive currents each having the current value 4×Is are provided as the first to eighth output drivers. It is possible to cope with the operation modes of various interfaces in which the current values of the drive currents are different by turning on the operations of some output drivers of the first group that apply the drive currents each having the current value Is or turning on the operations of some output drivers of the second group that apply the drive currents each having the current value 4×Is.
In the present embodiment, Is may be 875 μA. In this manner, it is possible to cope with the operation modes of various interfaces required to apply drive currents having current values corresponding to multiple of Is=875 JLA.
In the present embodiment, the first to n-th output drivers may include the output drivers of the third group including the drive current sources that apply the drive currents each having the current value b×Is (b is an integer of 2 or more and b≠a).
In this manner, it is possible to cope with the operation modes of various interfaces by turning on the operations of some output drivers of the first group that apply the drive currents each having the current value Is, turning on the operations of some output drivers of the second group that apply the drive currents each having the current value a×Is, or turning on the operations of some output drivers of the third group that apply the drive currents each having the current value b×Is.
In the present embodiment, the circuit device may include the bias current circuit that is coupled to the first output signal line and the second output signal line and applies the bias current to the first output signal line and the second output signal line from the power supply at the high potential side.
In this manner, the first and second output signal lines can be driven by using the bias current from the bias current circuit in addition to the drive currents from the output drivers when coping with an operation mode of a predetermined interface.
In the present embodiment, each output driver of the first to n-th output drivers may include the first transistor provided between the node of the power supply at the high potential side and the first node, the second transistor provided between the first node and the first output signal line, and the third transistor provided between the first node and the second output signal line. Each output driver may include the fourth transistor provided between the first output signal line and the second node, the fifth transistor provided between the second output signal line and the second node, and the sixth transistor provided between the second node and the node of the power supply at the low potential side.
In this manner, the first and second output signal lines can be driven by the first transistor as the transistor for the drive current source and using the differential section constituted by the second, third, fourth, and fifth transistors.
In the present embodiment, the first to third transistors may be the P-type transistors, and the fourth to sixth transistors may be the N-type transistors.
In this manner, the current source at the high potential side may be realized by the P-type first transistor, and the load resistance section at the low potential side may be realized by the N-type sixth transistor. The differential section may be realized by the P-type second and third transistors and the N-type fourth and fifth transistors.
In the present embodiment, the operations of the output drivers other than the i number of output drivers of the first to n-th output drivers may be turned off in the first mode, the operations of the output drivers other than the j number of output drivers of the first to n-th output drivers may be turned off in the second mode.
In this manner, the first and second output signal lines can be driven by using only the i number of output drivers in the first mode, and the first and second output signal lines can be driven by using only the j number of output drivers in the second mode. Accordingly, it is possible to appropriately drive the first and second output signal lines by using output drivers as much as the output drivers corresponding to each interface.
In the present embodiment, the circuit device may include the oscillation signal generation circuit that generates the oscillation signal by using the resonator, and the first input signal and the second input signal may be the signals based on the oscillation signal.
In this manner, the signals obtained by buffering the first and second input signals based on the oscillation signal generated by using the resonator by means of the first to n-th output drivers can be output as the first and second output signals each having the signal waveform corresponding to each interface.
The present embodiment relates to the oscillator including the circuit device and the resonator.
The present embodiment relates to the electronic apparatus including the aforementioned circuit device.
The present embodiment relates to the vehicle including the aforementioned circuit device.
While the present embodiment has been described in detail, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of the present disclosure. Therefore, all the modifications may be included in the scope of the present disclosure. For example, in the specification or drawings, the terms described together with broader or synonymous different terms at least once may be replaced with different terms in any of the specification or drawings. All combinations of the present embodiment and the modification example are also included in the present embodiment. The configurations and operations of the circuit device, the oscillator, the electronic apparatus, and the vehicle or the circuit configuration and arrangement configuration of the output drivers are also not limited to those described in the present embodiment, and may be variously modified.
Kozaki, Minoru, Komatsu, Fumikazu
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 7145359, | Jun 28 2004 | Skyworks Solutions, Inc | Multiple signal format output buffer |
| 20070279124, | |||
| 20080106301, | |||
| JP2007324799, | |||
| JP2008118382, | |||
| JP9162717, |
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