A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.
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1. A recessed access device comprising:
a conductive gate in a trench in semiconductor material, the conductive gate in a straight-line vertical cross-section having opposing sidewalls and a bottom below and extending between the opposing sidewalls;
a gate insulator between the conductive gate and the semiconductor material, the gate insulator being along the opposing sidewalls and the bottom of the conductive gate in the straight-line vertical cross-section;
a pair of source/drain regions in upper portions of the semiconductor material on opposing sides of the trench in the straight-line vertical cross-section; and
a channel region in the semiconductor material, the channel region having a pair of top surfaces below the pair of source/drain regions in the straight-line vertical cross-section, the channel region being below the pair of source/drain regions along the opposing sidewalls of the conductive gate and around the bottom of the conductive gate in the straight-line vertical cross-section, those portions of the channel region that are along all of the opposing sidewalls of the conductive gate below the pair of source/drain regions in the straight-line vertical cross-section comprising GaP, that portion of the channel region that is directly below the bottom of the conductive gate in the straight-line vertical cross-section being devoid of GaP.
9. A recessed access device comprising:
a conductive gate in a trench in semiconductor material, the conductive gate in a straight-line vertical cross-section having opposing sidewalls and a bottom below and extending between the opposing sidewalls;
a gate insulator between the conductive gate and the semiconductor material, the gate insulator being along the opposing sidewalls and the bottom of the conductive gate in the straight-line vertical cross-section;
a pair of source/drain regions in upper portions of the semiconductor material on opposing sides of the trench in the straight-line vertical cross-section; and
a channel region in the semiconductor material, the channel region having a pair of top surfaces below the pair of source/drain regions in the straight-line vertical cross-section, the channel region being below the pair of source/drain regions along the opposing sidewalls of the conductive gate and around the bottom of the conductive gate in the straight-line vertical cross-section, the channel region comprising:
a pair of first portions along upper portions of the opposing sidewalls of the conductive gate that are below the pair of source/drain regions in the straight-line vertical cross-section, the first portions comprising GaP;
a pair of second portions along the opposing sidewalls of the conductive gate below the pair of first portions in the straight-line vertical cross-section, the second portions being devoid of GaP; and
a third portion below the pair of second portions in the straight-line vertical cross-section, the third portion extending around the bottom of the conductive gate in the straight-line vertical cross-section and being devoid of GaP.
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Embodiments disclosed herein pertain to recessed access devices and to DRAM constructions.
A recessed access device is a field effect transistor having its gate construction buried within a trench formed in semiconductive material. The gate construction includes a gate insulator which lines the trench and conductive gate material within the trench laterally inward of the gate insulator. A source/drain region is formed in outermost regions of the semiconductive material on each of opposing sides of the trench. When the two source/drain regions are at different voltages and a suitable voltage is applied to the conductive gate material, current (Ion) flows through the semiconductive material between the source/drain regions along the trench sidewalls and around the base of the trench (i.e., a conductive channel forms through which current flows between the two source/drain regions). It is desirable to attain high device on-current (Ion) and low device off-current (e.g. leakage current Ioff) in recessed access devices.
Recessed access devices are typically devoid of non-volatile charge-storage devices (yet may be fabricated to include such), and regardless may be used in memory circuitry, for example DRAM circuitry. Achieving lower Ioff may result in less disturb and longer retention of the information stored in a memory cell incorporating a recessed access device.
Embodiments of the invention encompass recessed access devices and DRAM constructions. First example embodiments are initially described with reference to
Base substrate 11 comprises semiconductor material 12 (e.g., appropriately and variously doped monocrystalline silicon and/or other semiconductive material), trench isolation regions 14 (e.g., silicon nitride and/or doped or undoped silicon dioxide), and active area regions 16 comprising suitably and variously-doped semiconductor material 12. In one embodiment, construction 8 comprises memory cells 75 (
Field effect transistors 25 are in the form of recessed access devices (a type of construction of a field effect transistor), with
One of the source/drain regions (e.g., region 26) of the pair of source/drain regions is laterally between conductive gate material 22 and is shared by the pair of devices 25. Others of the source/drain regions (e.g., regions 24) of the pair of source/drain regions are not shared by the pair of devices 25. Thus, in the example embodiment, each active area region 16 comprises two devices 25 with each sharing a central source/drain region 26. A digitline 30 is directly electrically coupled to the one shared source/drain region 26. A pair of capacitors 85 individually are directly electrically coupled to one of the other source/drain regions 24. A conductive via 34 is shown interconnecting shared source/drain region 26 with digitline 30. Conductive vias 36 are shown interconnecting non-shared source/drain regions 24 with individual capacitors 85. Example insulator material 38 (e.g., comprising, consisting essentially of, or consisting of silicon nitride and/or doped or undoped silicon dioxide) surrounds vias 34, 36.
A channel region 27 is in semiconductor material 12 below pair of source/drain regions 24, 26 along trench sidewalls 21 and around trench base 23. Channel region 27 may be suitably doped with a conductivity-increasing dopant likely of the opposite conductivity-type of the dopant in source/drain regions 24, 26, and for example that is at a maximum concentration in the channel of no greater than 1×1016 atoms/cm3. When suitable voltage is applied to gate material 22 of an access line construction 18, a conductive channel forms (e.g., along a channel current-flow line/path 29 [
At least some of channel region 27 comprises GaP (gallium phosphide).
In one embodiment, pair of source/drain regions 24, 26 comprises GaP, and in one such embodiment consists essentially of GaP and conductivity-modifying dopant therein, or consists of GaP and conductivity-modifying dopant therein.
Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments of
An alternate example embodiment DRAM construction 8a comprising a pair of recessed access devices 25a is shown in
Another alternate example embodiment DRAM construction 8b comprising a pair of recessed access devices 25b is shown in
The example embodiments may be manufactured using any existing or future-developed method(s). For example, trenches 19 including portions thereof in which insulator material 38 is received could be formed in semiconductor material 12. Alternately, by way of example only, GaP-containing material could be formed above Si-containing material and trenches 19 could be formed in the GaP-containing material. Epitaxial growth may be used.
In this document unless otherwise indicated, “elevational”, “higher”, “upper”, “lower”, “top”, “atop”, “bottom”, “above”, “below”, “under”, “beneath”, “up”, and “down” are generally with reference to the vertical direction. “Horizontal” refers to a general direction (i.e., within 10 degrees) along a primary substrate surface and may be relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to “exactly horizontal” is the direction along the primary substrate surface (i.e., no degrees there-from) and may be relative to which the substrate is processed during fabrication. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending” and “extend(ing) elevationally” refer to a direction that is angled away by at least 450 from exactly horizontal. Further, “extend(ing) elevationally”, “elevationally-extending”, extend(ing) horizontally, and horizontally-extending with respect to a field effect transistor are with reference to orientation of the transistor's channel length along which current flows in operation between the source/drain regions. For bipolar junction transistors, “extend(ing) elevationally” “elevationally-extending”, extend(ing) horizontally, and horizontally-extending, are with reference to orientation of the base length along which current flows in operation between the emitter and collector.
Further, “directly above” and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).
Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.
Additionally, “thickness” by itself (no preceding directional adjective) is defined as the mean straight-line distance through a given material or region perpendicularly from a closest surface of an immediately-adjacent material of different composition or of an immediately-adjacent region. Additionally, the various materials or regions described herein may be of substantially constant thickness or of variable thicknesses. If of variable thickness, thickness refers to average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the thickness being variable. As used herein, “different composition” only requires those portions of two stated materials or regions that may be directly against one another to be chemically and/or physically different, for example if such materials or regions are not homogenous. If the two stated materials or regions are not directly against one another, “different composition” only requires that those portions of the two stated materials or regions that are closest to one another be chemically and/or physically different if such materials or regions are not homogenous. In this document, a material, region, or structure is “directly against” another when there is at least some physical touching contact of the stated materials, regions, or structures relative one another. In contrast, “over”, “on”, “adjacent”, “along”, and “against” not preceded by “directly” encompass “directly against” as well as construction where intervening material(s), region(s), or structure(s) result(s) in no physical touching contact of the stated materials, regions, or structures relative one another.
Herein, regions-materials-components are “electrically coupled” relative one another if in normal operation electric current is capable of continuously flowing from one to the other, and does so predominately by movement of subatomic positive and/or negative charges when such are sufficiently generated. Another electronic component may be between and electrically coupled to the regions-materials-components. In contrast, when regions-materials-components are referred to as being “directly electrically coupled”, no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) is between the directly electrically coupled regions-materials-components.
Additionally, “metal material” is any one or combination of an elemental metal, a mixture or an alloy of two or more elemental metals, and any conductive metal compound.
In some embodiments, a recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.
In some embodiments, a recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. Those portions of the channel region that are along all of the trench sidewalls below the pair of source/drain regions comprise GaP. That portion of the channel region that is directly below the trench base is devoid of GaP.
In some embodiments, a recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. Those portions of the channel region that are along all of the trench sidewalls below the pair of source/drain regions and that portion of the channel region that is around the trench base comprising GaP.
In some embodiments, a recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. The channel region comprises a pair of first portions along upper portions of the trench sidewalls that are below the pair of source/drain regions. The first portions comprise GaP. A pair of second portions is along the trench sidewalls below the pair of first portions. The second portions are devoid of GaP. A third portion is below the pair of second portions. The third portion extends around the trench base and is devoid of GaP.
In some embodiments, a DRAM construction comprises a pair of recessed access devices individually comprising a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP. One of the source/drain regions of the pair of source/drain regions is laterally between the conductive gates and is shared by the pair of recessed access devices. The others of the source/drain regions of the pair of source/drain regions are not shared by the pair of recessed access devices. A digitline is directly electrically coupled to the one shared source/drain region. A pair of capacitors individually are directly electrically coupled to one of the other source/drain regions.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
Sandhu, Gurtej S., Liu, Haitao, Hill, Richard J., Pulugurtha, Srinivas, Karda, Kamal M., Pandey, Deepak Chandra, Gao, Yunfei
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