In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.
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1. A pillar-shaped semiconductor device comprising:
a first semiconductor pillar on a substrate and extending in a direction perpendicular to the substrate;
a first impurity region below the first semiconductor pillar;
a first impurity region connection layer connecting to the first impurity region, extending in a horizontal direction, and comprising a semiconductor or a conductor;
a second impurity region above the first semiconductor pillar;
a first gate insulating layer surrounding the first semiconductor pillar between the first impurity region and the second impurity region;
a first gate conductor layer surrounding the first gate insulating layer;
a second semiconductor pillar on the substrate and extending in the direction perpendicular to the substrate;
a third impurity region below the second semiconductor pillar;
a fourth impurity region above the second semiconductor pillar;
a second gate insulating layer surrounding the second semiconductor pillar between the third impurity region and the fourth impurity region;
a second gate conductor layer surrounding the second gate insulating layer;
a second gate connection conductor layer connecting to the second gate conductor layer, extending in a horizontal direction, and comprising a conductor;
a first contact hole connecting to the first impurity region connection layer and the second gate connection conductor layer, and having a portion overlapping, in plan view, at least the second gate connection conductor layer, the portion having a bottom portion positioned, in the perpendicular direction, lower than upper surfaces of the second gate conductor layer and the second gate connection conductor layer; and
a first connection conductor layer within the first contact hole and connecting to the first impurity region connection layer and the second gate connection conductor layer.
10. A method for producing a pillar-shaped semiconductor device including
a first impurity region, a first semiconductor pillar, and a second impurity region disposed on a substrate in a hierarchical manner and in a direction perpendicular to the substrate;
a third impurity region, a second semiconductor pillar, and a fourth impurity region that are disposed on the substrate; in a hierarchical manner in the direction perpendicular to, the substrate,
the first impurity region below the first semiconductor pillar,
the third impurity region below the second semiconductor pillar; and
a first impurity region connection layer, formed of a semiconductor or a conductor, connecting to the first impurity region, and extending in a horizontal direction,
the method comprising:
forming a first gate insulating layer so as to surround the first semiconductor pillar;
forming a second gate insulating layer so as to surround the second semiconductor pillar;
forming a first gate conductor layer so as to surround the first gate insulating layer;
forming a second gate conductor layer so as to surround the second gate insulating layer;
forming a second gate connection conductor layer connecting to the second gate conductor layer and extending in a horizontal direction;
forming a first contact hole connecting to the first impurity region connection layer and the second gate connection conductor layer, and, in plan view, having a portion overlapping at least the second gate connection conductor layer, the portion having a bottom portion positioned, in the perpendicular direction, lower than upper surfaces of the second gate conductor layer and the second gate connection conductor layer; and
forming a first connection conductor layer within the first contact hole so as to connect to the first impurity region connection layer and the second gate connection conductor layer.
2. The pillar-shaped semiconductor device according to
3. The pillar-shaped semiconductor device according to
4. The pillar-shaped semiconductor device according to
a second contact hole on the first impurity region connection layer or on the second gate connection conductor layer, and
a third contact hole that connects to the second gate connection conductor layer when the second contact hole is on the first impurity region connection layer, or that connects to the first impurity region connection layer when the second contact hole is on the second gate connection conductor layer,
the third contact hole has a bottom portion positioned lower than the upper surfaces of the second gate conductor layer and the second gate connection conductor layer, and
the first connection conductor layer includes the second connection conductor layer within the second contact hole and the third connection conductor layer connecting to the second connection conductor layer and being present within the third contact hole.
5. The pillar-shaped semiconductor device according to
a first gate connection conductor layer connecting to the first gate conductor layer and extending in a horizontal direction;
a first interlayer insulating layer surrounding side surfaces of the first gate connection conductor layer and the second gate connection conductor layer; and
a second interlayer insulating layer surrounding a side surface of the first interlayer insulating layer, being formed of a material different from a material of the first interlayer insulating layer, and being used for formation of the first contact hole.
6. The pillar-shaped semiconductor device according to
a third interlayer insulating layer between a side surface of the first gate connection conductor layer, a side surface of the second gate connection conductor layer, and a side surface of the first connection conductor layer, the third interlayer insulating layer having a dielectric constant smaller than a dielectric constant of a silicon oxide film.
7. The pillar-shaped semiconductor device according to
a fourth interlayer insulating layer having a pore between one or both of a side surface of the first gate connection conductor layer and a side surface of the second gate connection conductor layer, and a side surface of the first connection conductor layer.
8. The pillar-shaped semiconductor device according to
a fourth contact hole connecting to a bottom of the third contact hole and connecting to a material layer being positioned lower than the third contact hole and being a semiconductor or conductive layer; and
a fourth connection conductor layer within the fourth contact hole.
9. The pillar-shaped semiconductor device according to
11. The method for producing a pillar-shaped semiconductor device according to
12. The method for producing a pillar-shaped semiconductor device according to
13. The method for producing a pillar-shaped semiconductor device according to
forming a second contact hole on the first impurity region connection layer;
forming a second connection conductor layer within the second contact hole;
forming a third contact hole on and connecting to the second contact hole and the second gate connection conductor layer; and
forming a third connection conductor layer within the third contact hole,
the second contact hole and the third contact hole together forming the first contact hole,
the second connection conductor layer and the third connection conductor layer together forming the first connection conductor layer.
14. The method for producing a pillar-shaped semiconductor device according to
forming a fourth contact hole on the second gate connection conductor layer;
forming a fourth connection conductor layer within the fourth contact hole;
forming a fifth contact hole on and connecting to the fourth contact hole and the first impurity region connection layer; and
forming a fifth connection conductor layer within the fifth contact hole,
the fourth contact hole and the fifth contact hole together forming the first contact hole, and
the fourth connection conductor layer and the fifth connection conductor layer together forming the first connection conductor layer.
15. The method for producing a pillar-shaped semiconductor device according to
forming a first gate connection conductor layer connecting to the first gate conductor layer, and extending in a horizontal direction;
forming a first interlayer insulating layer surrounding side surfaces of the first gate connection conductor layer and the second gate connection conductor layer; and
forming a second interlayer insulating layer surrounding a side surface of the first interlayer insulating layer, formed of a material different from a material of the first interlayer insulating layer, and providing a higher etching rate than the first interlayer insulating layer with an etching species for forming the first contact hole.
16. The method for producing a pillar-shaped semiconductor device according to
17. The method for producing a pillar-shaped semiconductor device according to
18. The method for producing a pillar-shaped semiconductor device according to
forming a sixth contact hole connecting to a bottom of the third contact hole, and connecting to a material layer being positioned lower than the third contact hole and being a semiconductor or conductive layer; and
forming a sixth connection conductor layer within the third contact hole and the sixth contact hole.
19. The method for producing a pillar-shaped semiconductor device according to
forming a seventh contact hole connecting to a bottom of the fourth contact hole, and connecting to a material layer being positioned lower than the fourth contact hole and being a semiconductor or conductive layer; and
forming a seventh connection conductor layer within the fourth contact hole and the seventh contact hole.
20. The method for producing a pillar-shaped semiconductor device according to
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The present application is a continuation application of PCT/JP2017/039538, filed Nov. 1, 2017, the entire contents of which are incorporated herein by reference.
The present invention relates to a pillar-shaped semiconductor device and a method for producing the pillar-shaped semiconductor device.
In these years, SGTs (Surrounding Gate Transistors), which represent pillar-shaped semiconductor devices, have been attracting attention as semiconductor elements that provide highly integrated semiconductor devices. There has been a demand for an SGT-including semiconductor memory device that has a higher degree of integration and a higher performance.
Ordinary planar MOS transistors have a channel that is present in a horizontal direction along the upper surface of the semiconductor substrate. By contrast, SGTs have a channel that is present in a direction perpendicular to the upper surface of the semiconductor substrate (for example, refer to Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)). For this reason, compared with planar MOS transistors, SGTs enable an increase in the density of semiconductor devices.
A large number of SGTs illustrated in
There has been a demand for achievement of a higher density, a higher performance, and a reduction in the cost of SGT-including LSI circuits.
A pillar-shaped semiconductor device according to a first aspect of the present invention includes: a first semiconductor pillar disposed on, in a direction perpendicular to, a substrate; a first impurity region present below the first semiconductor pillar; a first impurity region connection layer connecting to the first impurity region, extending in a horizontal direction, and being formed of a semiconductor or a conductor; a second impurity region present above the first semiconductor pillar; a first gate insulating layer surrounding the first semiconductor pillar between the first impurity region and the second impurity region; a first gate conductor layer surrounding the first insulating layer; a second semiconductor pillar disposed on, in the direction perpendicular to, the substrate; a third impurity region present below the second semiconductor pillar; a fourth impurity region present above the second semiconductor pillar; a second gate insulating layer surrounding the second semiconductor pillar between the third impurity region and the fourth impurity region; a second gate conductor layer surrounding the gate insulating layer; a second gate connection conductor layer connecting to the second gate conductor layer, extending in a horizontal direction, and being formed of a conductor; a first contact hole connecting to the first impurity region connection layer and the second gate connection conductor layer, and having a portion overlapping, in plan view, at least the second gate connection conductor layer, the portion having a bottom portion positioned, in the perpendicular direction, lower than upper surfaces of the second gate conductor layer and the second gate connection conductor layer; and a first connection conductor layer being present within the first contact hole and connecting to the first impurity region and the second gate connection conductor layer.
In the above-described pillar-shaped semiconductor device, desirably, an upper surface of the first connection conductor layer is positioned, in the perpendicular direction, lower than the upper surfaces of the second gate conductor layer and the second gate connection conductor layer.
In the above-described pillar-shaped semiconductor device, desirably, the second gate conductor layer and the second gate connection conductor layer are layers formed of an identical material.
In the above-described pillar-shaped semiconductor device, desirably, in plan view, the first contact hole includes a second contact hole present on the first impurity region connection layer or on the second gate connection conductor layer, and a third contact hole that connects to the second gate connection conductor layer when the second contact hole is on the first impurity region connection layer, or that connects to the first impurity region connection layer when the second contact hole is on the second gate connection conductor layer, the third contact hole has a bottom portion positioned lower than the upper surfaces of the second gate conductor layer and the second gate connection conductor layer, and the first connection conductor layer includes the second connection conductor layer within the second contact hole and the third connection conductor layer connecting to the second connection conductor layer and being present within the third contact hole.
The above-described pillar-shaped semiconductor device desirably includes: a first gate connection conductor layer connecting to the first gate conductor layer and extending in a horizontal direction; a first interlayer insulating layer surrounding side surfaces of the first gate connection conductor layer and the second gate connection conductor layer; and a second interlayer insulating layer surrounding a side surface of the first interlayer insulating layer, being formed of a material different from a material of the first interlayer insulating layer, and being used for formation of the first contact hole.
The above-described pillar-shaped semiconductor device desirably includes: a third interlayer insulating layer between a side surface of the first gate connection conductor layer, a side surface of the second gate connection conductor layer, and a side surface of the first connection conductor layer, the third interlayer insulating layer having a dielectric constant smaller than a dielectric constant of a silicon oxide film.
The above-described pillar-shaped semiconductor device desirably includes: a fourth interlayer insulating layer having a pore between one or both of a side surface of the first gate connection conductor layer and a side surface of the second gate connection conductor layer, and a side surface of the first connection conductor layer.
The above-described pillar-shaped semiconductor device desirably includes: a fourth contact hole connecting to a bottom of the third contact hole and connecting to a material layer being positioned lower than the third contact hole and being a semiconductor or conductive layer; and a fourth connection conductor layer within the fourth contact hole.
In the above-described pillar-shaped semiconductor device, the first contact hole desirably has a bottom portion within the first impurity region.
A method for producing a pillar-shaped semiconductor device according to a second aspect of the present invention, the pillar-shaped semiconductor device including a first impurity region, a first semiconductor pillar, and a second impurity region that are disposed, in a hierarchical manner, in a direction perpendicular to, on a substrate; a third impurity region, a second semiconductor pillar, and a fourth impurity region that are disposed, in a hierarchical manner, in the direction perpendicular to, on the substrate, the first impurity region being disposed below the first semiconductor pillar, the third impurity region being disposed below the second semiconductor pillar; and a first impurity region connection layer formed of a semiconductor or a conductor, connecting to the first impurity region, and extending in a horizontal direction, the method including: a step of forming a first gate insulating layer so as to surround the first semiconductor pillar; a step of forming a second gate insulating layer so as to surround the second semiconductor pillar; a step of forming a first gate conductor layer so as to surround the first gate insulating layer; a step of forming a second gate conductor layer so as to surround the second gate insulating layer; a step of forming a second gate connection conductor layer connecting to the second gate conductor layer and extending in a horizontal direction; a step of forming a first contact hole connecting to the first impurity region connection layer and the second gate connection conductor layer, and, in plan view, having a portion overlapping at least the second gate conductor layer, the portion having a bottom portion positioned, in the perpendicular direction, lower than upper surfaces of the second gate conductor layer and the second gate connection conductor layer; and a step of forming a first connection conductor layer within the first contact hole so as to connect to the first impurity region and the second gate connection conductor layer.
In the above-described method, desirably, the first connection conductor layer is formed so as to have an upper surface positioned, in the perpendicular direction, lower than upper surfaces of the second gate conductor layer and the second gate connection conductor layer.
In the above-described method, desirably, the second gate conductor layer and the second gate connection conductor layer are formed as layers of an identical material.
The above-described method desirably includes: a step of forming a second contact hole on the first impurity region connection layer; a step of forming a second connection conductor layer within the second contact hole; a step of forming a third contact hole on and connecting to the second contact hole and the second gate connection conductor layer; and a step of forming a third connection conductor layer within the third contact hole, the second contact hole and the third contact hole together forming the first contact hole, the second connection conductor layer and the third connection conductor layer together forming the first connection conductor layer.
The above-described method desirably includes: a step of forming a fourth contact hole on the second gate connection conductor layer; a step of forming a fourth connection conductor layer within the fourth contact hole; a step of forming a fifth contact hole on and connecting to the fourth contact hole and the first impurity connection layer; and a step of forming a fifth connection conductor layer within the fifth contact hole, the fourth contact hole and the fifth contact hole together forming the first contact hole, and the fourth connection conductor layer and the fifth connection conductor layer together forming the first connection conductor layer.
The above-described method desirably includes: a step of forming a first interlayer insulating layer surrounding side surfaces of the first gate connection conductor layer and the second gate connection conductor layer; and a step of forming a second interlayer insulating layer surrounding a side surface of the first interlayer insulating layer, formed of a material different from a material of the first interlayer insulating layer, and providing a higher etching rate than the first interlayer insulating layer with an etching species for forming the first contact hole.
The above-described method desirably includes: a step of forming a third interlayer insulating layer surrounding a side surface of the first connection conductor layer, and having a smaller relative dielectric constant than a silicon oxide film.
The above-described method desirably includes: a step of forming a fourth interlayer insulating layer surrounding the first connection conductor layer and having a pore therein.
The above-described method desirably includes: a step of forming a sixth contact hole connecting to a bottom of the third contact hole, and connecting to a material layer being positioned lower than the third contact hole and being a semiconductor or conductive layer; and a sixth connection conductor layer within the third contact hole and the sixth contact hole.
The above-described method desirably includes: a step of forming a seventh contact hole connecting to a bottom of the fourth contact hole, and connecting to a material layer being positioned lower than the fourth contact hole and being a semiconductor or conductive layer; and a step of forming a seventh connection conductor layer within the fourth contact hole and the seventh contact hole.
In the above-described method, the first contact hole desirably has a bottom portion within the first impurity region connection layer.
According to the present invention, in an SGT-including pillar-shaped semiconductor memory device, a single memory cell is constituted by at least three semiconductor pillars and a small number of contact holes that connect wiring layers within the memory cell. As a result, a high-density SRAM cell circuit can be achieved.
Hereinafter, methods for producing SGT-including pillar-shaped semiconductor memory devices according to embodiments of the present invention will be described with reference to drawings.
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a first embodiment of the present invention, will be described with reference to
As illustrated in
Hereinafter, a production flow will be described for an SRAM cell structure according to the first embodiment relating to the equivalent circuit of an SRAM cell illustrated in
As illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
This embodiment provides the following advantages.
1. In this embodiment, the N+ layer 12a, the P+ layer 13a, and the W layer 22c, which connects to the gate TiN layer 17b, are connected together through the W layer 29a. The W layer 29a is, within the W layer 22c, embedded in the contact hole 27aa. Similarly, the W layer 29b is, within the W layer 22b, embedded in the contact hole 27bb. As a result, compared with the case of not embedding such a layer, the W layer 22c and the W layer 29a can be connected to each other with certainty. In addition, an increase in the connection area is achieved between the W layer 22c and the W layer 29a, so that, compared with the case of not embedding the layer, a decrease in the connection resistance between the W layer 22c and the W layer 29a is achieved. The same applies to the W layer 22b and the W layer 29b.
2. In this embodiment, the W layers 29a and 29b have upper surfaces positioned lower than the upper surfaces of the gate TiN layers 23a, 23b, 23c, and 23d and the upper surfaces of the W layers 22a, 22b, 22c, and 22d, which connect to the gate TiN layers 23a, 23b, 23c, and 23d. Thus, the W layers 29a and 29b are formed so as to have upper surfaces positioned lower than, with certainty, the upper surfaces of the gate TiN layers 23a, 23b, 23c, and 23d and the W layers 22a, 22b, 22c, and 22d, to thereby prevent, with certainty, electrical short circuit faults between the W layers 29a and 29b, the word wiring metal layer WL, and the ground wiring metal layers VSS1 and VSS2, which are formed on the SiO2 layer 35. In addition, a decrease in the coupling capacitance can be achieved between the W layers 29a and 29b and, for example, the gate TiN layers 23a to 23d and the W layers 22a to 22d. This enables a decrease in the driving voltage to thereby achieve a decrease in the power consumption.
3. In this embodiment, the contact hole 27aa is formed so as to have a bottom portion that is positioned lower than the upper surface of the W layer 22c, that is positioned, in plan view, on the boundary between the N+ layer 12a and the P+ layer 13a, and that is positioned at the upper surfaces of the N− layer 12a and the P+ layer 13a, or within the N+ layer 12a and the N− layer 13a. Thus, the contact hole 27aa is formed so as to have a bottom portion positioned within the P+ layer 12a and the P− layer 13a. This enables an increase in the contact area between the W layer 29a and the N+ layer 12a and P+ layer 13a. This enables a decrease in the connection resistance between the W layer 29a and the N+ layer 12a and P+ layer 13a. This effect of decreasing the connection resistance becomes stronger with a decrease in the area of the contact hole 27aa in plan view. Thus, the effect is advantageous for increasing the degree of integration of SGT circuits.
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a second embodiment of the present invention, will be described with reference to
As illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
This embodiment provides the following advantages.
In the first embodiment, the connections between the N+ layer 12a and the P+ layer 13a and the W layer 22c, and the connections between the N+ layer 12d and the P+ layer 13b and the W layer 22b are established through the contact holes 27aa and 27bb, which are formed by a lithographic process and an RIE process carried out one time (refer to
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a third embodiment of the present invention, will be described with reference to
As illustrated in
As illustrated in
This embodiment provides the following advantages.
In the second embodiment, as has been described with reference to
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a fourth embodiment of the present invention, will be described with reference to
As illustrated in
Subsequently, as illustrated in
This embodiment provides the following advantages.
In this embodiment, the SiO2 layers 53a and 53b, which are insulating material layers, are present between the W layers 55a and 55b and the W layers 22a to 22d. This prevents electrical short circuit faults between the W layers 55a and 55b and the W layers 22a to 22d, the faults being caused by mask misalignment in the lithographic process during formation of the contact holes 40a and 40b.
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a fifth embodiment of the present invention, will be described with reference to
As illustrated in
As illustrated in
This embodiment provides the following advantages.
In this embodiment, the SiN layer 56 and the SiO2 layer 25 are present between the contact holes 27aa and 27bb and the W layers 22a to 22d. The formation of the contact holes 27aa and 27bb is achieved by etching the SiO2 layer 25 by an RIE process. In this case, the SiN layer 56 functions as an etching stopper against etching of the SiO2 layer 25. This prevents electrical short circuit faults between the W layers 22a to 22d and the W layers 29a and 29b, the faults being caused by mask misalignment in the lithographic process during formation of the contact holes 27aa and 27bb.
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a sixth embodiment of the present invention, will be described with reference to
As illustrated in
Subsequently, a SiO2 layer 61 is formed so as to surround the outer periphery of the Si pillars. Subsequently, as in
This embodiment provides the following advantages.
In this embodiment, the SiO2 layer 25 (relative dielectric constant: 3.9 to 4.3) in the first embodiment is replaced by the SiOC layer 60 (relative dielectric constant: 2.7 to 2.9), which has a low relative dielectric constant. As a result, the resultant SRAM circuit enables, compared with the first embodiment, a decrease in the coupling capacitance between the W layers 22a to 22d, which are gate conductor layers disposed on both sides of the low dielectric constant SiOC layer 60, and the W layers 29a and 29b, which are connection wiring conductor layers. This enables a decrease in the driving voltage to thereby achieve a decrease in the power consumption.
Hereinafter, a method for producing an SRAM cell that is an SGT-including pillar-shaped semiconductor memory device, according to a seventh embodiment of the present invention, will be described with reference to
The steps described with
Subsequently, a CVD process is carried out to form a SiO2 layer 64. In this formation of the SiO2 layer 64, pores 65a, 65b, 65c, and 65d are formed in the narrow regions between the W layers 22a to 22d and the W layers 29a and 29b.
The same steps as in
This embodiment provides the following advantages.
In this embodiment, the pores 65a, 65b, and 65c, which have a relative dielectric constant of 1, are present between the W layers 22a to 22d, which are gate conductor layers, and the W layers 29a and 29b, which are connection wiring conductor layers. This enables a decrease in the coupling capacitance between the W layers 22a to 22d, which are gate conductor layers, and the W layers 29a and 29b, which are connection wiring conductor layers, compared with the first embodiment in which the SiO2 layer 25, which has a relative dielectric constant of 3.9 to 4.3, is present over the whole structure. This enables a decrease in the driving voltage to thereby achieve a decrease in the power consumption.
Hereinafter, a method for producing an SGT-including CMOS inverter chain circuit, according to an eighth embodiment of the present invention, will be described with reference to
As illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
This embodiment provides the following advantages.
In this embodiment, in the structure in which two SGTs are formed in upper and lower portions of each of the Si pillars 76a, 76b, and 76c, the NiSi layer 88a, and the W layer 82b and the W layer 83b, which are gate conductor layers, which are three layers separated in the perpendicular direction, are connected together through the W layers 96a and 92b, which are connection conductor layers. Referring to the second embodiment, the N+ layer 12a and the P+ layer 13a correspond to the NiSi layer 88a; the W layer 22c serving as a gate corresponds to the W layer 83b serving as a gate; the W layer 42a serving as a connection conductor layer corresponds to the W layer 92a serving as a connection conductor layer; and the W layer 49a serving as a connection conductor layer corresponds to the W layer 96a serving as a connection conductor layer. Note that, in the first embodiment, the W layer 42a serving as a connection conductor layer has a bottom portion present not beyond but within the W layer 22c serving as a gate; by contrast, in this embodiment, the W layer 92a serving as a connection conductor layer, the W layer 82b serving as a gate, and the W layer 83b serving as a gate are formed so as to continuously extend in the perpendicular direction. This enables formation of high-density connections between layers overlapping in plan view. As a result, an increase in the density of an SGT-including circuit can be achieved.
Incidentally, the first embodiment is described as to the case of forming an SRAM circuit on the P-layer substrate 1a. Alternatively, another substrate such as an SOI (Silicon On Insulator) may be used. The same applies to other embodiments.
The first embodiment is described as to the case of forming an SRAM cell circuit; however, application to other SGT-including circuits is also possible. In the first embodiment, the N− layer 12a, which is in the bottom portion of a Si pillar 11a, is connected through the W layer 29a to the gate W layer 22c of another Si pillar 11d. In addition, the N− layer 12a, which is in the bottom portion of a Si pillar 11a, is connected through the W layer 29a to the gate W layer 22c of another Si pillar 11e. Similarly, the P− layer 13a, which is in the bottom portion of a Si pillar 11b, is connected through the W layer 29a to the gate W layer 22c of other Si pillars 11d and 11e. In this way, the present invention is applied to a connection between an impurity layer in the bottom portion of a Si pillar having an SGT and a gate conductor layer of another Si pillar having an SGT. Accordingly, the present invention is also applicable to circuits in which the source or drain of a MOS field-effect transistor is connected to the gate of another MOS field-effect transistor, such as various flip-flop circuits, latch circuits, and DRAM (Random Access Memory) sense circuits. This enables an increase in the degree of integration of such circuits. The same applies to other embodiments.
The first embodiment is described as to the case of forming a single SGT in each of the Si pillars 11a to 11f. However, the present invention is also applicable to cases where two or more SGTs are formed in each of the Si pillars 11a to 11f. The same applies to other embodiments.
In the first embodiment, the gate TiN layers 23a to 23d and the W layers 22a to 22d connected thereto are formed. Alternatively, the gate TiN layers 23a to 23d and the W layers 22a to 22d may be layers of other materials. Alternatively, the gate TiN layers 23a to 23d and the W layers 22a to 22d may be layers of the same material. As with the barrier metal layers, the gate TiN layers 23a to 23d and the W layers 22a to 22d may each be a conductor layer constituted by a plurality of layers. The same applies to other embodiments.
In the first embodiment, the N− layers 12a to 12d and the P− layers 13a and 13b, which are in the bottom portions of the Si pillars 11a to 11f, are formed so as to be connected to the bottom portions of the Si pillars 11a to 11f and to extend in the horizontal direction. In the N+ layers 12a to 12d and the P+ layers 13a and 13b, the regions extending in the horizontal direction function as impurity region connection layers for forming the connection W layers 29a and 29b on these regions. The impurity region connection layers extending in the horizontal direction may be layers formed of other semiconductor or conductor materials. The same applies to other embodiments.
In the first embodiment, the W layers 22a to 22d connect to the TiN layers 23a to 23d, which serve as gate conductor layers, and extend in the horizontal direction. The W layers 22a to 22d function as gate connection conductor layers for forming the connection W layers 29a and 29b on the W layers 22a to 22d. These gate connection conductor layers extending in the horizontal direction may be conductor material layers of the same material as that of the gate conductor layers or conductor material layers of a material different from that of the gate conductor layers. The same applies to other embodiments.
In the first embodiment, the contact holes 27aa and 27bb are formed on the N− layers 12a and 22d and the P+ layers 13a and 13b. By contrast, the contact holes 27aa and 27bb may be formed on a silicide layer or a metal layer formed on the N− layers 12a and 22d and the P+ layers 13a and 13b. An N+ layer or a P+ layer may be formed in lower portions of the Si pillars 11a to 11f; and, on a low-resistance semiconductor layer or conductor layer connecting to the side surface of the N− layer or P− layer, the contact holes 27aa and 27bb may be formed. Incidentally, this low-resistance semiconductor layer connecting to the side surface of the N+ layer or P+ layer may be constituted by a single continuous semiconductor layer, or may be constituted by different semiconductor layers. The same applies to other embodiments.
In the first embodiment, the HfO2 layer 16a is used as a gate insulating film. Alternatively, a layer of another material may be used. The gate insulating material layer may be constituted by a plurality of material layers. The same applies to other embodiments.
In the first embodiment, the Si pillars 11a to 11f, the N+ layers 12a to 12d, 33a, 33c, 33d, and 33f, and the P− layers 13a, 13b, 33b, and 33e, which are formed of Si, are used. Alternatively, other semiconductor materials may be used. The same applies to other embodiments.
In the first embodiment, the source and drain of each SGT are of the same conductivity. Alternatively, a tunnel SGT in which the source and the drain are of different conductivities may be used. The same applies to other embodiments.
In the first embodiment, lithographic processes are used to pattern the material layers. In such a lithographic process, in addition to a resist layer, a single material layer or a plurality of material layers formed under the resist layer may be patterned to form a mask material layer for a material layer to be etched. The same applies to other embodiments.
In the second embodiment, the contact hole 43a on the N+ layer 12a and the P+ layer 13a, and the contact hole 43b on the N− layer 12d and the P+ layer 13b are first formed. Subsequently, in plan view, the contact hole 46a, which extends from the contact hole 43a to the W layer 22c, and the contact hole 46b, which extends from the contact hole 43b to the W layer 22b, are formed. The order of forming the contact holes 43a and 43b and the contact holes 46a and 46b may be changed.
In the second embodiment, the barrier conductor layers 48a and 48b are formed on the W layers 42a and 22b. For the connection between the W layers 42a and 22b and the W layers 49a and 49b, the barrier conductor layers 48a and 48b may be omitted. These barrier conductor layers may be omitted when the W layers 42a and 22b and the W layers 49a and 49b are replaced by other conductor material layers and barrier conductor layers are not necessary for operating the circuit. The same applies to other embodiments in which at least two conductor layers are connected together such as connections between the W layers 42a and 22b and the W layers 49a and 49b.
In the third embodiment and the fourth embodiment, a selective growth process is employed to form the W layers 51a, 51b, 55a, and 55b. Instead of the W layers 51a, 51b, 55a, and 55b, other conductor materials may be formed by a selective growth process.
In the fourth embodiment, the SiO2 layers 53a and 53b are formed on the side surfaces of the contact holes 40a and 40b. Alternatively, instead of the SiO2 layers 53a and 53b, other insulating material layers may be used.
The fifth embodiment, which is described with the steps in the first embodiment, is similarly applicable to other embodiments.
In the fifth embodiment, instead of the SiN layer 56, a layer of another insulating material may be used as long as the material provides an etching stopper against etching for forming the contact holes 27aa and 27bb.
In the sixth embodiment, the SiOC layer 60, which is formed of a low dielectric constant material, may be replaced by a layer of another material such as porous silica or SiOF.
In the seventh embodiment, the SiO2 layer 64 may be replaced by another insulating layer.
In the seventh embodiment, the pores 65a and 65b are formed in the SiO2 layer 64, which is between the W layers 22a and 22b, which are disposed on both sides of the W layer 29a. The regions where the pores 65a to 65d are formed may be changed depending on the design of the SRAM cell or other circuits.
The eighth embodiment, which is described as to the case of forming a CMOS inverter chain circuit, is also applicable to other SGT-including circuits.
In the eighth embodiment, the W layer 92b serving as a connection conductor layer is used to establish the connection between the gate W layer 82b and the gate W layer 83b. Alternatively, depending on the circuit formed, a connection between, within the same Si pillar 76b, the W layer 83b and one or both of the impurity region P+ layer 73b and N+ layer 72b, or a connection to the impurity region N+ layer 70a may be employed.
In the eighth embodiment, the W layer 96a connects the NiSi layer 88a, which connects to the P+ layer 73a and the N− layer 72a, to the W layer 83b, which connects to the gate TiN layer 81b. By contrast, depending on the circuit formed, the W layer 96a may connect to a connection conductor layer connecting to the P+ layer 73a or the N+ layer 72a. In the Si pillar 76a, the W layer 96a may connect to one or both of the W layer 82a and the N+ layer 70a, which are positioned lower than the P+ layer 73a and the N+ layer 72a. The same applies to, in addition to the Si pillar 76a, the Si pillar 76c. Depending on the circuit formed, the same applies to connections between the Si pillar 76b and a plurality of other Si pillars.
The eighth embodiment is described as to the case where the present invention is applied to a circuit in which two SGTs are formed per Si pillar. Alternatively, the present invention is also applicable to the cases where one or three or more SGTs are formed per Si pillar. A circuit in which a single SGT is formed per Si pillar includes a gate conductor layer, and a conductor layer that connects to the gate conductor layer through a contact hole extending through a source or drain impurity region that is present under the gate conductor layer. When three or more SGTs are formed per Si pillar, a contact through-hole is formed that corresponds to the contact hole 93b and connects together three or more conductor layers or impurity regions.
In the eighth embodiment, holes are formed so as to have, in the perpendicular direction, lower ends positioned at the lower ends of the N− layers 72a, 72b, and 72c, have upper ends positioned at the upper ends of the P+ layers 73a, 73b, and 73c, and extend through in the horizontal direction the W layer, the TiN layer, the HfO2 layers 79a, 79b, and 79c to reach the side surfaces of the N+ layers 72a, 72b, and 72c and the P+ layers 73a, 73b and 73c. As a result, the HfO2 layer, the TiN layer, and the W layer are divided into upper and lower portions, to form the HfO2 layers 78, 79a, 79b, and 79c, the TiN layers 80a, 80b, 80c, 81a, 81b, and 81c, and the W layers 82a, 82b, 82c, 83a, 83b, and 83c. By contrast, the HfO2 layer 78, the TiN layers 80a, 80b, and 80c, and the W layers 82a, 82b, and 82c may be first formed; subsequently, the NiSi layers 88a, 88b, and 88c, over and under which the SiO2 layers 85a, 85b, 85c, 86a, 86b, and 86c are formed, may be formed; subsequently, the HfO2 layers 79a, 79b, and 79c, the TiN layers 81a, 81b, and 81c, and the W layers 83a, 83b, and 83c may be formed. Alternatively, another process and other material layers may be employed to form the gate insulating layer and the gate conductor layer of each SGT, a conductor connection layer connecting to the N+ layers 72a, 72b, and 72c and the P− layers 73a, 73b, and 73c, and insulating layers over and under the conductor connection layer.
In the first embodiment, as described above, the contact hole 27aa is formed so as to have a bottom portion positioned within the N+ layer 12a and the P+ layer 13a, to thereby increase the contact area between the W layer 29a and the N+ layer 12a and P+ layer 13a. This enables a decrease in the connection resistance between the W layer 29a and the N+ layer 12a and P+ layer 13a. The same applies to other embodiments.
The present invention encompasses various embodiments and modifications without departing from the broad spirit and scope of the present invention. The above-described embodiments are mere examples of the present invention and do not limit the scope of the present invention. The above-described embodiments and modifications can be appropriately combined. The above-described embodiments from which some elements are omitted as necessary still fall within the technical idea of the present invention.
A pillar-shaped semiconductor memory device and a method for producing a pillar-shaped semiconductor memory device according to the present invention provide at low cost a semiconductor device that has a high degree of integration and a high performance.
Kim, Min Soo, Nakamura, Hiroki, Harada, Nozomu, Masuoka, Fujio, Tao, Zheng
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