A power converter device includes a first phase-shift full-bridge circuit, a second phase-shift full-bridge circuit, a detector circuit, and a control circuit. The control circuit controls the first phase-shift full bridge circuit and the second phase-shift full bridge circuit. The control circuit disables the second phase-shift full-bridge circuit when the output current is less than a first predetermined value. The control circuit enables the second phase-shift full-bridge circuit when the output current is equal to or greater than the first predetermined value. The control circuit controls a synchronous switching circuit of the second phase-shift full-bridge circuit to operate in a traditional control mode when the output current is equal to or greater than a second predetermined value and a duty cycle of a phase-shift switching circuit is equal to or greater than a third predetermined value. The second predetermined value is greater than the first predetermined value.
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1. A power converter device comprising:
a first phase-shift full-bridge circuit comprising a first phase-shift switching circuit and a first synchronous switching circuit;
a second phase-shift full-bridge circuit coupled in parallel with the first phase-shift full-bridge circuit, wherein the second phase-shift full-bridge circuit comprises a second phase-shift switching circuit and a second synchronous switching circuit, wherein the second phase-shift full-bridge circuit and the first phase-shift full-bridge circuit are configured to receive an input voltage and output an output voltage;
a detector circuit configured to detect an output current; and
a control circuit configured to control the first phase-shift full-bridge circuit and the second phase-shift full-bridge circuit according to the output current, the input voltage, and the output voltage;
wherein the control circuit disables the second phase-shift full-bridge circuit when the output current is less than a first predetermined value;
wherein the control circuit enables the second phase-shift full-bridge circuit when the output current is equal to or greater than the first predetermined value, such that the second phase-shift full-bridge circuit and the first phase-shift full-bridge circuit operate in a same control mode;
wherein the control circuit controls the second synchronous switching circuit to operate in a traditional mode when the output current is equal to or greater than a second predetermined value and a duty cycle of the second phase-shift switching circuit is equal to or greater than a third predetermined value, wherein the second predetermined value is greater than the first predetermined value, wherein the third predetermined value is associated with the input voltage and the output voltage.
2. The power converter device of
3. The power converter device of
4. The power converter device of
5. The power converter device of
a first front stage switching circuit comprising a first switch and a second switch, wherein the first switch and the second switch are coupled in series; and
a first rear stage switching circuit comprising a third switch and a fourth switch, wherein the third switch and the fourth switch are coupled in series;
wherein the first front stage switching circuit and the first rear stage switching circuit are coupled in parallel between a first input terminal and a second input terminal;
wherein the control circuit controls the first phase-shift switching circuit by controlling the first switch, the second switch, the third switch, and the fourth switch.
6. The power converter device of
a second front stage switching circuit comprising a fifth switch and a sixth switch, wherein the fifth switch and the sixth switch are coupled in series; and
a second rear stage switching circuit comprising a seventh switch and an eighth switch, wherein the seventh switch and the eighth switch are coupled in series;
wherein the second front stage switching circuit and the second rear stage switching circuit are coupled in parallel between the first input terminal and the second input terminal;
wherein the control circuit controls the second phase-shift switching circuit by controlling the fifth switch, the sixth switch, the seventh switch, and the eighth switch.
7. The power converter device of
a ninth switch;
a tenth switch coupled with the ninth switch at a first node, wherein the detector circuit is coupled between the first node and a first output terminal;
a first inductor coupled between the ninth switch and a second output terminal; and
a second inductor coupled between the tenth switch and the second output terminal.
8. The power converter device of
in a first time duration, controlling the first switch, the fourth switch, and the tenth switch to be turned on, and controlling the second switch, the third switch, and the ninth switch to be turned off;
in a second time duration, controlling the first switch and the third switch to be turned on, and controlling the second switch, the fourth switch, the ninth switch, and the tenth switch to be turned off;
in a third time duration, controlling the second switch, the third switch, and the ninth switch to be turned on, and controlling the first switch, the fourth switch, and the tenth switch to be turned off; and
in a fourth time duration, controlling the second switch and the fourth switch to be turned on, and controlling the first switch, the third switch, the ninth switch, and the tenth switch to be turned off.
9. The power converter device of
an eleventh switch;
a twelfth switch coupled with the eleventh switch at a second node, wherein the detector circuit is coupled between the second node and the first output terminal;
a third inductor coupled between the eleventh switch and the second output terminal; and
a fourth inductor coupled between the twelfth switch and the second output terminal.
10. The power converter device of
a first detector unit coupled between the first node and the first output terminal, wherein the first detector unit is configured to detect a first sub output current of the first phase-shift full-bridge circuit; and
a second detector unit coupled between the second node and the first output terminal, wherein the second detector unit is configured to detect a second sub output current of the second phase-shift full-bridge circuit, wherein a sum of the first sub output current and the second sub output current is the output current.
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This application claims priority to Taiwanese Application Serial Number 108135749, filed Oct. 2, 2019, which is herein incorporated by reference.
The present disclosure relates to a circuit technology. More particularly, the present disclosure relates to a power converter device.
With development in the circuit technology, power converter devices have been applied to various apparatus. The power converter devices in current approaches are affected by negative factors. The negative factors are, for example, switching loss of switches, core loss, conductance loss, and negative currents. How to increase efficiency of the power converter devices is an important issue in this field.
One embodiment of the present disclosure is related to a power converter device. The power converter device includes a first phase-shift full-bridge circuit, a second phase-shift full-bridge circuit, a detector circuit, and a control circuit. The first phase-shift full-bridge circuit includes a first phase-shift switching circuit and a first synchronous switching circuit. The second phase-shift full-bridge circuit and the first phase-shift full-bridge circuit are coupled in parallel. The first phase-shift full-bridge circuit includes a second phase-shift switching circuit and a second synchronous switching circuit. The second phase-shift full-bridge circuit and the first phase-shift full-bridge circuit are configured to receive an input voltage and output an output voltage. The detector circuit is configured to detect an output current. The control circuit is configured to control the first phase-shift full-bridge circuit and the second phase-shift full-bridge circuit according to the output current, the input voltage, and the output voltage. The control circuit disables the second phase-shift full-bridge circuit when the output current is less than a first predetermined value. The control circuit enables the second phase-shift full-bridge circuit when the output current is equal to or greater than the first predetermined value, such that the second phase-shift full-bridge circuit and the first phase-shift full-bridge circuit operate in a same control mode. The control circuit controls the second synchronous switching circuit to operate in a traditional mode when the output current is equal to or greater than a second predetermined value and a duty cycle of the second phase-shift switching circuit is equal to or greater than a third second phase-shift switching circuit. The second predetermined value is greater than the first predetermined value. The third predetermined value is associated with the input voltage and the output voltage.
As the above embodiments, operating efficiency of the power converter device of the present disclosure is better by multi-phases and multi-segments control.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
Reference is now made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. The embodiments below are described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the disclosure covered by the description. The structure and operation are not intended to limit the execution order. Any structure regrouped by elements, which has an equal effect, is covered by the scope of the present disclosure.
In the present disclosure, “connected” or “coupled” may be referred to “electrically connected” or “electrically coupled.” “Connected” or “coupled” may also be referred to operations or actions between two or more elements.
Reference is made to
As illustrated in
The first phase-shift full-bridge circuit 110 includes a first phase-shift switching circuit 112 and a first synchronous switching circuit 114. The first phase-shift switching circuit 112 and the first synchronous switching circuit 114 are coupled magnetically via a first transformer circuit TA. The first phase-shift switching circuit 112 includes a first front stage switching circuit 1121 and a first rear stage switching circuit 1122. The first front stage switching circuit 1121 and the first rear stage switching circuit 1122 are coupled in parallel between a first input terminal IN1 and a second input terminal IN2. The first input terminal IN1 is, for example, a positive voltage terminal, and the second input terminal IN2 is, for example, a ground terminal PGND (0 volt). The first front stage switching circuit 1121 includes a first switch QA1 and a second switch QA2. The first switch QA1 and the second switch QA2 are coupled in series. The first rear stage switching circuit 1122 includes a third switch QA3 and a fourth switch QA4. The third switch QA3 and the fourth switch QA4 are coupled in series. The control circuit 140 controls the first phase-shift switching circuit 112 by controlling the first switch QA1, the second switch QA2, the third switch QA3, and the fourth switch QA4.
The second phase-shift full-bridge circuit 120 includes a second phase-shift switching circuit 122, a second synchronous switching circuit 124, and a second transformer circuit TB. the second phase-shift switching circuit 122 includes a second front stage switching circuit 1221 and a second rear stage switching circuit 1222. The second front stage switching circuit 1221 includes a fifth switch QB1 and a sixth switch QB2. The second rear stage switching circuit 1222 includes a seventh switch QB3 and an eighth switch QB4. A circuit structure of the second phase-shift full-bridge circuit 120 is the same to that of the first phase-shift full-bridge circuit 110, so it is not described herein again.
The first synchronous switching circuit 114 includes a ninth switch QA5, a tenth switch QA6, a first inductor LOA1, a second inductor LOA2, a first node K1, and a first capacitor COA. The ninth switch QA5 and the tenth switch QA6 are coupled at the first node K1. The first inductor LOA1 is coupled between the ninth switch QA5 and a second output terminal OUT2. A first output terminal OUT1 is, for example, the ground terminal GND (0 volt), and the second output terminal OUT2 is, for example, a positive voltage terminal (12 volts). The second inductor LOA2 is coupled between the tenth switch QA6 and the second output terminal OUT2. The first capacitor COA is coupled between the first node K1 and the second output terminal OUT2.
The second synchronous switching circuit 124 includes an eleventh switch QB5, a twelfth switch QB6, a third inductor LOB1, a fourth inductor LOB2, a second node K2, and a second capacitor COB. A circuit structure of the second synchronous switching circuit 124 is the same to that of the first synchronous switching circuit 114, so it is not described herein again.
The detector circuit 130 includes a first detector unit R1 and a second detector unit R2. The first detector unit R1 is coupled between the first node K1 and the first output terminal OUT1. The first detector unit R1 is configured to detect the first sub output current IA of the first phase-shift full-bridge circuit 110. The second detector unit R2 is coupled between the second node K2 and the first output terminal OUT1. The second detector unit R2 is configured to detect the second sub output current IB of the second phase-shift full-bridge circuit 120.
The control circuit 140 includes an analog-to-digital converter 142, a micro controller 144, and a driver 146. In operation, the analog-to-digital converter 142 receives the first sub output current IA, the second sub output current IB, the input voltage VIN, and the output voltage VOUT, and converts the analog signals above to be digital signals. The micro controller 144 receives the digital signals and controls the driver 146 to output control signals A1-A6 and B1-B6 according to the digital signals, to control the first phase-shift full-bridge circuit 110 and the second phase-shift full-bridge circuit 120.
In specific, the power converter device 100 sets five predetermined values according to the output current IO, and the control circuit 140 changes control modes according to the five predetermined values. An order of the five predetermined values from least to greatest is a predetermined value A, a predetermined value B, a predetermined value C, a predetermined value D, and a predetermined value E. The control signals A1-A4 are configured to control the first switch QA1 to the fourth switch QA4 respectively. The control signals B1-B4 are configured to control the fifth switch QBE to the eighth switch QB4 respectively. The control signals A5-A6 are configured to control the ninth switch QA5 and the tenth switch QA6 respectively. The control signals B5-B6 are configured to control the eleventh switch QB5 and the twelfth switch QB6 respectively. The control circuit 140 controls the switches above according to the output current IO, to change the control modes.
In some embodiments, the driver 146 is implemented by a pulse width modulation (PWM) driver. In these embodiments, the control signals A1-A6 and B1-B6 are pulse width modulation control signals.
Reference is made to
In an operation S202, the control circuit 140 determines whether the output current IO is less than the predetermined value A or not. If yes, an operation S204 is entered. If no, an operation S206 is entered.
In the operation S204, the control circuit 140 disables the second phase-shift full-bridge circuit 120, conducts the first synchronous switching circuit 114, and controls the first phase-shift switching circuit 112 to operate in a hiccup control mode. Reference is made to
In addition, voltage levels of the control signals A1-A6 and the control signals B1-B6 may be designed according to types of the aforementioned switches.
As mentioned above, the second phase-shift full-bridge circuit 120 is disabled under a condition that the output current is less than the predetermined value C, switching loss of the switches and core loss of magnetic elements of the second transformer circuit TB can be reduced, to maintain the power converter device 100 to operate at a best power point. In addition, the control circuit 140 does not switch the ninth switch QA5 and the tenth switch QA6 under a condition that the output current is less than the predetermined value B, such that the switching loss of the switches can be reduced, to increase operating efficiency.
In the operation S206, the control circuit 140 disables the second phase-shift full-bridge circuit 120, conducts the first synchronous switching circuit 114, and controls the first phase-shift switching circuit 112 to operate in a normal control mode. Main differences between the normal control mode and the aforementioned hiccup control mode are that, in the normal control mode, the switches operate as descriptions above in each of the working periods.
In an operation S208, the control circuit 140 determines whether the output current IO is less than the predetermined value B or not. If yes, an operation S210 is entered. If no, an operation S212 is entered. The control methods of the operation S210 are the same to those of the operation S206, so they are not described herein again.
In the operation S212, the control circuit 140 disables the second phase-shift full-bridge circuit 120, controls the first synchronous switching circuit 114 to operate in an intermediate control mode, and controls the first phase-shift switching circuit 112 to operate in the normal control mode. Reference is made to
In an operation S214, the control circuit 140 determines whether the output current IO is less than the predetermined value C or not. If yes, an operation S216 is entered. If no, an operation S218 is entered. The control methods of the operation S216 are the same to those of the operation S212, so they are not described herein again.
In an operation S218, the control circuit 140 enables the second phase-shift full-bridge circuit 120, and controls the second phase-shift full-bridge circuit 120 and the first phase-shift full-bridge circuit 110 have a same control mode. Circuit loss becomes greater when the load becomes greater, so the second phase-shift full-bridge circuit 120 is enabled to cooperate with the first phase-shift full-bridge circuit 110 to charge the load, to maintain the power converter device 100 to operate at a best power point. Reference is made to
In an operation S220, the control circuit 140 determines whether the output current IO is less than the predetermined value D or not. If yes, an operation S222 is entered. If no, an operation S224 is entered. The control methods of the operation S222 are the same to those of the operation S218, so they are not described herein again.
As mentioned above, under a condition that the load is light, the first synchronous switching circuit 114 or the second synchronous switching circuit 124 is controlled in the intermediate control mode. In other words, the switches on the secondary side are turned on (the ninth switch QA5/the eleventh switch QB5 are turned on or the tenth switch QA6/the twelfth switch QB6 are turned on) when the primary side charges the secondary side (the first time duration T1 and the third time duration T3). Accordingly, an overall current of the circuit and conductance loss can be reduced to increase operating efficiency.
In the operation S224, the control circuit 140 determines whether a duty cycle of the second phase-shift switching circuit 122 is less than the predetermined value P3 or not. If yes, an operation S226 is entered. If no, an operation S228 is entered. The control methods of the operation S226 are the same to those of the operation S218, so they are not described herein again. In some embodiments, the predetermined value P3 is related to the input voltage VIN and the output voltage VOUT. For example, the predetermined value can be derived by a formula (1):
P3=(N1/N2)×(VOUT/VIN) (1)
P3 is a predetermined value, N1 is the number of turns of the primary side, N2 is the number of turns of the secondary side, VOUT is the output voltage, and VIN is the input voltage.
In general, for operating smoothly, duty cycles of the control signals of the second phase-shift switching circuit 122 are from smaller to larger when the second phase-shift full-bridge circuit 120 is enabled. A charging time of the second phase-shift switching circuit 122 (primary side) charging the second synchronous switching circuit 124 (secondary side) is shorter when the duty cycles of the control signals of the second phase-shift switching circuit 122 are smaller. At this time, the second phase-shift switching circuit 122 could not provide enough energy to the second synchronous switching circuit 124. If the eleventh switch QB5 or the twelfth switch QB6 is turned on at this time, negative currents of the output inductor (third inductor) LOB1 and the output inductor (fourth inductor) LOB2 (demagnetizations of the inductors are larger than excitation) are formed. At this time, the first phase-shift full-bridge circuit 110 not only provides energy to the load, but also provides energy to the second phase-shift full-bridge circuit 120 via a loop of the load, such that a loading suffered by the first phase-shift full-bridge circuit 110 is heavier and the first phase-shift full-bridge circuit 110 thus is damaged. Thus, it is needed to determine whether the duty cycle of the second phase-shift switching circuit 122 is less than the predetermined value P3 or not before entering the operation S228, to determine whether the second synchronous switching circuit 124 enters a traditional control mode described below or not.
The operation S228 is entered if the duty cycle of the second phase-shift switching circuit 122 is greater than the predetermined value P3. In the operation S228, the control circuit 140 controls the first phase-shift switching circuit 112 and the second phase-shift switching circuit 122 to operate in the normal control mode, and controls the first synchronous switching circuit 114 and the second synchronous switching circuit 124 to operate in the traditional control mode. Reference is made to
As mentioned above, in the second time duration T2 and the fourth time duration T4 (current circulation state), the ninth switch QA5, the tenth switch QA6, the eleventh switch QB5, and the twelfth switch QB6 are turned on. Thus, the current does not flow through body diodes of the switches. Accordingly, operating efficiency can be increased.
As mentioned above, the eleventh switch QB5 and the twelfth switch QB6 are turned on when the duty cycle of the second phase-shift switching circuit 122 is equal to or greater than the predetermined value P3. Thus, a current circulation formed by the second phase-shift full-bridge circuit 120 (negative current) and the first phase-shift full-bridge circuit 110 (positive current) could be prevented to ensure the circuit to operate normally.
In an operation S230, the control circuit 140 determines whether the output current IO is less than the predetermined value E or not. If yes, an operation S232 is entered. If no, an operation S234 is entered.
In the operation S232, the control circuit 140 controls the first phase-shift full-bridge circuit 110 and the second phase-shift full-bridge circuit 120 to operate in a high-frequency control mode. The current variation of the inductors on the secondary side can be reduced when switching frequencies of the switches are higher, such that core loss of iron cores of the inductors is reduced, to increase operating efficiency.
In the operation S234, the control circuit 140 controls the first phase-shift full-bridge circuit 110 and the second phase-shift full-bridge circuit 120 to operate in a low-frequency control mode. The switching loss of the switches can be prevented from being too high when the switching frequencies of the switches are lower. Accordingly, operating efficiency of the circuit can be increased and heat on the switches (transistors) can be reduced.
In an operation S236, the system (for example: a digital signal processor) performs controls and operations according to the setting above.
Time lengths of the first time duration T1, the second time duration T2, the third time duration T3, and the fourth time duration T4 in
As the above embodiments, the power converter device of the present disclosure selects an appropriate corresponding control mode of the control modes according to different output currents. The control modes not only include the traditional PWM control, but also integrate controls of the synchronous switches and the parallel full-bridge phase-shift circuit into the control modes. Thus, the power converter device of the present disclosure operates at a best power point, to achieve a better efficiency improvement over the traditional control mode. In addition, when the second phase-shift full-bridge circuit cooperates with the first phase-shift full-bridge circuit, a special control mode is provided to prevent an unstable condition that the output voltage oscillates.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
Chiu, Jung-Ching, Liu, Chien-Lung, Kuo, You-Chen
| Patent | Priority | Assignee | Title |
| 11750105, | Apr 29 2022 | Asian Power Devices Inc. | Full-bridge phase-shift converter with voltage clamping |
| Patent | Priority | Assignee | Title |
| 8295068, | Feb 02 2010 | National Taipei University of Technology | Shift full bridge power converting system and control method thereof |
| 9621056, | Oct 04 2013 | Chicony Power Technology Co., Ltd. | Method of controlling phase-shift full-bridge converter in light load operation |
| 20040208028, | |||
| 20110273909, | |||
| 20130033904, | |||
| 20160149498, | |||
| 20170244331, | |||
| 20180301995, | |||
| CN103036405, | |||
| CN106374762, | |||
| CN108054922, | |||
| CN108781039, | |||
| TW201306657, | |||
| TW347063, | |||
| TW495245, | |||
| TW568161, | |||
| TW580822, | |||
| TW601367, | |||
| WO2018123767, | |||
| WO2019159663, |
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