A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.
|
17. A method of performing a write operation on a resistive random-access memory (RRAM) device, the method comprising:
generating a first current using a current source in a first current path;
conducting the first current in the first current path to generate a voltage difference;
including the voltage difference in a bias voltage output from a node in the first current path;
generating a drive voltage from the bias voltage; and
applying the drive voltage to the RRAM device.
1. A memory circuit comprising:
a bias voltage generator comprising a first current path, the first current path comprising a node and a current source configured to output a first current at the node, wherein the bias voltage generator is configured to output a bias voltage from the node based on a voltage difference generated from conduction of the first current in the first current path;
a drive circuit configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage; and
a resistive random-access memory (RRAM) device configured to conduct a second current responsive to the drive voltage.
10. A memory circuit comprising:
an activation voltage generator configured to generate an activation voltage based on a resistance value of a resistive device;
a first transistor configured to conduct a first current from a current source responsive to the activation voltage, thereby generating a voltage difference; and
an array of resistive random-access memory (RRAM) devices, each RRAM device comprising a selection transistor,
wherein the selection transistor of each RRAM device comprises a gate configured to receive the activation voltage and is thereby configured to generate a selection transistor voltage difference responsive to the activation voltage, the selection transistor voltage difference having a value corresponding to a value of the voltage difference.
2. The memory circuit of
3. The memory circuit of
the RRAM device is included in the second current path,
the first current path comprises a path segment having a resistance value based on a portion of the second current path between the drive circuit and the RRAM device, and
the voltage difference is based on the resistance value.
4. The memory circuit of
the RRAM device is included in the second current path,
the first current path comprises a path segment having a resistance value based on a portion of the second current path between the RRAM device and a reference node, and
the voltage difference is based on the resistance value.
5. The memory circuit of
the RRAM device comprises a resistive layer configured to conduct the second current,
the first current path comprises a resistive device having a resistance value based on the resistive layer, and
the voltage difference is based on the resistance value.
6. The memory circuit of
the resistive layer is capable of having a high resistance state (HRS) and a low resistance state (LRS), and
the resistance value is based on the LRS.
7. The memory circuit of
the RRAM device comprises a selection transistor configured to conduct the second current,
the first current path comprises a transistor configured to generate the voltage difference by conducting the first current, and
the memory circuit is configured to generate a selection transistor voltage difference having a value corresponding to a value of the voltage difference.
8. The memory circuit of
the selection transistor is configured to conduct the second current responsive to an activation voltage, and
the transistor in the first current path is configured to conduct the first current responsive to the activation voltage.
9. The memory circuit of
11. The memory circuit of
12. The memory circuit of
13. The memory circuit of
14. The memory circuit of
15. The memory circuit of
16. The memory circuit of
receive a target value of the voltage difference from the activation voltage generator, and
output the activation voltage to the first transistor and the selection transistor of each RRAM device.
18. The method of
19. The method of
20. The method of
generating the activation voltage based on a resistance value of a resistive device; and
applying the activation voltage to the RRAM device.
|
|||||||||||||||||||||||||
The present application claims the priority of U.S. Provisional Application No. 62/679,679, filed Jun. 1, 2018, which is incorporated herein by reference in its entirety.
In some applications, integrated circuits (ICs) include memory circuits that store data in arrays of resistive random-access memory (RRAM) cells. An individual RRAM cell is programmable to a high resistance state (HRS) or a low resistance state (LRS), each state representing a logical state stored by the RRAM cell.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In various embodiments, a circuit is configured to generate a bias voltage and/or an activation voltage for RRAM programming and/or read operations by including a current source and a current path, also referred to as a dummy column, having IC elements corresponding to IC elements in columns of an RRAM array. The bias voltage is based on one or more voltage differences generated in the current path by the current from the current source and is used to generate voltage drops across RRAM devices in the programming and/or read operations. The activation voltage is based on a target transistor voltage and is used to control RRAM device selection transistors. By including the current path, the circuit is capable of generating the bias and/or activation voltages having values that vary according to temperature and process-dependent variations in the dummy column IC elements. Because the dummy column IC element variations track those of the corresponding elements in the RRAM columns, the circuit generates the bias and/or activation voltages adapted to temperature and process-dependent variations in RRAM column current path resistance, thereby improving data retention compared to approaches in which bias and activation voltages are generated independent of RRAM column current path resistance.
In some embodiments, memory circuit 100 is a subset of a memory macro (not shown) that includes one or more additional components, e.g., at least one control or logic circuit or one or more arrays of RRAM devices in addition to the array of RRAM devices 150 depicted in
RRAM device 150 is a memory storage device capable of having either a HRS or a LRS indicative of a logical state. RRAM device 150 includes an input terminal 151 coupled to signal line WL (one of signal lines WL_1-WL_N), a terminal 152 coupled to conduction line L1 (one of conduction lines L1_1-L1_M), and a terminal 153 coupled to conduction line L2 (the corresponding one of conduction lines L2_1-L2_M). RRAM device 150 includes a resistive layer capable of having either insulating properties corresponding to the HRS or conductive properties corresponding to the LRS based on the respective absence or presence of one or more filaments, also referred to as conduction paths. In operation, filaments are formed, thereby setting RRAM devices to the LRS, based on one or more of various mechanisms, e.g., vacancy or defect migration or another suitable mechanism, and broken, thereby resetting RRAM devices to the HRS, based on heating or one or more other suitable mechanisms. In some embodiments, RRAM device 150 is RRAM device 500 discussed below with respect to
RRAM device 150 includes a selection transistor (not shown in
RRAM device 150 is thereby programmable and readable based on a memory cell voltage V12 equal to a difference between a voltage V1 at terminal 152 and a voltage V2 at terminal 153 (not labeled in
Memory circuit 100, or a memory macro including memory circuit 100, is configured so that memory cell voltage V12 has first programming voltage level corresponding to setting RRAM device 150 to the LRS in a first write operation, a second programming voltage level corresponding to resetting RRAM device 150 to the HRS in a second write operation, and a read voltage level corresponding to detecting the LRS or HRS of RRAM device 150 in a read operation.
In various embodiments, each of the first and second write operations and the read operation has a same polarity, or one of the first and second write operations and the read operation has a polarity different from that of the other two of the first and second write operations and the read operation. In each of the first and second write operations and the read operation, memory cell voltage V12 applied to RRAM device 150 causes a current Id to flow between terminals 152 and 153 in a direction determined by the polarity of the memory cell voltage.
As depicted in
Drive circuit 120 includes an amplifier OP2 and a transistor P1 coupled between a power supply node VDDN2 and an output terminal 121. A current path 120P is coupled between drive circuit 120 and power reference node VSSN. Current path 120P includes path segments 130 and 140, conduction lines L1 and L2 (L1_1-L1_M and L2_1-L2_M) coupled between path segments 130 and 140, and RRAM device 150 (plurality of RRAM devices 150) coupled between conduction lines L1 and L2 (corresponding conduction lines L1_1-L1_M and L2_1-L2_M).
Two or more circuit elements are considered to be coupled based on a direct electrical connection or an electrical connection that includes one or more additional circuit elements and is thereby capable of being controlled, e.g., made resistive or open by a transistor or other switching device.
Bias voltage generator 110 is an electronic circuit configured to output a bias voltage VBLR to an output terminal 111 and/or an activation voltage VWL to signal path WL (signal paths WL_1-WL_N). Bias voltage VBLR and activation voltage VWL have voltage levels based on one or more current levels of a current Ic generated by current source 114, resistance values of current path 110P, and an output of activation voltage generator 112, as discussed below.
Drive circuit 120 is an electronic circuit configured to receive bias voltage VBLR from bias voltage generator 110, generate a drive voltage VBL having a voltage level equal to that of bias voltage VBLR, and output drive voltage VBL to an output terminal 121, as further discussed below.
Current path 120P is a portion of memory circuit 100 configured to receive drive voltage VBL from drive circuit 120 and activation voltage VWL from signal path WL (signal paths WL_1-WL_N) and, responsive to drive voltage VBL and activation voltage VWL, enable current Id to flow between drive circuit 120 and power supply reference node VSSN as part of performing a write or read operation on a given RRAM device 150. In some embodiments, memory circuit 100 is configured to enable current Id to flow by coupling either one of conduction lines L1 or L2 (L1_1-L1_M or L2_1-L2_M) to output terminal 121 and coupling the other one of conduction lines L1 or L2 (L1_1-L1_M or L2_1-L2_M) to power supply reference node VSSN.
Power supply nodes VDDN1 and VDDN2 are voltage nodes configured to carry respective power supply voltages VDD1 and VDD2. In various embodiments, power supply voltage VDD1 has a power supply voltage level less than, equal to, or greater than a power supply voltage level of power supply voltage VDD2. In some embodiments, power supply nodes VDDN1 and VDDN2 are a same voltage node, and power supply voltages VDD1 and VDD2 are a same power supply voltage. In the embodiment depicted in
Power supply reference node VSSN is a voltage node configured to carry a power supply reference voltage VSS, e.g., a ground voltage. In the embodiment depicted in
Current source 114 is an electronic circuit configured to receive power supply voltage VDD1 from power supply node VDDN1, and generate current Ic having one or more predetermined current levels. In some embodiments, at least one predetermined current level is based on a compliance level of an RRAM device, e.g., RRAM device 150, in a write operation, the compliance level being a maximum current level designed to avoid an undesirable condition, e.g., an overheating and/or damaging stress level, or performance of an unreliable programming operation. In various embodiments, current source 114 is configured to generate current Ic having a predetermined current level equal to a compliance level or to another level derived from the compliance level, e.g., a multiple or fraction of the compliance level.
In some embodiments, current source 114 is configured to generate current Ic having the one or more predetermined current levels ranging from 50 microamperes (μA) to 500 μA. In some embodiments, current source 114 is configured to generate current Ic having the one or more predetermined current levels ranging from 200 μA to 300 μA.
Path segment 116 is one or more IC elements (not depicted in
In the embodiment depicted in
In various embodiments, path segment 116 is configured to have the path resistance value equal to that of the corresponding portion of current path 120P or to another value derived from the resistance value of the corresponding portion of current path 120P, e.g., a multiple or fraction of the resistance value of the corresponding portion of current path 120P. In various embodiments, path segment 116 is path segment 300 discussed below with respect to
Path segment 116 is coupled to current source 114 at a node VBLRN and to transistor N1 at a node DN and is thereby configured to, in operation, generate a voltage difference VD116 between voltage VBLR on node VBLRN and a voltage VD on node DN.
In the embodiment depicted in
In addition to being based on current Ic and the output of amplifier OP1, a value of voltage difference VDS is based on dimensions of transistor N1. In some embodiments, transistor N1 has dimensions that match those of the selection transistor of RRAM device 150, e.g., transistor N14 of RRAM device 500 discussed below with respect to
Resistive device RP1 is one or more conductive segments configured to provide a path resistance. The one or more conductive segments have dimensions configured to provide the path resistance having a predetermined resistance value. In various embodiments, the one or more conductive segments include a polycrystalline silicon material (poly) a compound material including silicon, a semiconductor material or compound, or other material suitable for having the predetermined resistance value. In some embodiments, the predetermined resistance value is based on a resistance value of an RRAM device, e.g., RRAM device 150.
In various embodiments, the predetermined resistance value corresponds to the resistance value of the RRAM device in the HRS or the LRS, a resistance value above the resistance value of the RRAM device in the HRS, a resistance value below the resistance value of the RRAM device in the LRS, or a resistance value between the resistance values of the RRAM device in the HRS and the LRS.
In various embodiments, resistive device RP1 is configured to have the predetermined resistance value equal to the RRAM device resistance value or to another value derived from the RRAM device resistance value, e.g., a multiple or fraction of the RRAM device resistance value.
In some embodiments, resistive device RP1 is configured to have the predetermined resistance value ranging from 1 kilo-ohm (kΩ) to 50 kΩ. In some embodiments, resistive device RP1 is configured to have the predetermined resistance value ranging from 2 kΩ to 5 kΩ.
Resistive device RP1 is coupled to path segment 118 at a node RP1N and is thereby configured to, in operation, generate a voltage difference VDRP1 between voltage VS on node SN and a voltage VRP1 on node RP1N.
Path segment 118 is one or more IC elements (not depicted in
In the embodiment depicted in
In some embodiments, the portion of current path 120P corresponding to path segment 116 includes path segment 130 and the portion of one of conduction lines L1 or L2 (L1_1-L1_M or L2_1-L2_M) between path segment 130 and a given RRAM device 150, and the portion of current path 120P corresponding to path segment 118 includes the portion of the other of conduction lines L1 or L2 (L1_1-L1_M or L2_1-L2_M) between path segment 140 and the given RRAM device 150.
In various embodiments, path segment 118 is configured to have the path resistance value equal to that of the corresponding portion of current path 120P or to another value derived from the resistance value of the corresponding portion of current path 120P, e.g., a multiple or fraction of the resistance value of the corresponding portion of current path 120P. In various embodiments, path segment 118 is path segment 300 discussed below with respect to
Path segment 118 is coupled to power supply reference node VSSN and is thereby configured to, in operation, generate a voltage difference VD118 between voltage VRP1 on node RP1N and power supply reference voltage VSS on power supply reference node VSSN.
Amplifier OP1 is an operational amplifier including, in addition to the output terminal coupled to the gate of transistor N1, a non-inverting input terminal coupled to an output terminal 112B of activation voltage generator 112, and an inverting input terminal coupled to an output terminal 112C of activation voltage generator 112.
Activation voltage generator 112 is an electronic circuit including, in addition to output terminals 112B and 112C, an input terminal 112A coupled to node DN, and an input terminal 112D coupled to node SN. In various embodiments, either input terminal 112A is coupled to output terminal 112B, or input terminal 112D is coupled to output terminal 112C. In some embodiments, activation voltage generator 112 does not include one of input terminals 112A or 112D.
Activation voltage generator 112 includes a resistive device (not depicted in
In some embodiments, the resistive material has a TCR corresponding to poly and therefore smaller than a TCR corresponding to a metal. In such embodiments, the target value of voltage difference VDS increases with temperature to a substantially lesser degree than in embodiments in which the resistive material has a TCR corresponding to a metal. In various embodiments, the resistive material includes poly, a compound material including silicon, a semiconductor material or compound, or other material suitable for having the TCR properties.
In embodiments in which input terminal 112D is coupled to output terminal 112C, activation voltage generator 112 is thereby configured to, in operation, output voltage VS received at input terminal 112D as a voltage VC on output terminal 112C, and thereby to the inverting input of amplifier OP1. In such embodiments, activation voltage generator 112 is configured to output a voltage VB based on the current flow through the resistive device to output terminal 112B, and thereby to the non-inverting input of amplifier OP1. In various embodiments, activation voltage generator 112 is configured to generate voltage VB based on voltage VD received at input terminal 112A or based on an internal reference voltage independent of voltage VD. In various embodiments, activation voltage generator 112 is activation voltage generator 200A discussed below with respect to
In embodiments in which input terminal 112A is coupled to output terminal 112B, activation voltage generator 112 is thereby configured to, in operation, output voltage VD received at input terminal 112A as voltage VB on output terminal 112B, and thereby to the non-inverting input of amplifier OP1. In such embodiments, activation voltage generator 112 is configured to output voltage VC based on the current flow through the resistive device to output terminal 112C, and thereby to the inverting input of amplifier OP1. In various embodiments, activation voltage generator 112 is configured to generate voltage VC based on voltage VS received at input terminal 112D or based on an internal reference voltage independent of voltage VS. In some embodiments, activation voltage generator 112 is activation voltage generator 200C discussed below with respect to
In operation, amplifier OP1 generates an output voltage based on a difference between voltages VC and VB received at the respective inverting and non-inverting inputs, and the output voltage drives the gate of transistor N1. Amplifier OP1 thereby controls a conductance level of transistor N1, causing voltage VD to differ from voltage VS by the target value of voltage difference VDS equal to the difference between voltages VC and VB output by activation voltage generator 112. Activation voltage generator 112, amplifier OP1, and transistor N1 are thereby configured in a closed loop capable of controlling voltage VDS for a given current level of current Ic.
In some embodiments, activation voltage generator 112 is configured to generate the target value of voltage difference VDS ranging from 200 millivolts (mV) to 600 mV. In some embodiments, activation voltage generator 112 is configured to generate the target value of voltage difference VDS ranging from 200 mV to 500 mV.
In some embodiments, bias voltage generator 110 is configured to output the output voltage of amplifier OP1 to signal path WL as activation voltage VWL as depicted in
By being configured to generate and output activation voltage VWL based on the current level of current Ic, and based on the target value of voltage difference VDS output by activation voltage generator 112, bias voltage generator 110 and memory circuit 100 are capable of controlling the drain-source voltage of the selection transistor of an RRAM device, e.g., RRAM device 150, to have a range of values smaller than that of a memory circuit that does not include bias voltage generator 110.
In an RRAM device, e.g., RRAM device 150, the drain-source voltage of the selection transistor acts to reduce a received voltage, e.g., memory cell voltage V12, used to bias the resistive layer in operation. Thus, the relatively smaller range of drain-source voltage values enables improved control of bias levels of resistive layers in RRAM devices in write and read operations, thereby improving data retention compared to approaches in which RRAM selection transistors do not receive activation voltage VWL generated by bias voltage generator 110.
By the arrangement depicted in
In various embodiments, bias voltage generator 110 does not include one or more of path segment 116, transistor N1, resistive device RP1, or path segment 118, and is thereby configured to generate bias voltage VBLR as the sum of voltage differences that do not include the corresponding one or more of voltage differences VD116, VDS, VDRP1, or VD118.
In various embodiments, bias voltage generator 110 includes one or more IC elements (not shown) other than or in addition to path segment 116, transistor N1, resistive device RP1, or path segment 118, and is thereby configured to generate bias voltage VBLR as the sum including one or more voltage differences corresponding to the one or more IC elements.
By the configuration discussed above, bias voltage generator 110 includes current path 110P configured to receive current Ic from current source 114, and generate bias voltage VBLR based on the one or more voltage differences generated from conduction of current Ic in current path 110P.
In some embodiments, bias voltage generator 110 is configured to generate bias voltage VBLR having voltage levels ranging from 0.5 volts (V) to 3.0 V. In some embodiments, bias voltage generator 110 is configured to generate bias voltage VBLR having voltage levels ranging from 1.5 V to 2.5 V.
In the embodiment depicted in
Amplifier OP2 of drive circuit 120 is an operational amplifier including an inverting input terminal configured to receive bias voltage VBLR, a non-inverting input terminal coupled to a node VBLN, and an output terminal coupled to a gate of transistor P1. Transistor P1 is a PMOS transistor having a source terminal coupled to power supply node VDDN2 and a drain terminal coupled to node VBLN, in addition to the gate coupled to the output of amplifier OP2.
Amplifier OP2 and transistor P1 are thereby configured as a closed loop that, in operation, causes amplifier OP2 to modulate the gate of transistor P1, and thereby generate drive voltage VBL on node VBLN having a voltage level equal to that of bias voltage VBLR.
As depicted in
As depicted in the simplified diagram of
Conduction lines L1 and L2 depicted in
Path segment 130 is one or more IC elements, e.g., a transistor and/or metal line, capable of selectively establishing a current path from output terminal 121 to any one of conduction lines L1 or L2 (L1_1-L1_M or L2_1-L2_M). In the embodiment depicted in
Transistor P4 is coupled between transistor P2 and conduction line L1_1, transistor P6 is coupled between transistor P2 and conduction line L1_2, transistor P8 is coupled between transistor P2 and conduction line L1_M, and transistor P2 is coupled to output terminal 121. Transistor P5 is coupled between transistor P3 and conduction line L2_1, transistor P7 is coupled between transistor P3 and conduction line L2_2, transistor P9 is coupled between transistor P3 and conduction line L2_M, and transistor P3 is coupled to output terminal 121.
Transistors P2-P9 include gates and are thereby configured to receive respective signals S1-S8. Signals S1-S8 have logical levels configured to control transistors P2-P9 so as to establish the portion of current path 120P as a single current path from output terminal 121 to a predetermined one of conduction lines L1_1-L1_M or L2_1-L2_M.
Path segment 140 is one or more IC elements, e.g., a transistor and/or metal line, capable of selectively establishing a current path from any one of conduction lines L1 or L2 (L1_1-L1_M or L2_1-L2_M) to power reference node VSSN. In the embodiment depicted in
Transistor N2 is coupled between transistor N8 and conduction line L1_1, transistor N4 is coupled between transistor N8 and conduction line L1_2, transistor N6 is coupled between transistor N8 and conduction line L1_M, and transistor N8 is coupled to power reference node VSSN. Transistor N3 is coupled between transistor N9 and conduction line L2_1, transistor N5 is coupled between transistor N9 and conduction line L2_2, transistor N7 is coupled between transistor N9 and conduction line L2_M, and transistor N9 is coupled to power reference node VSSN.
Transistors N2-N9 include gates and are thereby configured to receive respective signals S9-S16. Signals S9-S16 have logical levels configured to control transistors N2-N9 so as to establish the portion of current path 120P as a single current path from a predetermined one of conduction lines L1_1-L1_M or L2_1-L2_M to power reference node VSSN.
RRAM devices 150 are arranged in N rows, and each RRAM device 150 of a given row is coupled to a corresponding one of signal lines WL_1-WL_N. Each RRAM device 150 of a given row is thereby configured to be coupled to a corresponding one of conduction line pairs L1_1/L2_1 through L1_M/L2_M responsive to activation voltage VWL on the corresponding one of signal lines WL_1-WL_N.
Path segments 130 and 140 and plurality of RRAM devices 150 are thereby configured to establish current path 120P including one of RRAM devices 150 responsive to activation voltage VWL and signals S1-S16.
In the embodiment depicted in
As illustrated in
In the non-limiting example of a write or read biasing operation depicted in
In the non-limiting example of a write or read biasing operation depicted in
In the embodiment depicted in
By the configuration discussed above, memory circuit 100 is capable of generating bias voltage VBLR and/or activation voltage VWL based on voltage differences generated from current Ic flowing in current path 110P. The voltage differences are generated based on current path components having properties related to those of the corresponding components of current path 120P such that temperature and process-dependent variations in the resistance values of current path 120P are reflected as temperature and process-dependent variations in the resistance values of current path 110P. Because bias voltage VBLR and/or activation voltage VWL have values that vary in accordance with the resistance variations of current path 110P, bias voltage VBLR and/or activation voltage VWL have values that are adapted to temperature and process-dependent variations in resistance values of current path 120P including a given RRAM device 150. In write and read operations, data retention is thereby improved compared to approaches in which bias and activation voltages are generated independent of RRAM current path resistance values.
Activation voltage generator 200A includes input terminal 112D coupled to output terminal 112C, and resistive devices R1 and R2 coupled in series between input terminal 112A and power reference node VSSN. Resistive devices R1 and R2 are coupled to each other and to output terminal 112B at a node NA.
Resistive devices R1 and R2 are thereby arranged as a voltage divider configured to receive voltage VD on input terminal 112A and generate a voltage difference VTA between node NA and input terminal 112A based on resistance values of resistive devices R1 and R2 and a resultant current Ir.
Each of resistive devices R1 and R2 is one or more conductive segments configured to provide a path resistance. The one or more conductive segments have dimensions configured to provide path resistances having predetermined resistance values. In various embodiments, the one or more conductive segments include a poly, a compound material including silicon, a semiconductor material or compound, and/or a metal, e.g., copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), and/or another metal and/or another material suitable for having the predetermined resistance values. In some embodiments, the predetermined resistance values are based on resistance values of selection transistors of RRAM devices, e.g., RRAM device 150 discussed above with respect to
By including resistive devices R1 and R2 having the predetermined resistance values, activation voltage generator 200A is configured to generate voltage difference VTA between voltage VB output to output terminal 112B and voltage VD received at input terminal 112A having a value usable as the target value of voltage difference VDS discussed above with respect to activation voltage generator 112 and
Activation voltage generator 200B includes input terminal 112D coupled to output terminal 112C, and a resistive device RP2 coupled in series with a transistor N10 between input terminal 112A and power reference node VSSN. Resistive device RP2 is coupled to transistor N10 and to output terminal 112B at a node NB.
Resistive device RP2 is thereby configured to receive voltage VD on input terminal 112A and generate a voltage difference VTB between node NB and input terminal 112A based on a resistance value of resistive device RP2 and current Ir as controlled by transistor N10.
Resistive device RP2 is one or more conductive segments configured to provide a path resistance. The one or more conductive segments have dimensions configured to provide path resistances having predetermined resistance values. In various embodiments, the one or more conductive segments include a poly, a compound material including silicon, a semiconductor material or compound, and/or a metal, e.g., copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), and/or another material suitable for having the predetermined resistance values. In some embodiments, the predetermined resistance values are based on resistance values of selection transistors of RRAM devices, e.g., RRAM device 150 discussed above with respect to
Transistor N10 is configured to control current Ir based on a gate voltage Vg. In the embodiment depicted in
Gate bias circuit 210B includes an amplifier OP3 configured to receive a voltage Vr at a non-inverting input terminal, a PMOS transistor P10 and resistive devices R3 and R4 coupled in series between power supply node VDDN1 and power reference node VSSN, and a PMOS transistor P11 and an NMOS transistor N11 coupled in series between power supply node VDDN1 and power reference node VSSN. An output terminal of amplifier OP3 is coupled to gates of transistors P10 and P11, and an inverting input terminal of amplifier OP3 is coupled to a terminal of each of resistive devices R3 and R4. Transistor N11 is configured as a diode having a gate coupled to drain terminals of each of transistors P11 and N11, and configured to output gate voltage Vg.
Amplifier OP3 is thereby configured to drive the gate of transistor P10 so that, in operation, a voltage (not labeled) developed across resistive device R4 is equal to voltage Vr based on a current Im. Because amplifier OP3 also drives the gate of transistor P11, current Im is mirrored through transistors P11 and P10, and thereby determines a voltage level of gate voltage Vg based on a voltage level of voltage Vr. Bias circuit 210B is thereby configured to output gate voltage Vg capable of controlling current Ir through transistor N10 and responsive to voltage Vr.
By including resistive device RP2 having the predetermined resistance value and transistor N10 configured to control current Ir through resistive device RP2, activation voltage generator 200B is configured to generate voltage difference VTB between voltage VB output to output terminal 112B and voltage VD received at input terminal 112A having a value usable as the target value of voltage difference VDS discussed above with respect to activation voltage generator 112 and
Activation voltage generator 200C includes input terminal 112A coupled to output terminal 112B, and current source 114, path segments 116 and 118, and resistive devices RP1 and RP2 coupled in series between power supply node VDDN1 and power reference node VSSN. Each of current source 114, path segments 116 and 118, and resistive device RP1 is discussed above with respect to memory circuit 100 and
Path segment 116, resistive device RP2, and output terminal 112C are coupled together at a node NC, and activation voltage generator 200C is thereby configured to generate voltage VC with respect to power supply reference voltage VSS.
By including resistive device RP2 having the predetermined resistance value and current source 114, path segments 116 and 118, and resistive device RP1 configured to control current Ic through resistive device RP2, activation voltage generator 200C is configured to generate voltage VC and output voltage VC to output terminal 112C having a value usable as a target value of voltage VS of the target value of voltage difference VDS discussed above with respect to activation voltage generator 112 and
By the configurations discussed above, each of activation voltage generators 200A-200C operates to generate one of voltages VB or VC having a value based on current flow through one of resistive devices R1 or RP2. By configuring resistive devices R1 and RP2 to have resistance values based on a drain-source voltage of a selection transistor of an RRAM device, e.g., RRAM device 150, each of activation voltage generators 200A-200C generates the one of voltages VB or VC having temperature and process-dependent variations that reflect temperature and process-dependent variations of the selection transistor.
A memory circuit, e.g., memory circuit 100 discussed above with respect to
Path segment 300 includes PMOS transistors P12 and P13 coupled in series with a resistive device R5. Gates of transistors P12 and P13 are configured to receive respective signals S17 and S18, and transistors P12 and P13 are thereby controllable to provide a portion of a current path, e.g., current path 110P discussed above with respect to memory circuit 100 and
Values of voltage differences generated across transistors P12 and P13 are based on dimensions of transistors P12 and P13 and on voltage levels of signals S17 and S18. Transistors P12 and P13 have dimensions based on dimensions of one or more transistors in current path 120P discussed above with respect to memory circuit 100 and
In some embodiments, transistor P12 has dimensions that match those of transistors P2 and P3, and transistor P13 has dimensions that match those of transistors P4-P9, discussed above with respect to
In various embodiments, one or both of transistors P12 or P13 is controllable to provide the portion of the current path based on one or both of signals S17 or S18 having voltage levels that match those of one or more of signals S1-S8, discussed above with respect to
Resistive device R5 is one or more conductive segments configured to provide a path resistance. In some embodiments, the one or more conductive segments include a resistive material having a TCR corresponding to a metal and dimensions configured to provide the path resistance having a predetermined resistance value. In some embodiments, the resistive material includes a metal, e.g., copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), and/or another metal, and/or another material suitable for having the TCR properties. In some embodiments, the predetermined resistance value is based on a resistance value of a portion of current path 120P, as discussed above with respect to
In various embodiments, path segment 300 does not include one or more of transistors P12 or P13 or resistive device R5 and is thereby configured to generate a voltage difference, e.g., voltage difference VD116, based on one or two of transistors P12 or P13 or resistive device R5. In various embodiments, path segment 300 includes one or more IC elements (not shown) other than or in addition to transistors P12 or P13 or resistive device R5, and is thereby configured to generate the voltage difference based on the one or more IC elements.
By being included in memory circuit 100 discussed above with respect to
Path segment 400 includes NMOS transistors N12 and N13 coupled in series with a resistive device R6. Gates of transistors N12 and N13 are configured to receive respective signals S19 and S20, and transistors N12 and N13 are thereby controllable to provide a portion of a current path, e.g., current path 110P discussed above with respect to memory circuit 100 and
Values of voltage differences generated across transistors N12 and N13 are based on dimensions of transistors N12 and N13 and on voltage levels of signals S19 and S20. Transistors N12 and N13 have dimensions based on dimensions of one or more transistors in current path 120P discussed above with respect to memory circuit 100 and
In some embodiments, transistor N12 has dimensions that match those of transistors N2-N7, and transistor N13 has dimensions that match those of transistor N8, discussed above with respect to
In various embodiments, one or both of transistors N12 or N13 is controllable to provide the portion of the current path based on one or both of signals S19 or S20 having voltage levels that match those of one or more of signals S9-S16, discussed above with respect to
Resistive device R6 is one or more conductive segments configured to provide a path resistance. In some embodiments, the one or more conductive segments include a resistive material having a TCR corresponding to a metal and dimensions configured to provide the path resistance having a predetermined resistance value. In some embodiments, the resistive material includes a metal, e.g., copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), and/or another metal, and/or another material suitable for having the TCR properties. In some embodiments, the predetermined resistance value is based on a resistance value of a portion of current path 120P, as discussed above with respect to
In various embodiments, path segment 400 does not include one or more of transistors N12 or N13 or resistive device R6 and is thereby configured to generate a voltage difference, e.g., voltage difference VD118, based on one or two of transistors N12 or N13 or resistive device R6. In various embodiments, path segment 400 includes one or more IC elements (not shown) other than or in addition to transistors B12 or N13 or resistive device R6, and is thereby configured to generate the voltage difference based on the one or more IC elements.
By being included in memory circuit 100 discussed above with respect to
Selection transistor N14 includes a gate coupled to input terminal 151 configured to carry a signal (not labeled) that includes either activation voltage VWL or a second voltage level, e.g., a voltage level corresponding to power reference voltage VSS. RRAM device 500 is thereby configured to provide a current path between terminals 152 and 153 that includes variable resistance structure R7 responsive to activation voltage VWL, and interrupt the current path responsive to signal VWL having the second voltage level.
In the embodiment depicted in
As depicted in
Resistive layer L1 is one or more layers of dielectric materials configured to receive voltage difference VR7 across thickness LT. In various embodiments, resistive layer L1 includes one or more of an oxide of tungsten (W), tantalum (Ta), titanium (Ti), nickel (Ni), cobalt (Co), hafnium (Hf), ruthenium (Ru), zirconium (Zr), zinc (Zn), iron (Fe), tin (Sn), aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), or another suitable element, a composite material including, e.g., silicon, or another material capable of having either the HRS or LRS. In some embodiments, resistive layer L1 has thickness LT ranging from 20 nanometers (nm) to 100 nm.
Based on the presence or absence of filament F1, resistive layer L1 has either the LRS or HRS, respectively, as discussed above with respect to RRAM device 150 and
In various embodiments, resistive layer L1 has a resistance value ranging from 1 kilo-ohm (kΩ) to 4 kΩ in the LRS and/or a resistance value ranging from 15 kΩ to 30 kΩ in the HRS.
RRAM device 500 is thereby configured to, in operation, generate current Id in response to activation voltage VWL based on voltage difference VR7 and the resistance value of resistive layer L1.
By being included in memory circuit 100 discussed above with respect to
In some embodiments, biasing the RRAM device using method 600 includes performing a write or read operation on the RRAM device. In some embodiments, biasing the RRAM device using method 600 includes forming a filament, e.g., filament F1 discussed above with respect to RRAM device 500 and
The sequence in which the operations of method 600 are depicted in
At operation 610, in some embodiments, an activation voltage is generated based on a resistance value of a resistive device. Generating the activation voltage includes controlling a current across the resistive device to produce a target value of a difference voltage corresponding to a drain-source voltage of a selection transistor of the RRAM device. Based on the target value, an amplifier is used in a closed loop configuration to drive a gate of a transistor to generate a voltage difference, and the gate voltage is generated as the activation voltage.
In some embodiments, generating the activation voltage includes generating activation voltage VWL discussed above with respect to memory circuit 100 and
At operation 620, a first current is conducted in a first current path to generate a voltage difference. Conducting the first current includes conducting the first current having a predetermined current value. The first current path includes at least one IC element that corresponds to an IC element of a second current path that includes the RRAM device.
In some embodiments, conducting the first current in the first current path includes conducting current Ic in current path 110P discussed above with respect to memory circuit 100 and
In some embodiments, conducting the first current in the first current path includes generating the voltage difference across a transistor having a conductance level based on the activation voltage. In some embodiments, generating the voltage difference across the transistor includes generating the voltage difference across transistor N1 discussed above with respect to memory circuit 100 and
In some embodiments, conducting the first current in the first current path includes generating the voltage difference across a path segment having a resistance value based on a portion of the second current path. In some embodiments, generating the voltage difference across the path segment includes generating the voltage difference across one or both of path segments 116 or 118 discussed above with respect to memory circuit 100 and
In some embodiments, conducting the first current in the first current path includes generating the voltage difference across a resistive device having a resistance value based on a resistance value of the RRAM device. In some embodiments, generating the voltage difference across the path segment includes generating the voltage difference across resistive device RP1 discussed above with respect to memory circuit 100 and
At operation 630, in some embodiments, the voltage difference is included in a bias voltage. In various embodiments, including the voltage difference includes including one or more of the voltage differences generated in operation 620. Because the voltage difference is based on at least one element of the first current path corresponding to at least one element of the second current path, including the voltage difference causes the bias voltage to have a value based on a resistance value of the second current path that includes the RRAM device.
In various embodiments, including the voltage difference includes including one or more of voltage differences VD118, VDRP1, VDS, or VD116 discussed above with respect to memory circuit 100 and
At operation 640, in some embodiments, a drive voltage is generated from the bias voltage. In various embodiments, the drive voltage is equal to the bias voltage or otherwise derived from the bias voltage. Because the bias voltage is based on a resistance value of the second current path that includes the RRAM device, the drive voltage derived from the bias voltage is based on the resistance value of the second current path.
In some embodiments, generating the drive voltage includes generating drive voltage VBL discussed above with respect to memory circuit 100 and
At operation 650, in some embodiments, the drive voltage is applied to the RRAM device. Because the drive voltage is based on the resistance value of the second current path, the drive voltage is applied to the RRAM device based on the resistance value of the second current path.
In some embodiments, applying the drive voltage to the RRAM device includes applying drive voltage VBL to RRAM device 150 discussed above with respect to memory circuit 100 and
At operation 660, in some embodiments, the activation voltage is applied to the RRAM device. Because the activation voltage is based on the resistance value of the selection transistor, the activation voltage is applied to the RRAM device based on the resistance value of the selection transistor.
In some embodiments, applying the activation voltage to the RRAM device includes applying activation voltage VWL to RRAM device 150 discussed above with respect to memory circuit 100 and
By executing some or all of the operations of method 600, a bias voltage and/or activation voltage generated as part of biasing an RRAM device in a write or read operation are adapted to temperature and process-dependent variations in the RRAM current path resistance, thereby achieving the benefits discussed above with respect to memory circuit 100.
In some embodiments, a memory circuit includes a bias voltage generator including a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path, a drive circuit configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and an RRAM device configured to conduct a second current responsive to the drive voltage. In some embodiments, the current source is configured to output the first current having a current level based on a compliance current of the RRAM device. In some embodiments, the circuit includes a second current path configured to conduct the second current, the RRAM device is included in the second current path, the first current path comprises a path segment having a resistance value based on a portion of the second current path between the drive circuit and the RRAM device, and the voltage difference is based on the resistance value. In some embodiments, the circuit includes a second current path configured to conduct the second current, the RRAM device is included in the second current path, the first current path comprises a path segment having a resistance value based on a portion of the second current path between the RRAM device and a reference node, and the voltage difference is based on the resistance value. In some embodiments, the RRAM device includes a resistive layer configured to conduct the second current, the first current path includes a resistive device having a resistance value based on the resistive layer, and the voltage difference is based on the resistance value. In some embodiments, the resistive layer is capable of having the HRS and the LRS, and the resistance value is based on the LRS. In some embodiments, the RRAM device includes a selection transistor configured to conduct the second current, the first current path includes a transistor configured to generate the voltage difference by conducting the first current, and the memory circuit is configured to generate a selection transistor voltage difference having a value corresponding to a value of the voltage difference. In some embodiments, the selection transistor is configured to conduct the second current responsive to an activation voltage, and the transistor in the first current path is configured to conduct the first current responsive to the activation voltage. In some embodiments, the bias voltage generator includes an amplifier configured to generate the activation voltage based on a resistance value of a resistive device.
In some embodiments, a memory circuit includes an activation voltage generator configured to generate an activation voltage based on a resistance value of a resistive device, a first transistor configured to conduct a first current from a current source responsive to the activation voltage, thereby generating a voltage difference, and an RRAM device including a selection transistor configured to generate a selection transistor voltage difference responsive to the activation voltage, the selection transistor voltage difference having a value corresponding to a value of the voltage difference. In some embodiments, wherein the resistive device is a first resistive device of a voltage divider in parallel with a conductive path of the first transistor. In some embodiments, the activation voltage generator includes a second transistor configured to control a second current through the resistive device. In some embodiments, the activation voltage generator is configured to bias a gate of the second transistor responsive to a value of a reference voltage. In some embodiments, the resistive device is configured to receive a second current from another current source, the first current and the second current having a same current level. In some embodiments, the resistive device includes a polycrystalline silicon material. In some embodiments, the memory circuit further includes an amplifier configured to receive a target value of the voltage difference from the activation voltage generator, and output the activation voltage to the first transistor and the selection transistor.
In some embodiments, a method of performing a write operation on an RRAM device includes conducting a first current in a first current path to generate a voltage difference, including the voltage difference in a bias voltage, generating a drive voltage from the bias voltage, and applying the drive voltage to the RRAM device. In some embodiments, conducting the first current in the first current path includes generating the voltage difference across a path segment having a resistance value based on a portion of a second current path that includes the RRAM device. In some embodiments, conducting the first current in the first current path includes generating the voltage difference across a transistor having a conductance level based on an activation voltage. In some embodiments, the method further includes generating the activation voltage based on a resistance value of a resistive device, and applying the activation voltage to the RRAM device.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Chou, Chung-Cheng, Lin, Zheng-Jun, Lai, Chien-An, Chen, Hsu-Shun, Tseng, Pei-Ling
| Patent | Priority | Assignee | Title |
| 11527285, | Jun 01 2018 | Taiwan Semiconductor Manufacturing Company, Ltd. | RRAM current limiting method |
| 11942150, | Jun 01 2018 | Taiwan Semiconductor Manufacturing Company, Ltd. | RRAM circuit |
| Patent | Priority | Assignee | Title |
| 10115350, | May 21 2004 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having rectifying elements connected to a pixel of a display device |
| 7548467, | Dec 28 2006 | Samsung Electronics Co., Ltd. | Bias voltage generator and method generating bias voltage for semiconductor memory device |
| 9711203, | Aug 27 2015 | Samsung Electronics Co., Ltd. | Memory device including boosted voltage generator |
| 20100110768, | |||
| 20130070534, | |||
| 20170110191, | |||
| CN101246734, | |||
| CN101561994, | |||
| KR20100049926, | |||
| TW201040963, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| May 24 2019 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. | (assignment on the face of the patent) | / | |||
| May 28 2019 | CHOU, CHUNG-CHENG | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 049585 | /0890 | |
| May 28 2019 | CHEN, HSU-SHUN | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 049585 | /0890 | |
| May 28 2019 | LAI, CHIEN-AN | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 049585 | /0890 | |
| May 28 2019 | TSENG, PEI-LING | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 049585 | /0890 | |
| May 28 2019 | LIN, ZHENG-JUN | Taiwan Semiconductor Manufacturing Company, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 049585 | /0890 |
| Date | Maintenance Fee Events |
| May 24 2019 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
| Aug 07 2024 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Date | Maintenance Schedule |
| Feb 23 2024 | 4 years fee payment window open |
| Aug 23 2024 | 6 months grace period start (w surcharge) |
| Feb 23 2025 | patent expiry (for year 4) |
| Feb 23 2027 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Feb 23 2028 | 8 years fee payment window open |
| Aug 23 2028 | 6 months grace period start (w surcharge) |
| Feb 23 2029 | patent expiry (for year 8) |
| Feb 23 2031 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Feb 23 2032 | 12 years fee payment window open |
| Aug 23 2032 | 6 months grace period start (w surcharge) |
| Feb 23 2033 | patent expiry (for year 12) |
| Feb 23 2035 | 2 years to revive unintentionally abandoned end. (for year 12) |