Efficient and scalable computations with sparse tensors

Abstract

In a system for storing in memory a tensor that includes at least three modes, elements of the tensor are stored in a mode-based order for improving locality of references when the elements are accessed during an operation on the tensor. To facilitate efficient data reuse in a tensor transform that includes several iterations, on a tensor that includes at least three modes, a system performs a first iteration that includes a first operation on the tensor to obtain a first intermediate result, and the first intermediate result includes a first intermediate-tensor. The first intermediate result is stored in memory, and a second iteration is performed in which a second operation on the first intermediate result accessed from the memory is performed, so as to avoid a third operation, that would be required if the first intermediate result were not accessed from the memory.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to and claims the benefit of priority to U.S. Provisional Patent Application Ser. No. 61/648,848 filed on May 18, 2012, the entirety of which is hereby incorporated by reference.

GOVERNMENT INTERESTS

Portions of this invention were made with U.S. Government support under contract/instrument Department of Defense SBIR H98230-12-C-0229. The U.S. Government has certain rights in the invention.

FIELD OF THE INVENTION

The present invention generally concerns computations with data. More particularly, the invention concerns a system, methods, and apparatus for performing memory-efficient operations on large scale data.

BACKGROUND OF THE INVENTION

Using linear algebraic techniques to find structures and properties of data in data analytics applications is well established. For example, application of linear algebraic formulations for solving graph analysis problems is known. These linear techniques are applicable only to two-dimensional data and require the data to be represented in terms of matrices. However real-world data are often multi-dimensional with multiple attributes. Tensors or multi-dimensional arrays are a natural fit to represent data with multiple attributes and dimensionality. In order to perform operations on tensors, multi-linear algebra, a generalization of linear algebra to higher dimensions, is increasingly used in real-world applications for extracting and explaining the properties of multi-attribute data. Multi-linear algebraic computations or tensor computations such as tensor factorizations or decompositions have applications in a range of domains such as signal processing, data mining, computer vision, numerical linear algebra, numerical analysis, graph analysis, cyber security, and quantum chemistry.

Two of the prominent tensor decompositions are CANDECOMP/PARAFAC (CP) and Tucker decompositions. These decompositions are popular in scientific domains and also in modern applications such as social network analysis, network traffic analysis and web search mining.

The CP decomposition decomposes a tensor into a sum of component rank-one tensors (A N-way tensor is called a rank-one tensor if it can be expressed as an outer product of N vectors). The CP decomposition that factorizes an input tensor X of size I₁ x . . . x I_N into R components (with factor matrices A⁽¹⁾ . . . A^(N) and weight vector λ) is of the form:

$X=\sum _{r=1}^R{\lambda }_r{a}_r^{\left(1\right)}\dots a_r^{\left(N\right)}$
where a_r⁽ⁿ⁾ is the r-th column of the factor matrix A⁽ⁿ⁾ of size I_n x R.

The Tucker decomposition decomposes a tensor into a core tensor multiplied by a matrix along each mode. The Tucker decomposition that factorizes an input tensor X of size I₁ x . . . x I_N into a core tensor G of size R₁ x . . . x R_N and factor matrices A⁽¹⁾ . . . A^(N) (where each factor matrix A⁽ⁿ⁾ is of size I_n x R_n) is of the form:
X≈G x₁ A⁽¹⁾x₂ . . . x_N A^(N)

A widely used algorithm for computing Tucker decomposition is the higher-order orthogonal iteration (HOOI) method (L. D. Lathauwer, B. D. Moor, and J. Vandewalle, “On the Best Rank-1 and Rank-(R1, R2, . . . , RN) Approximation of Higher-Order Tensors,” SIAM J. Matrix Anal. Appl., vol. 21, pp. 1324-1342, March 2000).

An embodiment of the HOOI algorithm/method is presented in FIG. 6. The HOOI method involves various basic computational kernels that include SVD and n-Mode matrix product. An important tensor operation that is widely used in multi-linear algebra arithmetic is the n-Mode matrix product. The n-Mode matrix product of a tensor X of size I₁ x . . . x I_N with a matrix A of size J x I_n(denoted by X x_n A) results in a tensor of size I₁ x . . . x I_n−1 x J x I_n+1 x . . . x I_N such that (i₁ . . . i_n−1ji_n+1 . . . i_N)th element of (X x_n A) is given by

$\sum _{\mathrm{in}=1}^{\mathrm{In}}{x}_{i1\dots \mathrm{iN}}{a}_{jin}.$

A major challenge in real-world applications is handling the sparsity of data, as real-world data are not only multi-dimensional but also such that linkages between multiple attributes of data have a sparse characteristic. Sparse linear algebra primitives are widely used for two-dimensional data analysis and techniques for optimizing and parallelizing key sparse linear algebraic primitives such as sparse matrix vector multiply, sparse matrix multiply and the like have been studied extensively and are available in literature (See, e.g., F. G. Gustavson, “Two Fast Algorithms for Sparse Matrices: Multiplication and Permuted Transposition,” ACM Transactions on Mathematical Software, vol. 4, no. 3, pp. 250-269, 1978; T. A. Davis, Ed., Direct Methods for Sparse Linear Systems. SIAM, 2006; and A. Buluc and J. R. Gilbert, “Parallel Sparse Matrix-Matrix Multiplication and Indexing: Implementation and Experiments,” SIAM Journal of Scientific Computing (SISC), 2012). However, for performance and storage reasons, it is not efficient to use any existing sparse matrix format to store sparse tensors and apply sparse matrix primitives to solve sparse tensor problems. In other words, using sparse matrix formats to store sparse tensors typically requires a large amount of memory. Performing operations on sparse tensors using sparse matrix formats can result in significant performance penalty, in part, due to the time consumed in accessing various data elements of the sparse tensor.

A common or natural form of representing a sparse tensor is the coordinate sparse tensor format in which each non-zero is stored along with its index. FIG. 1. illustrates the coordinate sparse tensor format. A common storage scheme for storing sparse matrices is the Compressed Row Storage (CRS) format or the Compressed Column Storage (CCS) format. Sparse tensors are sometimes “flattened” or “matricized” and stored in the CRS or CCS format. There are few other tensor storage formats such as the Extended Karnaugh Map Representation (EKMR) format and its compressed sparse versions, namely, the Extended CRS (ECRS) and the Extended (ECCS) formats (See, e.g., C.-Y. Lin, J.-S. Liu, and Y.-C. Chung, “Efficient Representation Scheme for Multidimensional Array Operations,” IEEE Transactions on Computers, vol. 51, pp. 327-345, 2002; and C.-Y. Lin, Y.-C. Chung, and J.-S. Liu, “Efficient data compression methods for multidimensional sparse array operations based on the EKMR scheme,” IEEE Trans. Comput. 52(12) (2003), pp. 1640-1646). These formats do not account for tensor properties, and also, in using these formats the tensor operation needs to be restructured as a matrix operation. Therefore, these formats do not provide the benefits of viewing the tensor as a higher than two dimensional array and performing tensor operations. Some sparse tensor storage formats are specialized to specific sparsity patterns such as patterns in symmetric or super-symmetric sparse tensors. (See e.g. Geir Gundersen and Trond Steihaug, “Sparsity in higher order methods for unconstrained optimization,” Optimization Methods and Software 27(2):275-294 (2012)). These and other sparse tensor storage formats (see e.g. R.-G. Chang, T.-R. Chuang, and J. K. Lee, “Parallel sparse supports for array intrinsic functions of Fortran 90,” J. Supercomput. 18(3) (2001), pp. 305-339), do not account for tensor properties, and do not support efficient storage of dense sub-tensors, e.g., those present within a sparse tensor.

Another major challenge in real-world applications is that the data that these applications process are usually large and the large size of the data poses a significant challenge to the efficiency of the computations performed with the data. Large-scale data also poses a threat of “blowing up” system memory during computation resulting in inability to finish the computation.

The coordinate sparse tensor format and other known formats for storing a tensor are known to be inefficient or even inadequate while performing computations on large data sets requiring large tensors, e.g., tensors storing tens or hundreds of millions of values. In this context, inadequate generally means that in some instances the memory/storage requirement according to the format used to store the tensor or partial results that are tensors becomes so large that a computer/server/multi-processor system used to perform operations on the data runs out of memory, preventing completion of the task. This is often described as memory blowup.

Memory blowup problem is a phenomenon commonly observed by users in Tucker decomposition—a commonly used procedure in several tensor based large-data computations. Handling memory consumption in large-scale tensor computations is very important not only for preventing potential memory overflows but also for improving the overall execution time. Some techniques that address the memory blowup problem, particularly in Tucker decomposition and/or n-Mode matrix product, also cannot enable computers to efficiently complete the large-data analysis tasks in several instances. Accordingly, there is need for improved methods and systems for performing computations on tensors.

SUMMARY OF THE INVENTION

The present invention presents various embodiments for addressing the aforementioned major challenges in computations involving sparse tensor or multi-dimensional array data. In one embodiment, new sparse tensor storage formats that provide memory storage benefits and performance benefits while executing sparse tensor computations are presented. One format is called “mode-generic” sparse tensor format that is a generic representation of tensor to conveniently store sparse and semi-sparse tensors. Another format is called “mode-specific” sparse format that is a special form of the generic representation that is suitable for performing computations along a specific mode or dimension of the tensor. These new sparse tensor storage formats may not only store the tensor data using less memory than the conventional techniques, but also arrange the data in the memory in such a manner that the data elements likely to be accessed frequently during a certain time period, or while computing a portion of a large computation, are stored relatively close to each other in the memory, so as to improve data locality in sparse tensor computations and to reduce unnecessary memory storage in the process of large data computations.

In another embodiment, a novel optimization that aims to improve data reuse and reduce redundant or unnecessary computations in a sequence of tensor operations (e.g., in Tucker decomposition) is presented. It should be understood that Tucker decomposition is only an example of tensor computation. Various embodiments described herein can be used to improve performance and/or memory usage of several types of tensor operations such as those involving matrix operations on a tensor. In various embodiments, data reuse optimization technique reuses previously computed data and avoids redundant computation in a sequence of tensor operations.

In yet another embodiment, a memory-efficient scalable technique to handle large-scale sparse tensor computations is presented. The technique couples the data reuse optimization and the advantage of our sparse tensor formats to store semi-sparse tensors to arrive at a memory-efficient scalable solution to address the memory blowup challenges in large sparse tensor computations. The technique, in addition to addressing the memory blowup issues, can also help speed up the execution of the computations.

Accordingly, in one aspect, various embodiments feature an article of manufacture that includes instructions to configure a processor, a method, and/or a system that enables efficiently storing a tensor. The tensor includes at least three modes, and the system includes a memory, and a processor in electronic communication with the memory. The processor is configured according to the system configuration, or by the instructions included in the article of manufacture, and the method is provided to store in the memory elements of the tensor in a mode-based order for improving locality of references when the elements are accessed during an operation on the tensor. The memory can be local to the processor, or may be remote thereto. The memory may also be shared and/or distributed memory. The memory includes volatile memory such as RAM, and non-volatile memory such as a disk, CD, etc. The processor includes any computing device, such as desktops, laptops, hand-held, mobile computing devices, and servers. The processor also includes multi-processor and/or multi-core systems.

In some embodiments, the method is provided, and the processor included in the system, or configured by the instructions on the article of manufacture is further configured, to store in the memory a first data structure that includes one or more sparse mode index tuples associated with the tensor. The method and the processor are also adapted to store a second data structure that includes a number of significant values in the tensor. Each significant value, e.g., a “non-zero” value, corresponding to a sparse mode index tuple in the first data structure. The first data structure may include a matrix having b rows, b being a number of sparse mode index tuples in the plurality of sparse mode index tuples. Each row of the matrix may include a unique sparse mode index tuple. The matrix may also include k columns, each column corresponding to a sparse mode. The second data structure may include a sub-tensor.

In some embodiments, the method is provided, and the processor included in the system, or configured by the instructions on the article of manufacture is further configured, to store in the memory elements of the sub-tensor in a mode-based order for improving locality of references when the elements of the sub-tensor are accessed during an operation on the sub-tensor. The processor included in the system, or configured by the instructions on the article of manufacture and/or the method, may be further configured to identify a set of sparse modes of a tensor, and a subset of sparse modes from the set of sparse modes. The identified subset may include one of more sparse mode index tuples.

In some embodiments, the set of sparse modes includes each sparse mode of the tensor, and the subset of sparse modes is same as the set of sparse modes, i.e., each sparse mode of the tensor is included in the subset. Moreover, the tensor may include one or more dense modes. The processor included in the system, or configured by the instructions on the article of manufacture and/or the method, may be further configured to select a candidate sparse mode from the set of sparse modes. In identifying the subset of sparse modes, the candidate sparse mode selected from the set of sparse modes may be excluded from the subset, and each tuple in the several sparse-mode index tuples excludes indices of the candidate sparse mode. The tensor may lack (not have) a dense mode, i.e., all modes are determined to be sparse.

In some embodiments, the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, are further configured to store a third data structure C, that includes indices in the selected candidate sparse mode. Each index in the third data structure C may be associated with a significant value in the tensor. A fourth data structure t, including a cell corresponding to each sparse mode index tuple in the first data structure may also be stored. Each cell may represent a number of indices in the selected candidate sparse mode that are associated with a tuple corresponding to that cell. The third data structure C, the fourth data structure t, or both may include or be formed as an array or a vector.

In another aspect, various embodiments feature an article of manufacture that includes instructions to configure a processor, a method, and/or a system that facilitate data reuse in a tensor transform. The tensor has at least three modes, and the tensor transform includes a number of iterations. The system includes a memory and a processor in electronic communication with the memory. Each of the memory and the processor include various types of storage devices and computing devices, respectively, as described above. The processor included in the system, or configured by the instructions on the article of manufacture and/or the method, is configured to perform a first iteration that includes a first operation (e.g., an n-Mode matrix product) on the tensor to obtain a first intermediate result. The first intermediate result includes a first intermediate-tensor. The first intermediate result is stored in the memory, and the processor is configured to perform a second iteration that includes a second operation on the first intermediate result accessed from the memory. Because the second operation is performed on the intermediate result accessed from the memory, a third operation is avoided. For a required computation involving the tensor, the third operation is required if the first intermediate result is not accessed from the memory.

The second operation may use an operand computed during the first iteration. The operand may include a matrix. The first operation, the second operation, or both, may include an n-Mode product. Other matrix operations may also form the first and/or second operation. Each iteration in the several iterations in the transform may include a sequence of operations, and the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, may be further configured to order the sequence of operations in each iteration according to an increasing order or a decreasing order of modes of the tensor.

In some embodiments, each iteration in the several iterations in the transform includes a sequence of operations, and the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, is further configured to order the sequence of operations in each iteration in a first set of iterations from the several iterations according to an increasing order of modes of the tensor. The sequence of operations in each iteration in a second set of iterations in the several iterations is ordered according to a decreasing order of modes of the tensor.

The processor included in the system, or configured by the instructions on the article of manufacture and/or the method, is further configured to store in the memory, elements of the first intermediate tensor in a mode-based order for improving locality of references when the elements of the intermediate tensor are accessed during an operation thereon. To store the elements of the first intermediate tensor in the mode-based order, the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, may be further configured to store in the memory a first data structure that includes a number of sparse mode index tuples associated with the first intermediate tensor. A second data structure that includes a number of significant values in the first intermediate tensor may also be stored. Each significant value may correspond to a sparse mode index tuple in the first data structure.

In some embodiments, the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, is further configured to identify a set of reusable tensors to be computed during a plurality of iterations. The processor may also evaluate, for each reusable tensor in the set, a memory storage requirement, and may select a subset of reusable tensors from the set such that a total memory storage memory requirement for all of the reusable tensors in the subset does not exceed a preselected threshold. The preselected threshold can be size of the memory accessible to the processor.

In some embodiments, the set of reusable tensors comprises all reusable tensors to be computed during the plurality of iterations. To evaluate the memory storage requirement for each reusable tensor in the set, the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, may be further configured to determine a degree of reuse of the reusable tensor. The selection may be further based on, at least in part, the degree of reuse of each reusable tensor in the set.

In some embodiments, one or more iterations in the several iterations in the transform include a sequence of operations. Each operation may correspond to a mode of the tensor, and the processor included in the system, or configured by the instructions on the article of manufacture and/or the method, may be further configured to perform a first group of operations in element-wise mode, and perform a second mode of operation in standard mode. To evaluate the memory storage requirement for each reusable tensor, the processor included in the system, or configured by the instructions on the article of manufacture and/or the method may be further configured to determine a memory size required to store the reusable tensor by storing in the memory elements of the reusable tensor in a mode-based order for improving locality of references when the elements of the reusable tensor are accessed during an operation on the reusable tensor.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the present invention taught herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

FIG. 1 illustrates the representation of sparse tensors in coordinate sparse tensor format;

FIG. 2A depicts an exemplary sparse tensor and storage thereof using the conventional co-ordinate sparse tensor formal, and FIG. 2B illustrates a classification of dense and sparse modes, according to one embodiment;

FIG. 3 illustrates the representation of a sparse tensor in a mode-generic sparse tensor format, according to one embodiment;

FIGS. 4A-4C present an exemplary sparse tensor represented in three sparse tensor storage formats: the conventional coordinate format (shown in FIG. 4A), a mode-generic format according to one embodiment (shown in FIG. 4B), and a mode-specific format, according to one embodiment (shown in FIG. 4C);

FIG. 5 illustrates the representation of a sparse tensor in a mode-specific sparse tensor format, according to one embodiment;

FIG. 6 schematically depicts computations in the original higher-order orthogonal iteration (HOOI) method for computing the Tucker decomposition, and indications of potential data reuse and computation avoidance, according to one embodiment;

FIG. 7 schematically depicts computations in a modified higher-order orthogonal iteration (HOOI) method for computing the Tucker decomposition of a tensor, and corresponding indications of potential data reuse and computation avoidance, according to one embodiment;

FIG. 8 schematically depicts computations in a further modified higher-order orthogonal iteration (HOOI) method for computing the Tucker decomposition of a tensor, and corresponding indications of potential data reuse and computation avoidance, according to one embodiment; and

FIG. 9 illustrates a memory blowup problem in Tucker decomposition in the “all but one n-Mode matrix product sequence” operation, according to one embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Sparse tensors are typically represented in coordinate format (as illustrated in FIG. 1) by explicitly storing the non-zero indices and values of the tensor. If there are P non-zeros for a N mode tensor, the coordinate format stores the indices or subscripts of the P non-zeros in a P×N matrix and the values of the non-zeros in a P×1 vector. The coordinate format is simple and flexible. Further, the computations are not specialized for any ordering of the modes. However, the simplicity and flexibility of the format may be adverse to data locality based on the access pattern of the non-zeros.

When the non-zero values of a sparse tensor are stored not in any specific order of their indices, any tensor operation that is performed along a specific mode (mode-specific operation) would result in very poor locality with respect to accumulating the results of the operation in the output. This is because different non-zeros in the input tensor may contribute to the same element of the output and an arbitrary and/or a random order of the indices may result in accessing the same element in different time instances that are far apart in the execution time-line (resulting in loss of locality). Furthermore, the coordinate format is inefficient in terms of memory storage when the tensor is semi-sparse, i.e., when the tensor has dense sub-tensors.

For any mode-specific operation, it is beneficial in terms of data locality if the storage format supports enumerating the “fibers” (sections of a tensor obtained by fixing indices along all but one mode) corresponding to the mode efficiently. A fiber is generally understood as a higher-order analogue of a matrix row or column. A mode-n fiber may be obtained by fixing the indices along all modes except mode n. For example, for a 3×4×4×5 tensor X, a mode-3 fiber obtained after fixing the indices along modes 1, 2, and 4 to be 2, 3, and 5, respectively, is the vector [X₂₃₁₅ X₂₃₂₅ X₂₃₃₅ X₂₃₄₅].

A motivation behind our new sparse tensor formats is to facilitate the improvement of data locality of the sparse tensor references and to efficiently support the storage of dense sub-tensors within a sparse tensor. To improve data locality and data storage efficiency, in one embodiment we present a mode-generic sparse tensor storage format and in another embodiment we present a mode-specific sparse tensor storage format. In general, the mode-generic format is beneficial for any tensor operation and the mode-specific format is advantageous for mode-specific tensor operations. The mode-specific format can support efficient enumeration of fibers corresponding to a mode. The mode-generic and mode-specific formats take into account that some of the modes of the tensor may be dense (for example, tensors resulting from a sparse tensor dense matrix product) and hence are capable of efficiently representing dense sub-tensors within a sparse tensor.

With reference to FIGS. 2A and 2B we classify modes as dense or sparse as per the following criteria. For any mode n, (e.g., mode 3 of the 4-mode tensor Y) we enumerate the “fiber-index-tuples” 202 of the mode, where fiber-index-tuples are the unique index tuples of the non-zeros of the sparse tensor excluding the indices of mode n (e.g., mode 3 of tensor Y). If for each fiber-index-tuple, there exists a non-zero for each index of mode n (i.e., indices 1, 2, and 3 of mode 3, because the size of mode 3 is 3), then mode n is designated to be completely dense. In the case of tensor Y in FIG. 2A, mode 3 204 is completely dense. If there exists a non-zero for each index of mode n for most of the fiber-index-tuples (say for “q” fiber-index-tuples, where q is less than the total number of fiber-index-mode tuples), then mode n is considered to be mostly dense. The quantitative factor “q” governing the density of a mode can be configured by the user. If a mode is completely or mostly dense, it is considered as dense, otherwise it is considered as sparse.

In some embodiments, “non-zero” is also configured by a user. For example, absolute values less than or equal to a user-specified quantity “e” may be considered to be “zero” and the absolute values greater than “e” (e.g., 0.00001, 0.1, 0.5, 2, etc.) may be considered to be “non-zero.” As such, a non-zero value can also be called a significant value. In general, references to operations such as multiply and plus, and values such as zero, and non-zero, for the elements of tensors may be understood to refer to appropriate implementations where these operators and elements correspond to operators, elements, and identity elements generally over algebraic rings, semi-rings, or abelian rings, or their approximations, for example, algebras over integers, rationals, reals, complex numbers, digital floating point representations, and including min-plus algebras over numbers and symbolic operators and strings.

In one embodiment illustrated with reference to FIG. 3, a tensor may be stored in a mode-generic format as follows:

• • sparse and dense modes are identified and separated;
  • thereafter, storage for a N-th order tensor of size M₁×M₂×. . . ×M_N is as follows:
  • 1) k: a scalar that stores the number of modes identified as sparse modes,
  • 2) b: a scalar that stores the number of distinct sparse mode index tuples (or buckets),
  • 3) d: a l×1 vector that stores the list of l dense modes (where l=N−k),
  • 4) S: a b×k matrix that stores the coordinates/indices of the k sparse modes in each of the b distinct buckets, such that each bucket stores one distinct sparse mode index tuple, and

$5)D\text{:}\{\begin{array}{c}\begin{array}{c}\mathrm{ab}\times M_{d1}\times M_{d2}\times \dots \times M_{d1}\mathrm{array}({\mathrm{storing}}^{″}{b}^{″}\\ \mathrm{dense}\mathrm{sub}\text{-}\mathrm{tensors},\mathrm{when}1>0\end{array}\\ \mathrm{ab}\times 1\mathrm{vector},\mathrm{when}l=0\end{array}.$

With reference to FIG. 4B, for the exemplary tensor Y (described with reference to FIG. 2A), k=3 for the mode-generic format, because the tensor Y has three sparse modes—modes 1, 2, and 4. The number of distinct sparse mode index tuples, b, is 4. The number of dense modes is 1, because only mode 3 is determined to be dense. Therefore, the vector d is {3}. A sub-tensor [14, 7, 9] is associated with the first sparse mode index tuple (1, 1, 4). Another sub-tensor [49, 28, 35] is associated with a different sparse mode index tuple (2, 3, 1). Because tensor Y has only one dense mode, the sub-tensors corresponding to the dense mode 3 can be represented in the form of a vector or an array. The tensor Y, however, is illustrative only, and in general a sub-tensor associated with each sparse mode index tuple may have several dense modes.

In one embodiment illustrated with reference to FIG. 5, a tensor may be stored in a mode-specific format as follows:

• • sparse and dense modes are separated, and one sparse mode is selected as a candidate sparse mode;
  • thereafter, storage is as follows for a N-th order tensor of size M₁×M₂×. . . ×M_N is as follows:
  • 1) c: a scalar that indicates the selected candidate sparse mode,
  • 2) k: a scalar that stores the number of sparse modes excluding the candidate sparse mode,
  • 3) b: a scalar that stores the number of distinct non-candidate sparse mode index tuples (or buckets),
  • 4) d: a l x 1 vector that stores the list of l dense modes (where l=N−k−1),
  • 5) S: a b x k matrix that stores the coordinates/indices of the k non-candidate sparse modes in each of the b distinct buckets, such that each bucket stores one distinct sparse mode index tuple,
  • 6) t: a b×1 vector that stores the number of distinct candidate sparse mode indices corresponding to the non-zero values associated with each bucket,
  • 7) C: a nnz_s ×1 vector that stores the candidate sparse mode indices associated with non-zero values (where

${\mathrm{nnz}}_s=\sum _{i=1}^{b}t\left[i\right],$
and

$8)D\text{:}\{\begin{array}{c}\begin{array}{c}{\mathrm{annz}}_s\times M_{d1}\times M_{d2}\times \dots \times M_{\mathrm{dl}}\mathrm{array}({\mathrm{storing}}^{″}{{\mathrm{nnz}}_s}^{″}\\ \mathrm{dense}\mathrm{sub}\text{-}\mathrm{tensors},\mathrm{when}1>0\end{array}\\ {\mathrm{annz}}_s\times 1\mathrm{vector},\mathrm{when}l=0\end{array}.$

Recall that the exemplary tensor Y (described with reference to FIG. 2A), has three sparse modes, namely, modes 1, 2, and 4. Referring to FIG. 4C, from these sparse modes the mode 2 is selected as the candidate sparse mode “c.” Therefore, in the mode-specific format k=2. The number of distinct sparse mode index tuples, b, is 3, because indices associated with the candidate sparse mode (i.e., mode 2) are excluded. The number of dense modes is 1, because only mode 3 is determined to be dense, similarly as in the mode-generic format. Therefore, the vector d is {3}.

Two indices (1 and 2) of the candidate sparse mode (mode 2) are associated with the index tuple (1, 4) representing indices of sparse modes 1 and 4. One index (4) of the candidate sparse mode (mode 2) is associated with the index tuple (3, 3) representing indices of the sparse mode 1 and 4, and one index (3) of the candidate sparse mode (mode 2) is associated with the index tuple (2, 1) representing indices of the sparse mode 1 and 4. Thus, the vector t corresponding to the tensor Y includes three cells: {2, 1, 1}, and the corresponding vector C is {1, 2, 4, 3}. The first cell in the vector t indicates that the first two values in the vector C (i.e., indices 1 and 2) are associated with the sparse mode index tuple (1, 4). The second and third cells in the vector t, each of which has a value “1” further indicate that each of the remaining sparse mode index tuples corresponds to one value in the vector C.

In the mode-specific format, a sub-tensor [14, 7, 9] is associated with the first sparse mode index tuple (1, 4), and with the first element in the vector C, i.e., the index “1” of the candidate sparse mode (mode 2). A second sub-tensor [23, 38, 44] is also associated with the first sparse mode index tuple (1, 4), but with the second element in the vector C, i.e., the index “2” of the candidate sparse mode (mode 2). Another sub-tensor [49, 28, 35] is associated with a different sparse mode index tuple (2, 1), and with the fourth element in the vector C, i.e., the index “3” of the candidate sparse mode (mode 2). Because tensor Y has only one dense mode, the sub-tensors in D can be represented in the form of a vector or an array. The tensor Y, however, is illustrative only, and in general a sub-tensor associated with each sparse mode index tuple may have several dense modes. Any of these sub-tensors can be efficiently stored by using a mode-based order to store the sub-tensor elements. For example, a mode-generic and/or a mode-specific format can be used to store one or more sub-tensors.

With reference to FIG. 6, we present a novel high-level optimization that is designed to avoid unnecessary (and costly) computations and to efficiently reuse previously computed data in Tucker decomposition. An embodiment of the Tucker-HOOI algorithm depicted in FIG. 6 includes a common tensor operation, namely, a sequence of tensor matrix products along all but one modes of a tensor (all but one n-Mode matrix product sequence), which is described as follows:
Y=X x₁ A^(1)T x₂. . . x_n−1 A^(n-1)T x_n+1 A^(n+1)T . . . x_N A^(N)T
Each x_n in the computation indicates a n-Mode matrix product (multiplying a tensor with a matrix along the nth mode of the tensor). As it can be seen in FIG. 6, there is a sequence of N−1 n-Mode matrix product computations (N being the number of modes of the tensor) within each iteration of the “for” loop. Each product in the sequence produces an intermediate tensor that can be used to compute the next product in the sequence.

A major challenge is to reduce the storage of such intermediate tensors and increase the opportunity to reuse the intermediate data for memory scalability and performance improvement. Some of the intermediate tensors produced within one iteration of the for loop can be reused in subsequent iterations of the for loop. Exploiting such data reuse needs proper scheduling of the operations in the computation.

At iteration n=1, initial values of the matrices A^(2)T, . . . , and A^(N)T are used in the computation of “Y.” Also in iteration (n=1), an updated value of matrix A^(1)T is computed, as indicated at 602. The updated value of A^(1)T is used in iteration (n=2) as indicated by arrow 604. The computation in the iteration (n=2) can be described as:
Y=X x₁ A^(1)T x₃ A^(3)T. . . x_N A^(N)T
During this iteration, the matrix A^(2)T is updated as shown at 606, for subsequent use in iteration (n=3), as indicated by arrow 608. The computation in the iteration (n=3) can be described as:
Y=X x₁ A^(1)T x₂ A^(2)T x₄ A^(4)T . . . x_N A^(N)T
In the iteration (n=3), instead of re-computing the intermediate tensor (X x₁ A^(1)T), the value thereof, previously computed in the iteration (n=2), may be reused. Thus, the computation of Y in the iteration (n=3) may be expressed as:
Y=Z x₂ A^(2)T x₄ A^(4)T. . . x_N A^(N)T
where Z=(X x₁ A^(1)T), that was computed, as shown at 610, and stored in the iteration (n=2).

Further reuses of intermediate tensors are possible. For example, the computation in iteration (n=4) can be described as:
Y=X x₁ A^(1)T x₂ A^(2)T x₃ A^(3)T x₅ A^(5)T . . . x_N A^(N)T
In this computation, the intermediate tensor (X x₁ A^(1)T), that was computed as shown at 610 in the iteration (n=2) may be reused, or the intermediate tensor (X x₁ A^(1)T x₂ A^(2)T), that was computed as shown at 612 in the iteration (n=3) may be reused. In general, the computations in region 614 represent intermediate tensors that were computed in the immediately prior and/or other prior iterations, and that may be reused during the current iteration.

With reference to FIG. 7, we present a modified algorithm that performs the “all but one n-Mode matrix product sequence” rewritten in a way that performs the sequence of n-Mode matrix products in a reverse order compared to that in the algorithm depicted in FIG. 6. The modified all but one n-Mode matrix product sequence can be written as follows:
Y=X x_N A^(N)T x_N-1. . . x₁₊₁ A^(n+1)T x_n−1 A^(n-1)T . . . x₁ A^(1)T
The modified algorithm is equivalent to the original algorithm in terms of semantic correctness of the computation and the number of potential data reuses that can be exploited. The number of n-Mode matrix product computations that can be avoided by reusing previously computed intermediate tensor data is (N²/4)−(3N/2)+1, according to both the original and modified HOOI algorithms. In general in the modified algorithm, the computations in region 710 represent intermediate tensors that were computed in the immediately prior and/or other prior iterations, and that may be reused during the current iteration.

With reference to FIG. 8, we present an approach to potentially further increase the number of n-Mode matrix product computations that can be avoided by reusing previously computed intermediate tensor data. In this embodiment, the computation loop over different modes of the tensor is split into two halves, one half performing the original “n-Mode matrix product sequence” operation in each iteration and the other half performing the reverse “n-Mode matrix product sequence” in each iteration. According to this improvement, the number of reuses can be greater than or equal to (N²/4)−(3N/2)+((N−2)²/4)+1. It is achieved, in part, by reorganizing the computations of the original algorithm (presented in FIG. 6) taking advantage of the fact that for distinct modes in a sequence of n-Mode matrix products, the order of multiplication is irrelevant. Our approach does the following modification to the algorithm. The “for” loop goes over the modes of the tensor in a particular order and let us assume that the modes are numbered from 1 to N in that order. We split the “for” loop into two halves. In the first half, the “all but one n-Mode matrix product sequence” is performed in the decreasing (reverse) order of modes and in the second half, the “all but one n-Mode matrix product sequence” is performed in the increasing (original) order. By doing so, the number of reuses of the intermediate tensors produced is increased.

For example, intermediate results/tensors in region 810 may be reused in the first half of the iterations. This is an improvement over the algorithm depicted in FIG. 6, in which relatively fewer intermediate results are available for reuse during the first half of iterations, e.g., corresponding to iterations n=1 through n=4, if the number of iterations N is 7. The intermediate results/tensors in region 820 may be reused in the second half of the iterations. This is an improvement over the algorithm depicted in FIG. 7, in which relatively fewer intermediate results are available for reuse during the second half of iterations, e.g., corresponding to iterations n=5 through n=7, if the number of iterations N is 7. It should be understood that the total number of iterations N=7 is illustrative only. The number of modes, also 7, is also illustrative only. In general, the number of iterations can be fewer or more, e.g., 10, 15, 18, 25, etc., and the number of modes of the tensor is greater than two.

In some embodiments, we provide a memory-efficient technique to handle large-scale sparse tensor computations. Despite the popularity of Tucker decomposition, applying it on a large-scale sparse tensor is known to cause a memory blowup problem. Specifically, even if enough memory is available to store the large input sparse tensor and the core output dense tensor, memory overflow occurs frequently in Tucker computation due to the need to store larger intermediate results.

The computation of all but one n-Mode matrix product sequence introduces the possibility of memory blowup. Let us assume that the input tensor size is I₁ x . . . x I_N and the output tensor size is R₁ x . . . x R_N. The sizes I₁ . . . I_N are typically very large (e.g., on the order of thousands, millions, tens of millions, etc.) and the sizes R₁ . . . R_N are smaller (e.g., on the order of tens, hundreds, thousands, etc.). Many conventional sparse tensor dense matrix product implementations typically store the n-Mode matrix product result in a dense tensor. As such, in the all but one sequence computation (for any mode other than one), the result of the first n-Mode matrix product may to be stored in a large dense tensor of size R₁×I₂×. . . ×I_N. The need to store even one or several of such intermediate results can lead to memory overflow resulting in the intermediate memory blowup problem.

Many of the intermediate results, however, do not produce a dense tensor. An intermediate tensor resulting from an “all but one n-Mode matrix product sequence” is typically a semi-sparse tensor. In other words, these product sequences often produce completely sparse tensors or sparse tensors that have dense sub-tensors or one or more dense modes. Various embodiments that use the novel sparse formats (both mode-generic and mode-specific) described above can efficiently store both completely sparse tensors and tensors that have dense sub-tensors and/or a dense mode. Taking advantage of this typical property of the “all but one n-Mode matrix product sequence,” in one embodiment, the intermediate memory blowup problem is avoided or mitigated by using a mode-generic format for storing one or more of the intermediate results. In another embodiment, a mode-specific format is used to store one or more of the intermediate results, and in yet another embodiment a mode-generic format is used to store one or more intermediate results and a mode-specific format is used to store one or more other intermediate results.

The mode-generic format is beneficial if the intermediate tensor includes a dense mode, and the mode-specific format is beneficial if the intermediate tensor lacks a dense mode. Both formats can be used to store any type of tensor, however. In general embodiments that use mode-generic and/or mode-specific sparse formats to store one or more intermediate tensors can reduce the overall memory requirement. This typically: (1) reduces the possibility of memory blowup, and (2) provides opportunity to store more intermediate tensors and achieve more data reuse.

With reference to FIG. 9, another solution is described to address the memory blowup problem. Some embodiments provide this other solution independently, while in some embodiments, the use of this other solution is combined with the previous solution, i.e., the use of mode-generic and/or mode-specific formats to store one or more of the intermediate tensors.

In general, there are N−2 intermediate tensors associated with each iteration of a N-th order tensor Tucker decomposition. Typically the size of the first intermediate tensor 902 (resulting from the first n-Mode matrix product 904 in the sequence) is larger than that of the second intermediate tensor 906 (resulting from the second n-Mode matrix product 908 in the sequence) and so on. It should be understood, however, that in some instances, the size of the intermediate tensors does not decrease with the sequence of products, and embodiments in which the size may increase and/or decrease in a random order are within the scope of the present invention.

In one embodiment, the input tensor X and the output tensor, produced during the last iteration, fit in the memory. The first intermediate tensor 902 does not fit in the available memory if stored in the conventional dense format. In some embodiments, the first intermediate tensor does not fit in the memory even if it is stored in the conventional coordinate format, but the likelihood that the tensor 902 would fit in the memory can increase significantly if a mode-generic or a mode-specific format is used to store the first intermediate tensor 902. Similarly, the intermediate tensors 908 and other intermediate tensors may or may not fit in the available memory depending on the formats used to store each of these intermediate tensors. Whether an intermediate tensor would fit in memory can also depend on which other tensors have already been stored or are designated to be stored in the memory.

It is possible to compute the entire all but one n-Mode matrix product sequence without storing any of the intermediate tensors. However such a computation induces a huge overhead in terms of repeated computation of various intermediate values that would have been otherwise computed only once, if they were stored and used for computing the next product in the sequence. As such, a tradeoff exists between performing redundant computations and using more memory for storing intermediate results.

Some techniques to perform the above-described tradeoff divide the modes of the tensor as element-wise and standard. (See, e.g., T. G. Kolda and J. Sun, “Scalable Tensor Decompositions for Multiaspect Data Mining,” in ICDM 2008: Proceedings of the 8th IEEE International Conference on Data Mining, December 2008, pp. 363-372). These tradeoffs are based on a reduction ratio based on sizes of the operand and resulting tensors of the product sequence. Importantly, these tradeoffs are limited to product sequence within a single iteration of tensor computations (e.g., one iteration of the Tucker decomposition).

In one embodiment, we order the modes of the tensor based on a degree of data reuse of the intermediate tensor resulting after a single n-Mode matrix product along the mode and/or after a sequence n-Mode matrix products along less than N−1 modes, N being the number of modes of the tensor. Let L be the list of modes in the order they are accessed in the original HOOI method, as depicted in FIG. 6. In one embodiment employing the modified HOOI method described with reference to FIG. 8, in selecting element-wise modes for the first half of the iterations, we choose the reverse order of L and choose minimal number of modes in that order that guarantees memory availability, as element-wise. The memory availability can be guaranteed by computing the total storage requirement for the intermediate tensors to be stored, and by comparing that requirement with a preselected threshold. The preselected threshold can be the size of total memory accessible to the processor. When the element-wise modes are identified, the remaining modes are designated as “standard,” i.e., for single n-Mode matrix products or a sequence of less than N−1 matrix products associated with the designated standard modes, the intermediate results are stored in memory for subsequent reuse thereof. For the second half computation, the same process is repeated but with the original order of L.

When a set of modes is selected as element-wise, we perform the sequence of n-Mode matrix products along the element-wise modes at once (performing redundant computations and without storing the intermediate tensors) and store one intermediate tensor at the end of the “element-wise” computation. This intermediate tensor has the same number of modes as the input tensor but reduced in size along the element-wise modes. The intermediate tensor stored at the end of element-wise computation and/or other intermediate tensors stored after the standard-mode computations are available for reuse during a subsequent iteration. Thus, this approach can ensure memory availability to store intermediate tensors and also does not perturb the benefit of data reuse optimization illustrated with reference to FIGS. 6-8. As such, various embodiments employing one or more of these techniques not only address memory scalability but also improve computation time by reducing redundant computations through improved data reuse.

The selection of standard and element-wise modes can be based on, additionally or in the alternative, a degree of reuse of the intermediate tensor. For example, consider:
Y=X×A1 ×A2 ×A4.
This can be computed as:
y1=X×A1; y2=y1 ×A2; and Y=y2 ×A4, or as  (1)
y2=X×A1 ×A2; and Y=y2 ×A4, or as  (2)
z1=X×A2; y2=z1 ×A1; and Y=y2 ×A4, or as  (3)
z2=X×A2 ×A4; and Y=z2 ×A1.  (4)
Other combinations are also possible.

The reduction ratio based method selects the best combination from the combinations (1)-(4) (and from other possible combinations) by selecting the ordering or sequence that is most memory efficient. For example, if the combination (1) is selected, intermediate tensors y1 and y2 would be stored and reused, and resulting tensor Y is also stored. In the alternative, if the combination (2) is selected, only the intermediate tensor y2 is stored and reused, and resulting tensor Y is also stored. So the combination (2) has less reuse and more duplicate computations relative to the combination (1), but less storage requirement relative to the combination (1).

In the selection technique based on the degree of reuse, the intermediate tensor or tensors that are to be computed and stored are identified based on, at least in part, (a) the required storage, and (b) the degree of reuse of those tensors in the next iterations. For example, even if the combination (2) has less storage requirement relative to the combination (1), the combination (1) may be desired (if feasible), if y1 has a greater degree of reuse in subsequent iterations compared to y2. Comparing the combinations (1) and (4), the combination (4) may be selected over the combination (1) if memory requirements and degree of reuse of z2 (considered together) outweigh the same characteristics of y1 and y2.

In general, references to operations such as multiply, add, subtract, and values such as zero, and non-zero, for the elements of tensors may be understood to refer to appropriate implementations where these operators and elements correspond to operators, elements, and identity elements generally over algebraic rings, semi-rings, or abelian rings, or their approximations, for example, algebras over integers, rationals, reals, complex numbers, digital floating point representations, and including min-plus algebras over numbers and symbolic operators and strings. It should also be understood that in illustrating the features and benefits of various embodiments, Tucker decomposition is used only as an example of an iterative tensor computation. Various embodiments described herein can be used to improve performance and/or memory usage of several types of tensor operations such as those involving matrix operations on a tensor.

It is clear that there are many ways to configure the device and/or system components, interfaces, communication links, and methods described herein. The disclosed methods, devices, and systems can be deployed on convenient processor platforms, including network servers, personal and portable computers, and/or other processing platforms. Other platforms can be contemplated as processing capabilities improve, including personal digital assistants, computerized watches, cellular phones and/or other portable devices. The disclosed methods and systems can be integrated with known network management systems and methods. The disclosed methods and systems can operate as an SNMP agent, and can be configured with the IP address of a remote machine running a conformant management platform. Therefore, the scope of the disclosed methods and systems are not limited by the examples given herein, but can include the full scope of the claims and their legal equivalents.

The methods, devices, and systems described herein are not limited to a particular hardware or software configuration, and may find applicability in many computing or processing environments. The methods, devices, and systems can be implemented in hardware or software, or a combination of hardware and software. The methods, devices, and systems can be implemented in one or more computer programs, where a computer program can be understood to include one or more processor executable instructions. The computer program(s) can execute on one or more programmable processing elements or machines, and can be stored on one or more storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), one or more input devices, and/or one or more output devices. The processing elements/machines thus can access one or more input devices to obtain input data, and can access one or more output devices to communicate output data. The input and/or output devices can include one or more of the following: Random Access Memory (RAM), Redundant Array of Independent Disks (RAID), floppy drive, CD, DVD, magnetic disk, internal hard drive, external hard drive, memory stick, or other storage device capable of being accessed by a processing element as provided herein, where such aforementioned examples are not exhaustive, and are for illustration and not limitation.

The computer program(s) can be implemented using one or more high level procedural or object-oriented programming languages to communicate with a computer system; however, the program(s) can be implemented in assembly or machine language, if desired. The language can be compiled or interpreted.

As provided herein, the processor(s) and/or processing elements can thus be embedded in one or more devices that can be operated independently or together in a networked environment, where the network can include, for example, a Local Area Network (LAN), wide area network (WAN), and/or can include an intranet and/or the Internet and/or another network. The network(s) can be wired or wireless or a combination thereof and can use one or more communications protocols to facilitate communications between the different processors/processing elements. The processors can be configured for distributed processing and can utilize, in some embodiments, a client-server model as needed. Accordingly, the methods, devices, and systems can utilize multiple processors and/or processor devices, and the processor/processing element instructions can be divided amongst such single or multiple processor/devices/processing elements.

The device(s) or computer systems that integrate with the processor(s)/processing element(s) can include, for example, a personal computer(s), workstation (e.g., Dell, HP), personal digital assistant (PDA), handheld device such as cellular telephone, laptop, handheld, or another device capable of being integrated with a processor(s) that can operate as provided herein. Accordingly, the devices provided herein are not exhaustive and are provided for illustration and not limitation.

References to “a processor”, or “a processing element,” “the processor,” and “the processing element” can be understood to include one or more microprocessors that can communicate in a stand-alone and/or a distributed environment(s), and can thus can be configured to communicate via wired or wireless communications with other processors, where such one or more processor can be configured to operate on one or more processor/processing elements-controlled devices that can be similar or different devices. Use of such “microprocessor,” “processor,” or “processing element” terminology can thus also be understood to include a central processing unit, an arithmetic logic unit, an application-specific integrated circuit (IC), and/or a task engine, with such examples provided for illustration and not limitation.

Furthermore, references to memory, unless otherwise specified, can include one or more processor-readable and accessible memory elements and/or components that can be internal to the processor-controlled device, external to the processor-controlled device, and/or can be accessed via a wired or wireless network using a variety of communications protocols, and unless otherwise specified, can be arranged to include a combination of external and internal memory devices, where such memory can be contiguous and/or partitioned based on the application. For example, the memory can be a flash drive, a computer disc, CD/DVD, distributed memory, etc. References to structures include links, queues, graphs, trees, and such structures are provided for illustration and not limitation. References herein to instructions or executable instructions, in accordance with the above, can be understood to include programmable hardware.

Although the methods and systems have been described relative to specific embodiments thereof, they are not so limited. As such, many modifications and variations may become apparent in light of the above teachings. Many additional changes in the details, materials, and arrangement of parts, herein described and illustrated, can be made by those skilled in the art. Accordingly, it will be understood that the methods, devices, and systems provided herein are not to be limited to the embodiments disclosed herein, can include practices otherwise than specifically described, and are to be interpreted as broadly as allowed under the law.

Claims

1. A method for incorporating data reuse in a tensor transform, the tensor having a plurality of modes, the number of modes being N, N being at least equal to three, the tensor transform comprising a plurality of iterations, the method comprising:

performing by the processor a first iteration comprising a first sequence of n-mode matrix product operations on the tensor to obtain a first intermediate result, each n-mode matrix product comprising a product of a matrix and the tensor along a respective mode identified by a mode index denoted n, wherein 1≤n≤1V, the first intermediate result comprising a first intermediate-tensor;

at least one of: (i) selecting an order of modes for the first sequence by identifying a minimum number of element-wise modes, wherein the first sequence comprises all n-mode matrix product operations corresponding to all of the identified element-wise modes, to guarantee memory availability for all intermediate tensors resulting from the first iteration; and (ii) selecting a tensor format from one of mode-generic format and mode-specific format, wherein the selected format avoids memory blow up in storing intermediate results;

storing by the processor the first intermediate tensor in memory;

performing by the processor a second iteration representing a second sequence of n-mode matrix product operations using the first intermediate tensor accessed from the memory; and

avoiding an n-mode matrix product operation that is part of both the first and second sequences, and is represented by the first intermediate tensor.

2. The method of claim 1, wherein the second operation uses an operand computed during the first iteration.

3. The method of claim 2, wherein the operand comprises a matrix.

4. The method of claim 1, wherein each iteration in the plurality of iterations comprises a sequence of operations, the method further comprising:

ordering by the processor the sequence of operations in each iteration according to one of increasing order and decreasing order of modes of the tensor.

5. The method of claim 1, wherein each iteration in the plurality of iterations comprises a sequence of operations, the method further comprising:

ordering by the processor the sequence of operations in each iteration in a first set of iterations in the plurality of iterations according to increasing order of modes of the tensor; and

ordering by the processor the sequence of operations in each iteration in a second set of iterations in the plurality of iterations according to decreasing order of modes of the tensor.

6. The method of claim 1, wherein:

storing the first intermediate result comprising the first intermediate tensor comprises storing in the memory elements of the first intermediate tensor in a mode-based order for improving locality of references when the elements of the first intermediate tensor are accessed during an operation on the first intermediate tensor.

7. The method of claim 6, wherein:

storing the elements of the first intermediate tensor in the mode-based order comprises storing in the memory:

a first data structure comprising a plurality of sparse mode index tuples associated with the first intermediate tensor; and

a second data structure comprising a plurality of significant values in the first intermediate tensor, each significant value corresponding to a sparse mode index tuple in the first data structure.

8. The method of claim 1, further comprising:

identifying by the processor a set of reusable tensors to be computed during a plurality of iterations;

evaluating by the processor, for each reusable tensor in the set, a memory storage requirement; and

selecting by the processor, a subset of reusable tensors from the set such that a total memory storage memory requirement for all of the reusable tensors in the subset does not exceed a preselected threshold.

9. The method of claim 8, wherein the set of reusable tensors comprises all reusable tensors to be computed during the plurality of iterations.

10. The method of claim 8, wherein:

the evaluation comprises, for each reusable tensor in the set, determining a degree of reuse of the reusable tensor; and

the selection is further based on, at least in part, the degree of reuse of each reusable tensor in the set.

11. The method of claim 8, wherein at least one iteration in the plurality of iterations comprises a sequence of operations, each operation corresponding to a mode of the tensor, the method further comprising:

performing a first group of operations in element-wise mode; and

performing a second mode of operation in standard mode.

12. The method of claim 8, wherein:

evaluating the memory storage requirement for each reusable tensor comprises determining a memory size required to store the reusable tensor by storing in the memory elements of the reusable tensor in a mode-based order for improving locality of references when the elements of the reusable tensor are accessed during an operation on the reusable tensor.

13. A system for incorporating data reuse in a tensor transform, the tensor having a plurality of modes, the number of modes being N, N being at least equal to three, the tensor transform comprising a plurality of iterations, the system comprising:

a memory;

a processor in electronic communication with the memory, wherein the processor is configured to:

perform a first iteration comprising a first sequence of n-mode matrix product operations on the tensor to obtain a first intermediate result, each n-mode matrix product comprising a product of a matrix and the tensor along a respective mode identified by a mode index denoted n, wherein 1≤n≤1V, the first intermediate result comprising a first intermediate-tensor;

at least one of: (i) select an order of modes for the first sequence by identifying a minimum number of element-wise modes, wherein the first sequence comprises all n-mode matrix product operations corresponding to all of the identified element-wise modes, to guarantee memory availability for all intermediate tensors resulting from the first iteration; and (ii) select a tensor format from one of mode-generic format and mode-specific format, wherein the selected format avoids memory blow up in storing intermediate results;

store the first intermediate tensor in memory;

perform a second iteration representing a second sequence of n-mode matrix product operations using the first intermediate tensor accessed from the memory; and

avoid an n-mode matrix product operation that is part of both the first and second sequences, and is represented by the first intermediate tensor.

14. The system of claim 13, wherein the second operation uses an operand computed during the first iteration.

15. The system of claim 14, wherein the operand comprises a matrix.

16. The system of claim 13, wherein each iteration in the plurality of iterations comprises a sequence of operations, and the processor is further configured to:

order the sequence of operations in each iteration according to one of increasing order and decreasing order of modes of the tensor.

17. The system of claim 13, wherein each iteration in the plurality of iterations comprises a sequence of operations, and the processor is further configured to:

order the sequence of operations in each iteration in a first set of iterations in the plurality of iterations according to increasing order of modes of the tensor; and

order the sequence of operations in each iteration in a second set of iterations in the plurality of iterations according to decreasing order of modes of the tensor.

18. The system of claim 13, wherein the processor is further configured to:

store in the memory elements of the first intermediate tensor in a mode-based order for improving locality of references when the elements of the first intermediate tensor are accessed during an operation on the first intermediate tensor.

19. The system of claim 18, wherein to store the elements of the first intermediate tensor in the mode-based order, the processor is further configured to store in the memory:

a first data structure comprising a plurality of sparse mode index tuples associated with the first intermediate tensor; and

a second data structure comprising a plurality of significant values in the first intermediate tensor, each significant value corresponding to a sparse mode index tuple in the first data structure.

20. The system of claim 13, wherein the processor is further configured to:

identify a set of reusable tensors to be computed during a plurality of iterations;

evaluate, for each reusable tensor in the set, a memory storage requirement; and

select a subset of reusable tensors from the set such that a total memory storage memory requirement for all of the reusable tensors in the subset does not exceed a preselected threshold.

21. The system of claim 20, wherein the set of reusable tensors comprises all reusable tensors to be computed during the plurality of iterations.

22. The system of claim 20, wherein:

to evaluate the memory storage requirement for each reusable tensor in the set, the processor is further configured to determine a degree of reuse of the reusable tensor; and

the selection is further based on, at least in part, the degree of reuse of each reusable tensor in the set.

23. The system of claim 20, wherein at least one iteration in the plurality of iterations comprises a sequence of operations, each operation corresponding to a mode of the tensor, and the processor is further configured to:

perform a first group of operations in element-wise mode; and

perform a second mode of operation in standard mode.

24. The system of claim 20, wherein:

to evaluate the memory storage requirement for each reusable tensor, the processor is further configured to determine a memory size required to store the reusable tensor by storing in the memory elements of the reusable tensor in a mode-based order for improving locality of references when the elements of the reusable tensor are accessed during an operation on the reusable tensor.

25. An article of manufacture, comprising a non-transitory machine-readable medium storing instructions that, when executed by a machine comprising a memory and a processor in electronic communication with the memory, configure the processor, for incorporating data reuse in a tensor transform, the tensor having a plurality of modes, the number of modes being N, N being at least equal to three, the tensor transform comprising a plurality of iterations, to:

perform a first iteration comprising a first sequence of n-mode matrix product operations on the tensor to obtain a first intermediate result, each n-mode matrix product comprising a product of a matrix and the tensor along a respective mode identified by a mode index denoted n, wherein 1≤n≤N, the first intermediate result comprising a first intermediate-tensor;

at least one of: (i) select an order of modes for the first sequence by identifying a minimum number of element-wise modes, wherein the first sequence comprises all n-mode matrix product operations corresponding to all of the identified element-wise modes, to guarantee memory availability for all intermediate tensors resulting from the first iteration; and (ii) select a tensor format from one of mode-generic format and mode-specific format, wherein the selected format avoids memory blow up in storing intermediate results;

store the first intermediate tensor in memory;

perform a second iteration representing a second sequence of n-mode matrix product operations using the first intermediate tensor accessed from the memory; and

avoid an n-mode matrix product operation that is part of both the first and second sequences, and is represented by the first intermediate tensor.

26. The article of manufacture of claim 25, wherein the second operation uses an operand computed during the first iteration.

27. The article of manufacture of claim 26, wherein the operand comprises a matrix.

28. The article of manufacture of claim 25, wherein each iteration in the plurality of iterations comprises a sequence of operations, and the instructions further configure the processor to:

order the sequence of operations in each iteration according to one of increasing order and decreasing order of modes of the tensor.

29. The article of manufacture of claim 25, wherein each iteration in the plurality of iterations comprises a sequence of operations, and the instructions further configure the processor to:

order the sequence of operations in each iteration in a first set of iterations in the plurality of iterations according to increasing order of modes of the tensor; and

order the sequence of operations in each iteration in a second set of iterations in the plurality of iterations according to decreasing order of modes of the tensor.

30. The article of manufacture of claim 25, wherein the instructions further configure the processor to:

store in the memory elements of the first intermediate tensor in a mode-based order for improving locality of references when the elements of the first intermediate tensor are accessed during an operation on the first intermediate tensor.

31. The article of manufacture of claim 30, wherein to store the elements of the first intermediate tensor in the mode-based order, the instructions further configure the processor to store in the memory:

a first data structure comprising a plurality of sparse mode index tuples associated with the first intermediate tensor; and

a second data structure comprising a plurality of significant values in the first intermediate tensor, each significant value corresponding to a sparse mode index tuple in the first data structure.

32. The article of manufacture of claim 25, wherein the instructions further configure the processor to:

identify a set of reusable tensors to be computed during a plurality of iterations;

evaluate, for each reusable tensor in the set, a memory storage requirement; and

select a subset of reusable tensors from the set such that a total memory storage memory requirement for all of the reusable tensors in the subset does not exceed a preselected threshold.

33. The article of manufacture of claim 32, wherein the set of reusable tensors comprises all reusable tensors to be computed during the plurality of iterations.

34. The article of manufacture of claim 32, wherein:

to evaluate the memory storage requirement for each reusable tensor in the set, the instructions further configure the processor to determine a degree of reuse of the reusable tensor; and

the selection is further based on, at least in part, the degree of reuse of each reusable tensor in the set.

35. The article of manufacture of claim 32, wherein at least one iteration in the plurality of iterations comprises a sequence of operations, each operation corresponding to a mode of the tensor, and the instructions further configure the processor to:

perform a first group of operations in element-wise mode; and

perform a second mode of operation in standard mode.

36. The article of manufacture of claim 32, wherein:

to evaluate the memory storage requirement for each reusable tensor, the instructions further configure the processor to determine a memory size required to store the reusable tensor by storing in the memory elements of the reusable tensor in a mode-based order for improving locality of references when the elements of the reusable tensor are accessed during an operation on the reusable tensor.