A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.
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1. A method for manufacturing a printed circuit board (PCB), comprising the steps of:
providing a carrier substrate that includes a carrier layer, a release layer, and an aluminum layer;
forming a first conductive layer on the carrier substrate;
forming an insulating layer and a second conductive layer on the first conductive layer;
forming contact plugs that penetrate into the insulating layer and that electrically connect the first conductive layer and the second conductive layer;
separating the carrier layer and the aluminum layer from each other by separating the release layer into two sublayers, wherein a first sublayer of the release layer remains with the carrier layer and a second sublayer of the release layer remains with the aluminum layer,
removing the separated carrier layer and the first sublayer of the release layer;
forming an aluminum pattern, a first conductive pattern, and a second conductive pattern by respectively patterning the aluminum layer, the first conductive layer, and the second conductive layer, and removing the second sublayer of the release layer from the aluminum layer,
forming a first solder resist layer on an upper surface of the insulating layer and a second solder resist layer on a lower surface of the insulating layer opposite to the upper surface, wherein the first solder resist layer includes at least one opening that exposes a part of the first conductive pattern and a part of the aluminum pattern; and
forming a first passivation layer on an exposed surface of the first conductive pattern and a second passivation layer on an exposed surface of the second conductive pattern by an organic solderability preservative (OSP) surface treatment.
2. The method of
the carrier substrate further includes a barrier layer and a seed layer,
the first conductive layer is formed by plating using the seed layer as a seed, and
a barrier pattern is formed by patterning the barrier layer, and
the at least one opening exposes a part of the barrier pattern.
3. The method of
forming a preparatory first solder resist layer on an upper surface of the insulating layer that covers both upper and side surfaces of the aluminum pattern and sides of the first conductive pattern, and
removing a part of the preparatory first solder resist layer to form the at least one opening.
4. The method of
forming an oxide layer on an exposed surface of the aluminum pattern,
wherein the oxide layer forms as the aluminum pattern contacts air.
5. The method of
forming a first insulating layer and a third conductive pattern on the first conductive layer,
forming first contact plugs that penetrates into the first insulating layer and that electrically connect the first conductive layer and the third conductive pattern;
forming a second insulating layer that covers the third conductive pattern, wherein the second conductive layer is formed on a portion of a lower surface of the second insulating layer; and
forming second contact plugs that penetrate into the second insulating layer and that electrically connect the third conductive pattern and the second conductive layer.
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This application is a divisional of U.S. application Ser. No. 15/402,876, filed on Jan. 10, 2017 in the U.S. Patent and Trademark Office, which claims priority under 35 USC § 119 from, and the benefit of, Korean Patent Application No. 10-2016-0049384, filed on Apr. 22, 2016 in the Korean Intellectual Property Office, the contents of both of which are herein incorporated by reference in their entireties.
Embodiments of the inventive concept are directed to a printed circuit board (PCB) and a semiconductor package, and more particularly, to a PCB that has a surface treatment performed on pads thereof using aluminum and a semiconductor package.
As electronic components have become large-scale, various surface treatment technologies of a printed circuit board (PCB) have been developed. A metal plating technology is used to treat a surface of a PCB. In addition, due to consumer demand, electronic systems now have high-performance functions and smaller sizes, which leads to an increase in the number of connection terminals connected to a PCB included in an electronic system and a reduction in intervals and sizes of the connection terminals. A total area of the PCB can be reduced by reducing the intervals and sizes of the connection terminals. Accordingly, processes, such as tenting, a semi additive process (SAP), and a modified semi-additive process (MSAP), have been studied.
Embodiments of the inventive concept can provide a printed circuit board (PCB) that reduces process costs and improves bonding process reliability.
Embodiments of the inventive concept can also provide a semiconductor package that reduces process costs and improves bonding process reliability.
According to an embodiment of the inventive concept, there is provided a printed circuit board (PCB) that includes an insulating layer that includes an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.
According to another embodiment of the inventive concept, there is provided a semiconductor package that includes a package substrate; a semiconductor chip on the package substrate; and a bonding wire that connects the package substrate and the semiconductor chip, wherein the package substrate includes: an insulating layer; a first wiring pattern on an upper surface of the insulating layer and that includes copper, a second wiring pattern on the first wiring pattern and that includes a material different from that of the first wiring pattern; and an organic passivation layer on sides of the first wiring pattern that prevents diffusion into the first wiring pattern.
According to another embodiment of the inventive concept, there is provided a method for manufacturing a printed circuit board (PCB) that includes providing a carrier substrate that includes a carrier layer, a release layer, and an aluminum layer; forming a first conductive layer on the carrier substrate; forming a insulating layer and a second conductive layer on the first conductive layer; forming contact plugs that penetrate into the insulating layer and that electrically connect the first conductive layer and the second conductive layer, separating the carrier layer and the aluminum layer from each other by separating the release layer into two sublayers, wherein a first sublayer remains with the carrier layer and a second sublayer remains with the aluminum layer, removing the separated carrier layer and the first sublayer of the release layer; forming an aluminum pattern, a first conductive pattern, and a second conductive pattern by respectively patterning the aluminum layer the first conductive layer, and the second conductive layer, and removing the second sublayer of the release layer from the aluminum layer; forming a first solder resist layer and a second solder resist layer respectively on an upper surface of the insulating layer and a lower surface of the insulating layer opposite to the upper surface, wherein the first solder resist layer includes at least one opening that exposes a part of the first conductive pattern and a part of the aluminum pattern; and forming a first passivation layer and a second passivation layer on respective exposed surfaces of the first conductive pattern and the second conductive pattern by an organic solderability preservative (OSP) surface treatment.
Referring to
According to an embodiment, the insulating layer 10 includes at least one material selected from phenol resin, epoxy resin, and polyimide. For example, the insulating layer 10 may include at least one material selected from frame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer. In some embodiments, the insulating layer 10 includes, for example, polyester (PET), polyester telephthalate, fluorinated ethylene propylene (FEP), resin-coated paper, liquid polyimide resin, a polyethylene naphthalate (PEN) film, etc.
According to an embodiment, the first conductive pattern 100 is formed on the upper surface of the insulating layer 10. The second conductive pattern 200 is formed on the lower surface of the insulating layer 10. To electrically connect the first conductive pattern 100 and the second conductive pattern 200, a contact plug 150 that penetrates into the insulating layer 10 is formed. A plurality of first patterns 100 and a plurality of second patterns 200 can be configured. Accordingly, a plurality of contact plugs 150 can also be formed. The first conductive pattern 100 may include at least one of copper (Cu), nickel (Ni), aluminum (Al), gold (Au), platinum (Pt), and silver (Ag). For example, the first conductive pattern 100 may include copper. The second conductive pattern 200 may include a material similar to the material of the first conductive pattern 100, but embodiments are not limited thereto. The second conductive pattern 200 may include a material different from the material of the first conductive pattern 100.
According to an embodiment, the aluminum pattern 110 is formed to cover at least a part of an upper surface of the first conductive pattern 100. The aluminum pattern 110 can prevent the first conductive pattern 100 from being exposed. In this regard, the upper surface of the first conductive pattern 100 is higher than an upper surface of the insulating layer 10. Thus, the aluminum pattern 110 has a shape that protrudes from the insulating layer 10. A plurality of aluminum patterns 110 may also be configured, like the first conductive pattern 100. Aluminum has good electrical conductivity and a low price, and thus can replace gold, silver, etc. that are conventionally used to treat surfaces of pads formed on a substrate. As a result, manufacturing costs of the PCB 1a can be reduced.
According to an embodiment, a thickness T1 of the aluminum pattern 110 in a direction perpendicular to the upper surface of the insulating layer 10 is less than a thickness T2 of the first conductive pattern 100 in a direction perpendicular to the upper surface of the insulating layer 10. That is, a thin aluminum pattern 110 can be formed on the upper surface of the first conductive pattern 100. However, the thickness T1 of the aluminum pattern 110 is relatively exaggerated for emphasis in
According to an embodiment, the first passivation layer 120 covers at least a part of the sides of the first conductive pattern 100. The first passivation layer 120 can prevent diffusion into the first conductive pattern 100. The first passivation layer 120 includes a material formed through an organic solderability preservative (OSP) surface treatment. For example, when the first conductive pattern 100 includes copper, the first passivation layer 120 may include an organic compound such as benzotriazole, imidazole, benzimidazole, etc., that can attach to a copper surface and chemically combine with copper atoms. In particular, when the first conductive pattern 100 includes copper, the first passivation layer 120 on which the OSP surface treatment is performed can prevent an unwanted oxidation reaction from occurring in a surface of the first conductive pattern 100 or prevent the surface from being damaged.
According to an embodiment, the first passivation layer 120 is relatively thin 120 on the sides of the first conductive pattern 100. A thickness T3 of the first passivation layer 120 on the sides of the first conductive pattern 100 is equal to or less than 0.5 μm. Thus, spaces between the first conductive patterns 100 increase in size, and process reliability increases during wire bonding of the PCB 1a.
According to an embodiment, the first solder resist layer 130 is formed on the insulating layer 10 and includes an opening 130a. An upper surface of a portion of the aluminum pattern 110 is exposed by the opening 130a of the first solder resist layer 130. The second solder resist layer 230 is formed on a lower surface of the insulating layer 10. In this regard, the second solder resist layer 230 is formed to cover sides of the second conductive pattern 200. The first solder resist layer 130 and the second solder resist layer 230 are insulating layers and may include a polyimide film, a polyester film, a flexible solder mask, a photoimageable coverlay (PIC), a photoimageable solder resist, etc. The first solder resist layer 130 can protect the first conductive pattern 100 and can prevent a bridge phenomenon from occurring between adjacent second conductive patterns 200.
According to an embodiment, the second passivation layer 220 is additionally formed in a lower surface of the second conductive pattern 200 that does not contact the second solder resist layer 230. The second passivation layer 220 covers at least a portion of the lower surface of the second conductive pattern 200. The second passivation layer 220 includes the same material as the first passivation layer 120 through the same process and can perform the same function as the first passivation layer 120.
According to an embodiment, the PCB 1a described above has a surface treatment performed on pads thereof using aluminum, thereby reducing process costs. The PCB 1a also has larger spaces between pads formed thereon, thereby increasing reliability of an electrical connection and increasing reliability of a bonding process.
According to an embodiment, referring to
According to an embodiment, the release layer 30 includes an alloy and an organic compound. The release layer 30 can also include an adhesive layer and may be formed as a non-conductive film (NCF), an anisotropic conductive film (ACF), an instant adhesive, a thermosetting adhesive, a laser curable adhesive, an ultrasound curable adhesive, etc. The adhesive layer may be formed by, for example, spin coating, painting, spraying, etc.
The aluminum layer 40 may be formed through chemical deposition, metal sputtering, electroplating and electroless metal plating processes. The release layer 30 and the aluminum layer 40 are shown as being formed on one surface of the carrier layer 20 in
Referring to
Referring to
Referring to
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Referring to
Referring to
The preparatory first solder resist layer 130b and the second solder resist layer 230 may be formed by, for example, directly coating the insulating layer 10 with thermosetting ink using silk screen printing or inkjet printing and thermally hardening the coated thermosetting ink. Alternatively, the preparatory first solder resist layer 130b and the second solder resist layer 230 may be formed by, for example, entirely coating the insulating layer 10 with a photoimageable solder resist using screen printing or spray coating. The preparatory first solder resist layer 130b and the second solder resist layer 230 may be formed by, for example, a laminating method that adheres a polyimide film or a polyester film onto the insulating layer 10. Materials of the first solder resist layer 130 and the second solder resist layer 230 are described with reference to
Referring to
According to an embodiment, the first passivation layer 120 and the second passivation layer 220 are respectively formed on exposed surfaces of the first conductive pattern 100 and the second conductive pattern 200. Thus, the first passivation layer 120 is formed on sides of portions of the first conductive pattern 100, and the second passivation layer 220 is formed on lower surfaces of at least portions of the second conductive pattern 200. The first passivation layer 120 and the second passivation layer 220 are formed through an OSP surface treatment. The first passivation layer 120 and the second passivation layer 220 may be simultaneously formed, but embodiments are not limited thereto.
Referring to
According to an embodiment, barrier pattern 140 can prevent a reduction in electrical conductivity due to diffusion of a conductive material from the first conductive pattern 100 to the aluminum pattern 110. The barrier pattern 140 may include, for example, nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), gold (Au), silver (Ag), and tungsten (W). For example, the barrier pattern 140 may be a layer that includes nickel (Ni).
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
According to an embodiment, the first solder resist layer 130 and the second solder resist layer 230 are respectively formed on an upper surface of the insulating layer 10 and a lower surface of the insulating layer 10 opposite to the upper surface. The first solder resist layer 130 covers at least a part of upper surface and sides of the aluminum pattern 110, sides of the barrier pattern 140, and sides of the first conductive pattern 100. The second solder resist layer 230 covers sides of the second conductive pattern 200.
According to an embodiment, the first solder resist layer 130 includes at least one opening 130a that exposes a part of the first conductive pattern 100, a part of the barrier pattern 140, and a part of the aluminum pattern 110. The exposed parts of the first conductive pattern 100, the barrier pattern 140, and the aluminum pattern 110 can function as pads that contact a bonding wire that electrically connects the PCB and a semiconductor chip or a semiconductor package that is mounted on the PCB.
According to an embodiment, the first passivation layer 120 and the second passivation layer 220 are respectively formed on exposed surfaces of the first conductive pattern 100 and the second conductive pattern 200. Thus, the first passivation layer 120 is formed on sides of portions of the first conductive pattern 100, and the second passivation layer 220 is formed on lower surfaces of at least portions of the second conductive pattern 200. The first passivation layer 120 and the second passivation layer 220 are formed through an OSP surface treatment.
According to an embodiment, the oxide layer 115 is formed on an exposed surface of the aluminum pattern 110. The oxide layer 115 can naturally form as the aluminum pattern 110 contacts air. Thus, the oxide layer 115 is an aluminum oxide. The oxide layer 115 can protect the aluminum pattern 110.
Referring to
According to an embodiment, a third conductive pattern 300 is formed in the second insulating layer 12. Accordingly, a first contact plug 160 is formed that penetrates into the first insulating layer 11 and electrically connects the first conductive pattern 100 and the third conductive pattern 300. A second contact plug 260 is formed that penetrates into the second insulating layer 12 and electrically connects the second conductive pattern 200 and the third conductive pattern 300. The insulating layer 10a may include two layers as shown in
According to an embodiment, a thickness of the aluminum pattern 110 in a direction perpendicular to an upper surface of the insulating layer 10a is less than the thickness of the first conductive pattern 100 in the direction perpendicular to the upper surface of the insulating layer 10a. The thickness of the aluminum pattern is relatively exaggerated for emphasis in
Referring to
Referring to
According to an embodiment, the second contact plug 260 is formed that penetrates into the second insulating layer 12 and is connected to the second conductive layer 90. The contact plug 260 can be formed by forming a contact hole 260a using wet or dry etching or through mechanical drilling or laser drilling and then through a plating process.
Referring to
Referring to
According to an embodiment, the first solder resist layer 130 includes the at least one opening 130a that exposes a part of the first conductive pattern 100, a part of the barrier pattern 140, and a part of the aluminum pattern 110. The exposed parts of the first conductive pattern 100, the part of the barrier pattern 140, and the part of the aluminum pattern 110 can function as pads that contact a bonding wire that electrically connects the PCB and a semiconductor chip or a semiconductor package that is mounted on the PCB.
According to an embodiment, the first passivation layer 120 and the second passivation layer 220 are respectively formed on exposed surfaces of the first conductive pattern 100 and the second conductive pattern 200. Thus, the first passivation layer 120 is formed on sides of portions of the first conductive pattern 100, and the second passivation layer 220 is formed on lower surfaces of at least portions of the second conductive pattern 200. The first passivation layer 120 and the second passivation layer 220 can be formed through an OSP surface treatment. The first passivation layer 120 and the second passivation layer 220 can be simultaneously formed, but embodiments are not limited thereto. The oxide layer 115 is formed on a surface of the aluminum pattern 110 that is exposed by the opening 130a. The oxide layer 115 is an aluminum oxide. The oxide layer 115 can protect the aluminum pattern 110.
Referring to
In some embodiments, the semiconductor chip 500 may be a controller chip, a non-volatile memory chip, a volatile memory chip, and/or a dummy chip, or a combination of these chips.
A non-volatile memory chip may be, for example, a NAND flash memory, a resistive random access memory (RRAM), a magnetoresistive RAM (MRAM), a phase-changed RAM (PRAM), or a ferroelectric RAM (FRAM). A non-volatile memory chip may be a semiconductor package that includes one non-volatile memory chip or a plurality of stacked non-volatile memory chips.
In some embodiments, a plurality of semiconductor chips 500 may be stacked in the PCB 1. In some embodiments, the plurality of stacked semiconductor chips 500 may be electrically connected to each other via a through electrode.
According to an embodiment, a bonding wire 600 electrically connects the PCB 1 and the semiconductor chip 500. The bonding wire 600 may include, for example, copper or gold. The bonding wire 600 penetrates into the oxide 115 formed on a surface of the aluminum pattern 110 to electrically connect a pad 520 of the semiconductor chip 500 and the first conductive pattern 100 of the PCB 1.
According to an embodiment, the mold layer 700 is formed on an upper surface of the PCB 1 to cover at least a part of the upper surface of the PCB 1 and the semiconductor chip 500. The mold layer 700 may include, for example, a silicon material, a thermosetting material, a thermoplastic material, a UV curable material, etc. When the mold layer 700 includes a thermosetting material, the mold layer 700 may include a phenol type agent, an acid anhydride type agent, an amine type curable agent, or an acrylic polymer additive.
In some embodiments, the mold layer 700 includes resin while including a relatively small amount of filler. In this regard, the filler may be a silica filler.
Although the semiconductor chip 500 is mounted in
While embodiments of the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
6329074, | Nov 30 1998 | Mitsui Mining & Smelting Co., Ltd. | Copper foil for printed wiring board having excellent chemical resistance and heat resistance |
6770976, | Feb 13 2002 | NIKKO MATERIALS USA, INC | Process for manufacturing copper foil on a metal carrier substrate |
6955740, | Jan 10 2002 | CERBERUS BUSINESS FINANCE, LLC | Production of laminates for printed wiring boards using protective carrier |
7027145, | Jun 24 2003 | MICHIGAN, UNIVERSITY OF, THE REGENTS OF THE | Reconfigurable surface finish inspection apparatus for cylinder bores and other surfaces |
7175920, | Sep 22 2000 | FURUKAWA ELECTRIC CO , LTD , THE | Copper foil for high-density ultra-fine printed wiring board |
7691487, | Jul 04 2002 | MITSUI MINING & SMELTING CO , LTD | Electrodeposited copper foil with carrier foil |
8294039, | May 25 2007 | PRINCO CORP | Surface finish structure of multi-layer substrate and manufacturing method thereof |
8409726, | Nov 13 2008 | HAESUNG DS CO , LTD | Printed circuit board with multiple metallic layers and method of manufacturing the same |
8461036, | Dec 22 2009 | Intel Corporation | Multiple surface finishes for microelectronic package substrates |
8729395, | Jun 28 2011 | Samsung Electro-Mechanics Co., Ltd. | Wire bonding joint structure of joint pad, and method for preparing the same |
20040126547, | |||
20050017361, | |||
20070205520, | |||
20080217758, | |||
20100071950, | |||
20110031596, | |||
20110089462, | |||
20110297423, | |||
20120175772, | |||
20120205039, | |||
20130192885, | |||
20130277838, | |||
20130320547, | |||
20140144682, | |||
20140231127, | |||
20140284827, | |||
20140308538, | |||
20150340332, | |||
20160329275, | |||
20160374205, | |||
20170006713, | |||
JP2014193606, | |||
JP5826322, | |||
JP9092649, | |||
KR100959164, | |||
KR101317184, | |||
KR101391811, | |||
KR1020140076811, |
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