structures including a photodetector and methods of fabricating such structures. A substrate, which is composed of a semiconductor material, includes a first trench, a second trench, and a pillar of the semiconductor material that is laterally positioned between the first trench and the second trench. A first portion of a dielectric layer is located in the first trench and a second portion of the dielectric layer is located in the second trench. A waveguide core is coupled to the pillar at a top surface of the substrate.
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16. A method comprising:
forming a first trench and a second trench in a substrate comprised of a semiconductor material, wherein a pillar of the semiconductor material laterally positioned between the first trench and the second trench;
forming a spacer in the first trench and on the pillar;
forming a second dielectric layer beneath the spacer;
forming a first dielectric layer having a first portion in the first trench and a second portion in the second trench; and
forming a waveguide core coupled to the pillar at a top surface of the substrate,
wherein the second dielectric layer is positioned between the first portion of the first dielectric layer and the pillar.
1. A structure comprising:
a bulk substrate comprised of a semiconductor material, the bulk substrate including a top surface, a first trench extending from the top surface into the bulk substrate, a second trench extending from the top surface into the bulk substrate, and a first pillar of the semiconductor material laterally positioned between the first trench and the second trench;
a first dielectric layer having a first portion in the first trench and a second portion in the second trench; and
a first waveguide core directly on the first pillar at the top surface of the bulk substrate, the first waveguide core overlapping in part with the first portion of the first dielectric layer at the top surface of the bulk substrate, and the first waveguide core overlapping in part with the second portion of the first dielectric layer at the top surface of the bulk substrate,
wherein the first portion and the second portion of the first dielectric layer are arranged below the first waveguide core.
2. The structure of
3. The structure of
4. The structure of
5. The structure of
6. The structure of
a photodetector comprising a conformal layer positioned over the curved shape of the first waveguide core.
8. The structure of
a heater positioned over the top surface of the bulk substrate; and
a conductive layer coupling the heater to the first waveguide core.
9. The structure of
a second waveguide core coupled to the second pillar at the top surface of the bulk substrate,
wherein the first waveguide core and the second waveguide core are respective arms of a Mach-Zehnder interferometer modulator.
10. The structure of
11. The structure of
a transistor in a different region of the bulk substrate than the first waveguide core.
12. The structure of
13. The structure of
a spacer in the first trench and on the first pillar; and
a second dielectric layer beneath the spacer, the second dielectric layer positioned between the first portion of the first dielectric layer and the first pillar.
14. The structure of
15. The structure of
17. The method of
forming a heater positioned over the top surface of the substrate; and
forming a conductive layer coupling the heater to the waveguide core.
18. The method of
forming a photodetector conformally positioned over the curved shape of the waveguide core.
19. The method of
forming a p-type region and an n-type region in the waveguide core,
wherein a p-n junction is defined at an interface between the p-type region and the n-type region.
20. The structure of
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The present invention relates to photonics chips and, more particularly, to structures including a waveguide core and methods of fabricating such structures.
Photonics chips are used in many applications and systems including, but not limited to, data communication systems and data computation systems. A photonics chip integrates optical components, such as waveguides, optical switches, and bends, and electronic components, such as field-effect transistors, into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components. Silicon optical components rely on the thick buried oxide layer of a silicon-on-insulator wafer to provide a bottom cladding.
Improved structures including a waveguide core and methods of fabricating such structures are needed.
In an embodiment of the invention, a structure includes a substrate composed of a semiconductor material. The substrate includes a first trench, a second trench, and a pillar of the semiconductor material that is laterally positioned between the first trench and the second trench. The structure further includes a dielectric layer having a first portion in the first trench and a second portion in the second trench. A waveguide core is coupled to the pillar at a top surface of the substrate.
In an embodiment of the invention, a method includes forming a first trench and a second trench in a substrate comprised of a semiconductor material. A pillar of the semiconductor material is laterally positioned between the first trench and the second trench. The method further includes forming a dielectric layer having a first portion in the first trench and a second portion in the second trench, and forming a first waveguide core that is coupled to the pillar at a top surface of the substrate.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
With reference to
Pillars 18 containing portions of the single-crystal semiconductor material of the substrate 12 are located laterally between adjacent trenches 10. The pillars 18 extend from the top surface 11 of the substrate 12 to the same depth as the respective bottoms 17 of the trenches 10. The trenches 10 have a width, w1, between the sidewalls 16, and the pillars 18 have a width, w2, that is significantly less than the width, w1, of the trenches 10. In an embodiment, the width, w1, may be greater than or equal to two (2) microns, and the width, w2, may be about fifty (50) nanometers to about one (1) micron. In an embodiment, the pillars 18 may have an aspect ratio that is less than or equal to sixty (60).
With reference to
With reference to
With reference to
A dielectric layer 24 is then deposited and patterned by lithography and etching processes to open a region over the pillars 18 and dielectric-filled trenches 10. The dielectric layer 24 may be composed of a dielectric material, such as silicon nitride.
With reference to
The portions of the dielectric layer 20 in the trenches 10 are arranged below the waveguide cores 26, and each waveguide core 26 overlaps at its sides with the portions of the dielectric layer 20. Because the epitaxial growth is characterized by a vertical growth component and a lateral growth component, the waveguide cores 26 may be shaped as curved portions of cylinders extending along respective longitudinal axes and having a width that is greater than the width of the pillars 18. In an embodiment, the width of the waveguide cores 26 may be equal to approximately three times the width of the pillars 18, and the height of the waveguide cores 26 may be equal to approximately three times the width of the pillars 18.
With reference to
The portions of the dielectric layer 20 provide a bottom cladding for the waveguide cores 26. The dielectric layer 20 replaces the buried oxide layer of a silicon-on-insulator substrate, which enables the use of a cheaper bulk wafer as the substrate 12 for fabricating the photonics chip.
With reference to
With reference to
In an alternative embodiment, the semiconductor material of the pillars 18 may be implanted with ions to damage the crystal structure of the substrate 12 along the sidewalls 16 of the trenches 10 and thereby increase the oxidation rate. The implantation conditions (e.g., ion species (e.g., boron, arsenic, germanium, silicon, oxygen), dose, kinetic energy, tilt angle) may be selected to tune the amount of damage imparted to the crystal structure of the substrate 12.
With reference to
With reference to
With reference to
A layer 52 provides a bridge that connects the heater 50 with the adjacent waveguide core 26. The layer 52, which may be composed of polysilicon patterned by photolithography and etching processes, provides a path for the transfer of heat from the heater 50 to the waveguide core 26. The layer 52 may overlap with a section of the adjacent waveguide core 26. The layer 52 may be located in part over the shallow trench isolation region 22 between the heater 50 and the waveguide core 26, as well as in part over an adjacent portion of the dielectric layer 20. The dielectric materials thermally isolate the heater 50 from the substrate 12 during operation.
During operation, heat transferred to the waveguide core 26 from the heater 50 through the layer 52 may be used to modulate laser light received from the input waveguide 54 to provide digitized output signals at the output waveguide 56 by changing the permittivity (i.e., dielectric constant) of the heated waveguide core 26. The change to the permittivity of the heated waveguide core 26 prompts a change in the refractive index of its semiconductor material.
With reference to
Upper portions 31 of the waveguide cores 26 may be doped to have an opposite conductivity type from the lower portions 29 of the waveguide cores 26, which defines p-n junctions 64. In an embodiment, the upper portions 31 of the waveguide cores 26 may be doped with low-energy implantation.
Heavily-doped contacts 66 having the same conductivity type as the upper portions 31 of the waveguide cores 26 are formed on the dielectric layer 20. The heavily-doped contacts 66 are respectively coupled to the upper portions 31 of the waveguide cores 26. A heavily-doped contact 68 is formed in the reach-through region 62 at the top surface 11 of the substrate 12. In an embodiment, the pillars 18, lower portions 29 of the waveguide cores 26, well 60, reach-through region 62, and heavily-doped contact 68 may be doped to have n-type conductivity, and the upper portions 31 of the waveguide cores 26 and the heavily-doped contacts 66 may be doped to have p-type conductivity.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Ellis-Monaghan, John J., Jain, Vibhor, Adusumilli, Siva P.
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