A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.
|
1. A memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
a memory stack structure extending through the alternating stack, wherein the memory stack structure comprises a vertical stack of discrete charge storage elements that are vertically spaced apart from each other located at levels of the electrically conductive layers, a tunneling dielectric layer located on inner sidewalls of the discrete charge storage elements, and a vertical semiconductor channel contacting an inner sidewall of the tunneling dielectric layer,
wherein each of the discrete charge storage elements comprises:
a silicon nitride portion including an inner sidewall that contacts an outer sidewall of the tunneling dielectric layer; and
a silicon carbide nitride liner in contact with the silicon nitride portion;
further comprising silicon oxide blocking dielectric portions located at each level of the discrete charge storage elements, wherein each of the discrete charge storage elements is laterally spaced from a respective one of the electrically conductive layers by a respective one of the silicon oxide blocking dielectric portions;
wherein each of the discrete charge storage elements further comprises a silicon nitride liner contacting the silicon carbide nitride liner and the outer sidewall of the tunneling dielectric layer;
wherein the silicon nitride liner of each of the discrete charge storage elements contacts a respective overlying one of the insulating layers, and contacts a respective underlying one of the insulating layers; and
wherein the silicon nitride liner of each of the discrete charge storage elements is thinner than the silicon nitride portion.
|
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device with composite charge storage structures and methods of manufacturing the same.
Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack, wherein the memory stack structure comprises a composite charge storage structure, a tunneling dielectric layer located on an inner sidewall of the composite charge storage structure, and a vertical semiconductor channel contacting an inner sidewall of the tunneling dielectric layer. The composite charge storage structure comprises a vertical stack of discrete tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers and vertically spaced apart from each other, and a continuous charge storage layer including a second charge trapping material extending through a plurality of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material.
According to another aspect of the present disclosure, a method of forming a memory device is provided, which comprises: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; forming a memory opening through the alternating stack; and forming a memory stack structure by sequentially forming a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel in the memory opening. The composite charge storage structure is formed by: forming a vertical stack of tubular charge storage material portions including a first charge trapping material and at levels of the electrically conductive layers as discrete material portions that are vertically spaced apart by the insulating layers; and forming a charge storage layer including a second charge trapping material and extending through a plurality of electrically conductive layers of the electrically conductive layers.
According to an aspect of the present disclosure, a memory device is provided, which comprises: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack, wherein the memory stack structure comprises a vertical stack of discrete charge storage elements that are vertically spaced apart from each other and located at levels of the electrically conductive layers, a tunneling dielectric layer located on inner sidewalls of the discrete charge storage elements, and a vertical semiconductor channel contacting an inner sidewall of the tunneling dielectric layer, wherein each of the discrete charge storage elements comprises: a silicon nitride portion including an inner sidewall that contacts an outer sidewall of the tunneling dielectric layer; and a silicon carbide nitride liner in contact with the silicon nitride portion.
According to another aspect of the present disclosure, a method of forming a memory device is provided, which comprises: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming a memory opening through the alternating stack; forming annular recess regions around the memory opening at levels of the sacrificial material layers; forming discrete charge storage elements in the annular recess regions, wherein each of the discrete charge storage elements comprises a silicon nitride portion and a silicon carbide nitride liner disposed between the silicon nitride portion and a respective one of the sacrificial material layers located at a same level as the silicon nitride portion; forming a tunneling dielectric layer, a vertical semiconductor channel, and a drain region in the memory opening; and replacing the sacrificial material layers with electrically conductive layers.
As discussed above, the embodiments of the present disclosure are directed to a three-dimensional memory device with composite charge storage structures and methods of manufacturing the same, the various aspects of which are described below. The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.
A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no intervening substrates. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. Pat. No. 5,915,167 titled “Three-dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three-dimensional memory arrays. The various three-dimensional memory devices of the present disclosure include a monolithic three-dimensional NAND string memory device, and can be fabricated employing the various embodiments described herein.
Referring to
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0×105 S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×105 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×105 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−5 S/m to 1.0×105 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
At least one semiconductor device 700 for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure 720 can be formed by etching portions of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer 9, and can be subsequently patterned to form at least one gate structure (750, 752, 754, 758), each of which can include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 can be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. Active regions 730 can be formed in upper portions of the substrate semiconductor layer 9, for example, by introducing electrical dopants employing the at least one gate structure (750, 752, 754, 758) as masking structures. Additional masks may be employed as needed. The active region 730 can include source regions and drain regions of field effect transistors. A first dielectric liner 761 and a second dielectric liner 762 can be optionally formed. Each of the first and second dielectric liners (761, 762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 can be a silicon oxide layer, and the second dielectric liner 762 can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.
A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer 770. In one embodiment the planarized top surface of the planarization dielectric layer 770 can be coplanar with a top surface of the dielectric liners (761, 762). Subsequently, the planarization dielectric layer 770 and the dielectric liners (761, 762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer 9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).
The optional semiconductor material layer 10, if present, can be formed on the top surface of the substrate semiconductor layer 9 prior to, or after, formation of the at least one semiconductor device 700 by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer 9. The deposited semiconductor material can be any material that can be employed for the substrate semiconductor layer 9 as described above. The single crystalline semiconductor material of the semiconductor material layer 10 can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer 9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer 770 can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer 10 can have a top surface that is coplanar with the top surface of the planarization dielectric layer 770.
The region (i.e., area) of the at least one semiconductor device 700 is herein referred to as a peripheral device region 200. The region in which a memory array is subsequently formed is herein referred to as a memory array region 100. A staircase region 300 for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region 100 and the peripheral device region 200.
Referring to
Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer 32, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulating layers 32 and sacrificial material layers 42, and constitutes a prototype stack of alternating layers comprising insulating layers 32 and sacrificial material layers 42.
The stack of the alternating plurality is herein referred to as an alternating stack (32, 42). In one embodiment, the alternating stack (32, 42) can include insulating layers 32 composed of the first material, and sacrificial material layers 42 composed of a second material different from that of insulating layers 32. The first material of the insulating layers 32 can be at least one insulating material. As such, each insulating layer 32 can be an insulating material layer. Insulating materials that can be employed for the insulating layers 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers 32 can be silicon oxide.
The second material of the sacrificial material layers 42 is a sacrificial material that can be removed selective to the first material of the insulating layers 32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material. The sacrificial material layers 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers 42 can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers 42 can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.
In one embodiment, the insulating layers 32 can include silicon oxide, and sacrificial material layers can include silicon nitride sacrificial material layers. The first material of the insulating layers 32 can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers 32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The second material of the sacrificial material layers 42 can be formed, for example, CVD or atomic layer deposition (ALD). The sacrificial material layers 42 can be suitably patterned so that conductive material portions to be subsequently formed by replacement of the sacrificial material layers 42 can function as electrically conductive electrodes, such as the control gate electrodes of the monolithic three-dimensional NAND string memory devices to be subsequently formed. The sacrificial material layers 42 may comprise a portion having a strip shape extending substantially parallel to the major surface 7 of the substrate.
The thicknesses of the insulating layers 32 and the sacrificial material layers 42 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer 32 and for each sacrificial material layer 42. The number of repetitions of the pairs of an insulating layer 32 and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer) 42 can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer 42.
While the present disclosure is described employing an embodiment in which the spacer material layers are sacrificial material layers 42 that are subsequently replaced with electrically conductive layers, embodiments are expressly contemplated herein in which the sacrificial material layers are formed as electrically conductive layers. In this case, steps for replacing the spacer material layers with electrically conductive layers can be omitted.
The topmost layer of the alternating stack (32, 42) can be an insulating layer, which is herein referred to as a topmost insulating layer 32T, which can be formed over the alternating stack (32, 42). The topmost insulating layer 32T can have a greater thickness than each of the insulating layers 32. The topmost insulating layer 32T can be deposited, for example, by chemical vapor deposition. In one embodiment, the topmost insulating layer 32T can be a silicon oxide layer.
Referring to
The terrace region is formed in the staircase region 300, which is located between the memory array region 100 and the peripheral device region 200 containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.
Each sacrificial material layer 42 other than a topmost sacrificial material layer 42 within the alternating stack (32, 42) laterally extends farther than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that continuously extend from a bottommost layer within the alternating stack (32, 42) to a topmost layer within the alternating stack (32, 42).
Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer 32 and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer 32 and a sacrificial material layer 42. In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1 such that each vertical step has the height of a plurality of pairs of an insulating layer 32 and a sacrificial material layer 42, and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers 42 has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers 42 (as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers 42 may also be employed. Each sacrificial material layer 42 has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers 42 such that each physically exposed surface of any sacrificial material layer 42 does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd1, and the columns of staircases may be arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to the boundary between the memory array region 100 and the staircase region 300.
A retro-stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion 65. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may, or may not, be doped with dopants such as B, P, and/or F.
Optionally, drain select level isolation structures 72 can be formed through the topmost insulating layer 32T and a subset of the sacrificial material layers 42 located at drain select levels. The drain select level isolation structures 72 can be formed, for example, by forming drain select level isolation trenches and filling the drain select level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the topmost insulating layer 32T.
Referring to
The memory openings 49 extend through the entirety of the alternating stack (32, 42). The support openings 19 extend through a subset of layers within the alternating stack (32, 42). The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32, 42) can alternate to optimize etching of the first and second materials in the alternating stack (32, 42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the memory openings 49 and the support openings 19 can be substantially vertical, or can be tapered. The patterned lithographic material stack can be subsequently removed, for example, by ashing.
The memory openings 49 and the support openings 19 can extend from the top surface of the alternating stack (32, 42) to at least the horizontal plane including the topmost surface of the semiconductor material layer 10. In one embodiment, an overetch into the semiconductor material layer 10 may be optionally performed after the top surface of the semiconductor material layer 10 is physically exposed at a bottom of each memory opening 49 and each support opening 19. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer 10 may be vertically offset from the un-recessed top surfaces of the semiconductor material layer 10 by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 can be coplanar with the topmost surface of the semiconductor material layer 10.
Each of the memory openings 49 and the support openings 19 may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 can be formed in the memory array region 100. A two-dimensional array of support openings 19 can be formed in the staircase region 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 collectively constitutes a substrate (9, 10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the memory openings 49 and the support openings 19 can be extend to a top surface of the substrate semiconductor layer 9.
Referring to
Referring to
Referring to
Referring to
Referring to
Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 can include multiple dielectric metal oxide layers having different material compositions.
Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer 52 can be omitted, and a backside blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed.
The blocking dielectric layer 52 continuously extends through levels of a plurality of insulating layers 32 and a plurality of sacrificial material layers 42 within the alternating stack (32, 42). The blocking dielectric layer 52 has a laterally undulating vertical cross-sectional profile that conforms to the vertical cross-sectional profile of the alternating stack (32, 42) of the insulating layers 32 and the sacrificial material layers 42. Thus, the blocking dielectric layer 52 comprises laterally-protruding portions that protrude outward at each level of the annular recess regions 349 (and therefore, at each level of the sacrificial material layers 42). Further, a pair of annular ridges can laterally protrude from each laterally-protruding portion of the blocking dielectric layer 52 around each memory opening 49.
The interfaces between the blocking dielectric layer 52 and the insulating layers 32 can include annular horizontal surface portions and annular curved surface portions. A concave annular surface segment of an insulating layer 32 contacts a convex annular surface segment of the blocking dielectric layer 52 at each annular curved surface portion of the interfaces between the blocking dielectric layer 52 and the insulating layers 32. The annular horizontal surface portions of the interfaces can be vertically offset from interfaces between the insulating layers 32 and the sacrificial material layers 42.
In one embodiment, an inner sidewall of the blocking dielectric layer 52 comprises insulating-layer-level sidewall segments located at levels of the insulating layers 32, and annular recessed sidewall segments that are located at levels of the plurality of sacrificial material layers 42 and laterally recessed outward relative to insulating-layer-level sidewall segments.
Referring to
Referring to
A vertical stack of tubular charge storage material portions 53 can be formed within each memory opening 49. Each tubular charge storage material portion 53 includes the first charge trapping material. The tubular charge storage material portions 53 can be located at levels of the sacrificial material layers 42 as discrete material portions that are vertically spaced apart by the insulating layers 32. Each tubular charge storage material portion 53 can have a respective tubular shape with a uniform lateral distance between an inner cylindrical sidewall and an outer cylindrical sidewall. Each tubular charge storage material portion 53 can have a planar annular top surface and a planar annular bottom surface.
Each of the tubular charge storage material portions 53 can be formed within volumes of the annular recess regions 349. The tubular charge storage material portions 53 are formed on the blocking dielectric layer 52. The tubular charge storage material portions 53 can include aluminum nitride.
Referring to
The lower charge trap density of the second charge storage material is advantageous for preventing diffusion of electrical charge (e.g., electrons) from levels of the sacrificial material layers 42 (which are subsequently replaced with electrically conductive layers) to the level of an overlying insulating layer 32 or to the level of an underlying insulating layer 32. The higher charge trap density of the first charge storage material is advantageous for storing more electrical charge (e.g., electrons) during operation of a three-dimensional memory device employing the combination of a vertical stack of discrete (e.g., vertically separated) tubular charge storage material portions 53 and the continuous charge storage layer 54 as a composite charge storage structure (53, 54).
A tunneling dielectric layer 56 can be deposited over the charge storage layer 54. The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.
An optional first semiconductor channel layer 601 can be formed on the tunneling dielectric layer 56. The optional first semiconductor channel layer 601 includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polysilicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity 49′ is formed in the volume of each memory opening 49 that is not filled with the deposited material portions (52, 53, 54, 56, 601).
Referring to
A surface of the pedestal channel portion 11 (or a surface of the semiconductor material layer 10 in case the pedestal channel portions 11 are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity 49′ is vertically offset from the topmost surface of the pedestal channel portion 11 (or of the semiconductor material layer 10 in case pedestal channel portions 11 are not employed) by a recess distance. A tunneling dielectric layer 56 is located over the charge storage layer 54. A set of a blocking dielectric layer 52, a vertical stack of tubular charge storage material portions 53, a charge storage layer 54, and a tunneling dielectric layer 56 in a memory opening 49 constitutes a memory film 50. The combination of the vertical stack of tubular charge storage material portions 53 and the charge storage layer 54 constitutes a composite charge storage structure (53, 54). The composite charge storage structure (53, 54) includes a plurality of charge storage regions that are insulated from surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric layer 56. Each charge storage region can include a respective tubular charge storage material portion 53 and an adjoining portions of the charge storage layer 54 located at a respective level of a sacrificial material layer 42. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can have vertically coincident sidewalls.
Referring to
The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.
Referring to
Referring to
Referring to
Excess portions of the deposited semiconductor material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etch. Each remaining portion of the semiconductor material having a doping of the second conductively type constitutes a drain region 63. The horizontal portion of the second semiconductor channel layer 602 located above the top surface of the topmost insulating layer 32T can be concurrently removed by a planarization process. Each remaining portion of the second semiconductor channel layer 602 can be located entirety within a memory opening 49 or entirely within a support opening 19.
Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. Each adjoining pair of a first semiconductor channel layer 601 and a second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54, and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjoining set of a tunneling dielectric layer 56, a vertical stack of tubular charge storage material portions 53, a charge storage layer 54, and a blocking dielectric layer 52 collectively constitute a memory film 50, which includes a vertical stack of memory elements that can store a respective data bit with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours. In alternative embodiments, a blocking dielectric layer 52 may not be formed in each memory opening 49, and may be subsequently formed in backside recesses that are formed by removal of the sacrificial material layers 42 at a subsequent processing step.
Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, a plurality of memory elements comprising tubular charge storage material portions 53 and portions of the charge storage layer 54 contacting a respective one of the tubular charge storage material portions 53, and a blocking dielectric layer 52. Each combination of a pedestal channel portion 11 (if present), a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 is herein referred to as a memory opening fill structure 58. Each combination of a pedestal channel portion 11 (if present), a memory film 50, a vertical semiconductor channel 60, a dielectric core 62, and a drain region 63 within each support opening 19 fills the respective support openings 19, and constitutes a support pillar structure.
Referring to
Each memory stack structure 55 includes a vertical semiconductor channel 60, which may comprise multiple semiconductor channel layers (601, 602), and a memory film 50. The memory film 50 may comprise a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60, a vertical stack of charge storage elements (comprising a tubular charge storage material portion 53 and an adjoined portion of a charge storage layer 54) laterally surrounding the tunneling dielectric layer 56, and an optional blocking dielectric layer 52. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and/or for the vertical semiconductor channel 60.
Referring to
A photoresist layer (not shown) can be applied over the contact-level dielectric layer 73, and is lithographically patterned to form openings in areas between clusters of memory stack structures 55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer 73, the alternating stack (32, 42) and/or the retro-stepped dielectric material portion 65 employing an anisotropic etch to form backside trenches 79, which vertically extend from the top surface of the contact-level dielectric layer 73 at least to the top surface of the substrate (9, 10), and laterally extend through the memory array region 100 and the staircase region 300.
In one embodiment, the backside trenches 79 can laterally extend along a first horizontal direction hd1 and can be laterally spaced apart from each other along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The memory stack structures 55 can be arranged in rows that extend along the first horizontal direction hd1. The drain select level isolation structures 72 can laterally extend along the first horizontal direction hd1. Each backside trench 79 can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain select level isolation structure 72 can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1 that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures 55 can be located between a neighboring pair of a backside trench 79 and a drain select level isolation structure 72, or between a neighboring pair of drain select level isolation structures 72. In one embodiment, the backside trenches 79 can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.
Referring to
Referring to
The etch process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches 79. For example, if the sacrificial material layers 42 include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure 20, the retro-stepped dielectric material portion 65, and the memory stack structures 55 provide structural support while the backside recesses 43 are present within volumes previously occupied by the sacrificial material layers 42.
Each backside recess 43 can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 can be greater than the height of the backside recess 43. A plurality of backside recesses 43 can be formed in the volumes from which the second material of the sacrificial material layers 42 is removed. The memory openings in which the memory stack structures 55 are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses 43. In one embodiment, the memory array region 100 comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.
Each of the plurality of backside recesses 43 can extend substantially parallel to the top surface of the substrate (9, 10). A backside recess 43 can be vertically bounded by a top surface of an underlying insulating layer 32 and a bottom surface of an overlying insulating layer 32. In one embodiment, each backside recess 43 can have a uniform height throughout.
Referring to
Referring to
The backside blocking dielectric layer 44 can be formed in the backside recesses 43 and on a sidewall of the backside trench 79. The backside blocking dielectric layer 44 can be formed directly on horizontal surfaces of the insulating layers 32 and sidewalls of the memory stack structures 55 within the backside recesses 43. If the backside blocking dielectric layer 44 is formed, formation of the tubular dielectric spacers 116 and the planar dielectric portion 616 prior to formation of the backside blocking dielectric layer 44 is optional. In one embodiment, the backside blocking dielectric layer 44 can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer 44 can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.
The dielectric material of the backside blocking dielectric layer 44 can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer 44 can include a silicon oxide layer. The backside blocking dielectric layer 44 can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer 44 is formed on the sidewalls of the backside trenches 79, horizontal surfaces and sidewalls of the insulating layers 32, the portions of the sidewall surfaces of the memory stack structures 55 that are physically exposed to the backside recesses 43, and a top surface of the planar dielectric portion 616. A backside cavity 79′ is present within the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44.
Referring to
A metal fill material is deposited in the plurality of backside recesses 43, on the sidewalls of the at least one the backside trench 79, and over the top surface of the contact-level dielectric layer 73 to form a metallic fill material layer 46B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer 46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer 46B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer 46B can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer 46B can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer 46B can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer 46B is spaced from the insulating layers 32 and the memory stack structures 55 by the metallic barrier layer 46A, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.
A plurality of electrically conductive layers 46 can be formed in the plurality of backside recesses 43, and a continuous electrically conductive material layer 46L can be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 73. Each electrically conductive layer 46 includes a portion of the metallic barrier layer 46A and a portion of the metallic fill material layer 46B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers 32. The continuous electrically conductive material layer 46L includes a continuous portion of the metallic barrier layer 46A and a continuous portion of the metallic fill material layer 46B that are located in the backside trenches 79 or above the contact-level dielectric layer 73.
Each sacrificial material layer 42 can be replaced with an electrically conductive layer 46. A backside cavity 79′ is present in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44 and the continuous electrically conductive material layer 46L. A tubular dielectric spacer 116 laterally surrounds a pedestal channel portion 11. A bottommost electrically conductive layer 46 laterally surrounds each tubular dielectric spacer 116 upon formation of the electrically conductive layers 46.
Referring to
Each electrically conductive layer 46 can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer 46 are the control gate electrodes for the vertical memory devices including the memory stack structures 55. In other words, each electrically conductive layer 46 can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.
In one embodiment, the removal of the continuous electrically conductive material layer 46L can be selective to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 can be present at the bottom of each backside trench 79. In another embodiment, the removal of the continuous electrically conductive material layer 46L may not be selective to the material of the backside blocking dielectric layer 44 or, the backside blocking dielectric layer 44 may not be employed. The planar dielectric portions 616 can be removed during removal of the continuous electrically conductive material layer 46L. A backside cavity 79′ is present within each backside trench 79.
In one embodiment shown in
Backside blocking dielectric layers 44 can be located between each of the electrically conductive layers 46 and a combination of the blocking dielectric layer 52, a respective underlying one of the insulating layers 32, and a respective overlying one of the insulating layers 32.
Referring to
If a backside blocking dielectric layer 44 is present, the insulating material layer can be formed directly on surfaces of the backside blocking dielectric layer 44 and directly on the sidewalls of the electrically conductive layers 46. If a backside blocking dielectric layer 44 is not employed, the insulating material layer can be formed directly on sidewalls of the insulating layers 32 and directly on sidewalls of the electrically conductive layers 46.
An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer 73 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity 79′ is present within a volume surrounded by each insulating spacer 74. A top surface of the semiconductor material layer 10 can be physically exposed at the bottom of each backside trench 79.
An upper portion of the semiconductor material layer 10 that extends between the source region 61 and the plurality of pedestal channel portions 11 constitutes a horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channel 59 is connected to multiple vertical semiconductor channels 60 through respective pedestal channel portions 11. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of pedestal channel portions 11. A bottommost electrically conductive layer 46 provided upon formation of the electrically conductive layers 46 within the alternating stack (32, 46) can comprise a select gate electrode for the field effect transistors. Each source region 61 is formed in an upper portion of the substrate (9, 10). Semiconductor channels (59, 11, 60) extend between each source region 61 and a respective set of drain regions 63. The semiconductor channels (59, 11, 60) include the vertical semiconductor channels 60 of the memory stack structures 55.
A backside contact via structure 76 can be formed within each backside cavity 79′. Each contact via structure 76 can fill a respective backside cavity 79′. The contact via structures 76 can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity 79′) of the backside trench 79. For example, the at least one conductive material can include a conductive liner 76A and a conductive fill material portion 76B. The conductive liner 76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner 76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion 76B can include a metal or a metallic alloy. For example, the conductive fill material portion 76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.
The at least one conductive material can be planarized employing the contact-level dielectric layer 73 overlying the alternating stack (32, 46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 73 can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches 79 constitutes a backside contact via structure 76.
The backside contact via structure 76 extends through the alternating stack (32, 46), and contacts a top surface of the source region 61. If a backside blocking dielectric layer 44 is employed, the backside contact via structure 76 can contact a sidewall of the backside blocking dielectric layer 44.
Referring to
Referring to
In one embodiment, each of the tubular charge storage material portions 53 contacts a portion of an outer sidewall of the charge storage layer 54. In one embodiment, the entirety of an inner sidewall of the charge storage layer 54 contacts an outer sidewall of the tunneling dielectric layer 56.
In one embodiment, the memory device comprises a blocking dielectric layer 52 that continuously extends through the plurality of electrically conductive layers 46 and laterally surrounds the composite charge storage structure (53, 54) and located within a same memory opening 49.
In one embodiment, the blocking dielectric layer 52 comprises laterally-protruding portions that protrude outward from the composite charge storage structure (53, 54) at each level of the plurality of electrically conductive layers 46. Interfaces IN1 between the blocking dielectric layer 52 and the insulating layers 32 include annular horizontal surface portions. In one embodiment illustrated in
In one embodiment, a metal oxide backside blocking dielectric layer 44 can be located between the blocking dielectric layer 52 which comprises silicon oxide and each of the electrically conductive layers 46.
In one embodiment shown in
In one embodiment, each inner sidewall of the tubular charge storage material portions 53 can be vertically coincident with the segments of the inner sidewall of the blocking dielectric layer 52 that are located at levels of the insulating layers 32. In one embodiment, the entirety of an outer sidewall of the charge storage layer 54 can be straight in a vertical cross-sectional view that passes through a geometrical center of the volume of the memory opening fill structure 58.
In one embodiment, the first charge storage material comprises, and/or consists essentially of, aluminum nitride and the second charge storage material comprises, and/or consists essentially of, silicon nitride.
In one embodiment, the alternating stack (32, 46) comprises a terrace region in which each electrically conductive layer 46 other than a topmost electrically conductive layer 46 within the alternating stack (32, 46) laterally extends farther than any overlying electrically conductive layer 46 within the alternating stack (32, 46); the terrace region includes stepped surfaces of the alternating stack (32, 46); and support pillar structures 20 extend through the stepped surfaces and through a retro-stepped dielectric material portion 65 that overlies the stepped surfaces.
The first embodiment of the present disclosure provides a composite charge storage structure (53, 54) within each memory opening 49. Each composite charge storage structure (53, 54) includes discrete portions 53 of a first charge storage material having a high charge trap density and high electron mobility at each level of the electrically conductive layers 46 comprising the tubular charge storage material portions 53. The first charge storage material of the tubular charge storage material portions 53 provides high programming speed, and stores a high density of electrical charge (e.g., electrons). The high electron mobility of the first charge storage material does not induce high charge leakage which degrades data retention because this material is confined in discrete portions 53 at level of a respective electrically conductive layer 46. However, if the discrete portions 53 are used alone, then they may degrade the program slope.
Therefore, a continuous charge storage layer 54 is added at levels of the insulating layers 32 and the electrically conductive layers 46 to link up the discrete portions 53 in the composite charge storage structure (53, 54) to improve the program slope. The continuous charge storage layer 54 includes a second charge storage material having a lower charge trap density and a lower electron mobility than the first charge storage material. As such, electron leakage within the composite charge storage structure (53, 54) between neighboring memory cells is reduced, and data retention is not significantly degraded by the continuous charge storage layer 54. Thus, the composite charge storage structure (53, 54) can provide both improved programming speed and data (i.e., charge) retention characteristics without degrading the program slope for the memory stack structure 55.
Referring to
Referring to
Referring to
In case the sacrificial material layers 42 include silicon nitride, the silicon oxide blocking dielectric portions 152 can include residual nitrogen atoms at outer surface portions such that the atomic concentration of nitrogen atoms decreases with a lateral distance inward (i.e., toward the memory cavity 49′) from the outer sidewall within each silicon oxide blocking dielectric portion 152. In case the sacrificial material layers include amorphous silicon or polysilicon, the silicon oxide blocking dielectric portions 152 can consist essentially of silicon oxide and optional dopant atoms (such as boron, phosphorus, and/or arsenic). A sacrificial silicon oxide plate 13 can be formed by collateral oxidation of a surface portion of the pedestal channel portion 11.
Referring to
The silicon nitride material layer 541L can consist essentially of a stoichiometric or non-stoichiometric silicon nitride. The thickness of the silicon nitride material layer 541L can be in a range from 1 nm to 6 nm, such as from 2 nm to 4 nm, although lesser and greater thicknesses can also be employed. The silicon nitride material layer 541L can be deposited by a conformal deposition process such as low pressure chemical vapor deposition (LPCVD). The silicon carbide nitride material layer 542L includes a silicon carbide nitride material which contains any suitable non-zero atomic concentration of silicon, carbon and nitrogen, such as at least 5 atomic percent of silicon, carbon and nitrogen. In one embodiment, the atomic percentage of nitrogen atoms is between 5% and 20%, such as between 10% and 15%, the atomic percentage of silicon atoms is between 25% and 45%, such as between 30% and 40%, and the atomic percentage of carbon atoms is between 30% and 70%, such as between 50% and 60%. In one embodiment, the silicon carbide nitride material layer 542L may contain only silicon, carbon and nitrogen atoms and unavoidable impurities. In another embodiment, additional atoms other than silicon, carbon and nitrogen may be added at a concentration of 10 atomic percent or less. The silicon carbide nitride material layer 542L can be deposited by a conformal deposition process such as a low pressure chemical vapor deposition process employing a silicon precursor, a carbon precursor, and a nitrogen precursor, or by an atomic layer deposition process in which a silicon nitride deposition process and a carbonization process are repeated performed to provide a silicon carbide nitride material. The thickness of the silicon carbide nitride material layer 542L can be in a range from 1 nm to 10 nm, such as from 2 nm to 4 nm, although lesser and greater thicknesses can also be employed. An unfilled annular volume can be present within each of the annular recess regions 349 after deposition of the silicon carbide nitride material layer 542L.
The silicon nitride fill material layer 543L can consist essentially of a stoichiometric or non-stoichiometric silicon nitride. The thickness of the silicon nitride fill material layer 543L can be selected such that the unfilled annular volumes of the annular recess regions 349 after formation of the silicon carbide nitride material layer 542L are filled within the silicon nitride fill material layer 543L. The lateral thickness of the silicon nitride fill material layer 543L at levels of the insulating layers 32 can be in a range from 6 nm to 40 nm, such as from 10 nm to 25 nm, although lesser and greater thicknesses can also be employed. The silicon nitride fill material layer 543L can be deposited by a conformal deposition process such as low pressure chemical vapor deposition (LPCVD).
Referring to
Remaining discrete material portions located in the annular recess regions 349 comprise discrete charge storage elements 154. Each discrete charge storage element 154 is a composite charge storage structure including multiple materials. Each of the discrete charge storage elements 154 comprises a silicon nitride portion 543, a silicon carbide nitride liner 542, and an optional silicon nitride liner 541. Each silicon nitride portion 543 is a remaining portion of the silicon nitride fill material layer 543L. Each silicon carbide nitride liner 542 is a remaining portion of the silicon carbide nitride material layer 542L. Each silicon nitride liner 541 is a remaining portion of the silicon nitride material layer 541L.
Each silicon carbide nitride liner 542 can be disposed between a respective silicon nitride portion 543 and a respective sacrificial material layer 42 located at a same level as the silicon nitride portion 543. Each silicon carbide nitride liner 542 can have a uniform composition throughout. Within each discrete charge storage element 154, the silicon carbide nitride liner 542 contacts a top surface of the silicon nitride portion 543, an outer sidewall of the silicon nitride portion 543, and a bottom surface of the silicon nitride portion 543. Within each discrete charge storage element 154, the silicon nitride liner 541 can contact the silicon carbide nitride liner 542. The silicon nitride liner 541 of each of the discrete charge storage elements 154 contacts a respective overlying one of the insulating layers 32, and contacts a respective underlying one of the insulating layers 32. In one embodiment, the silicon nitride liner 541 of each of the discrete charge storage elements 154 contacts an annular horizontal bottom surface of the respective overlying one of the insulating layers 32, contacts an annular horizontal top surface of the respective underlying one of the insulating layers 32, and contacts a cylindrical sidewall of a respective silicon oxide blocking dielectric portion 152. Each of the discrete charge storage elements 154 can have a respective tubular shape, and can be formed directly on a respective one of the silicon oxide blocking dielectric portions 152. In one embodiment, physically exposed cylindrical sidewalls of the discrete charge storage elements 154 and cylindrical sidewalls of the insulating layers 32 can be vertically coincident with each other, i.e., can be located within a cylindrical plane that vertically extends from the topmost surface of the pedestal channel portion to the top surface of the topmost insulating layer 32T.
Referring to
An optional first semiconductor channel layer 601 can be formed on the tunneling dielectric layer 56. The optional first semiconductor channel layer 601 includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polysilicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity 49′ is present in the volume of each memory opening 49.
Referring to
A surface of the pedestal channel portion 11 (or a surface of the semiconductor material layer 10 in case the pedestal channel portions 11 are not employed) can be physically exposed underneath the opening through the first semiconductor channel layer 601 and the tunneling dielectric layer 56. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity 49′ is vertically offset from the topmost surface of the pedestal channel portion 11 (or of the semiconductor material layer 10 in case pedestal channel portions 11 are not employed) by a recess distance. The combination of the vertical stack of silicon oxide blocking dielectric portions 152, the vertical stack of discrete charge storage elements 154, and the tunneling dielectric layer 56 constitutes a memory film 150.
Referring to
The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as a semiconductor channel material. In other words, the semiconductor channel material is a set of all semiconductor material in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.
Referring to
Referring to
Referring to
Excess portions of the deposited semiconductor material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a recess etch. Each remaining portion of the semiconductor material having a doping of the second conductively type constitutes a drain region 63. The horizontal portion of the second semiconductor channel layer 602 located above the top surface of the topmost insulating layer 32T can be concurrently removed by a planarization process. Each remaining portion of the second semiconductor channel layer 602 can be located entirety within a memory opening 49 or entirely within a support opening 19.
Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region 63. Each adjoining pair of a first semiconductor channel layer 601 and a second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which electrical current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of discrete charge storage elements 154, and laterally surrounds a portion of the vertical semiconductor channel 60. The vertical stack of discrete charge storage elements 154 can store a respective data bit with a macroscopic retention time. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.
Each combination of a memory film 150 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 155. The memory stack structure 155 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, a vertical stack of discrete charge storage elements 154, and a vertical stack of silicon oxide blocking dielectric portions 152. Each combination of a pedestal channel portion 11 (if present), a memory stack structure 155, a dielectric core 62, and a drain region 63 within a memory opening 49 is herein referred to as a memory opening fill structure 58. Each combination of a pedestal channel portion 11 (if present), a memory film 150, a vertical semiconductor channel 60, a dielectric core 62, and a drain region 63 within each support opening 19 fills the respective support openings 19, and constitutes a support pillar structure.
Referring to
Referring to
Referring to
Each discrete charge storage element 154 does not include a silicon nitride liner 541 in the alternative configuration of the second exemplary structure. In this case, the silicon carbide nitride liner 542 of each of the discrete charge storage elements 154 contacts a respective overlying one of the insulating layers 32, and contacts a respective underlying one of the insulating layers 32. In one embodiment, the silicon carbide nitride liner 542 of each of the discrete charge storage elements 154 contacts an annular horizontal bottom surface of the respective overlying one of the insulating layers 32, contacts an annular horizontal top surface of the respective underlying one of the insulating layers 32, and contacts a cylindrical sidewall of a respective silicon oxide blocking dielectric portion 152.
Referring to
Referring to
Without wishing to be bound by a particular theory, it is believed that a significant portion of the electrons is stored in the part of the discrete charge storage element 154 closer to the blocking dielectric than to the tunneling dielectric. Therefore, in one embodiment, the silicon carbide nitride liner 542 with the deeper conduction band well is provided closer to the blocking dielectric (e.g., the silicon oxide blocking dielectric portions 152) than to the tunneling dielectric 60 to provide the electron storage well in the location where the significant portion of the electrons is stored. Therefore, if the silicon nitride liner 541 is present in the discrete charge storage element 154, then the silicon nitride liner 541 is thinner than the silicon nitride portion 543 to form the carbide nitride liner 542 closer to the blocking dielectric than to the tunneling dielectric. For example, the silicon nitride liner 541 is at least 50% thinner, such as 75% to 300% thinner than the silicon nitride portion 543.
Referring to
In one embodiment, the silicon carbide nitride liner 542 contacts a top surface of the silicon nitride portion 543, an outer sidewall of the silicon nitride portion 543, and a bottom surface of the silicon nitride portion 543 within each of the discrete charge storage elements 154. In one embodiment, each silicon carbide nitride liner 542 has a uniform composition throughout.
In one embodiment, edge portions of the silicon carbide nitride liner 542 are in contact with the outer sidewall of the tunneling dielectric layer 56.
In one embodiment, the atomic percentage of nitrogen atoms is between 5% and 20%, such as between 10% and 15%, the atomic percentage of silicon atoms is between 25% and 45%, such as between 30% and 40%, and the atomic percentage of carbon atoms is between 30% and 70%, such as between 50% and 60%, in the silicon carbide nitride liner 542.
In one embodiment, the memory device comprises silicon oxide blocking dielectric portions 152 located at each level of the discrete charge storage elements 154. Each of the discrete charge storage elements 154 is laterally spaced from a respective one of the electrically conductive layers 46 by a respective one of the silicon oxide blocking dielectric portions 152. In one embodiment, each of the silicon oxide blocking dielectric portions 152 has a respective tubular shape, contacts a bottom surface of a respective overlying one of the insulating layers 32, and contacts a top surface of a respective underlying one of the insulating layers 32. In one embodiment, each of the silicon oxide blocking dielectric portions ‘152 contacts the silicon carbide nitride liner 142.
In one embodiment, the silicon carbide nitride liner 542 of each of the discrete charge storage elements 154 contacts a respective overlying one of the insulating layers 32, and contacts a respective underlying one of the insulating layers 32. In one embodiment, the silicon carbide nitride liner 542 of each of the discrete charge storage elements 154 contacts an annular horizontal bottom surface of the respective overlying one of the insulating layers 32, contacts an annular horizontal top surface of the respective underlying one of the insulating layers 32, and contacts a cylindrical sidewall of a respective silicon oxide blocking dielectric portion 32.
In one embodiment, each of the discrete charge storage elements 154 further comprises a silicon nitride liner 541 contacting the silicon carbide nitride liner 542 and the outer sidewall of the tunneling dielectric layer 56. In one embodiment, the silicon nitride liner 541 of each of the discrete charge storage elements 154 contacts a respective overlying one of the insulating layers 32, and contacts a respective underlying one of the insulating layers 32. In one embodiment, the silicon nitride liner 541 of each of the discrete charge storage elements 154 is thinner than the silicon nitride portion 543.
In one embodiment, all surfaces of the silicon nitride portion 543 are in contact with the outer sidewall of the tunneling dielectric layer 56 or with a respective surface of the silicon carbide nitride liner 542 in each of the discrete charge storage elements 154. In one embodiment, each of the discrete charge storage elements 154 has a respective tubular shape; and the outer sidewall of the tunneling dielectric layer 56 has a straight vertical profile that extends through, and contacts, each of the discrete charge storage elements 154 in the memory opening fill structure 58.
Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
10651195, | Nov 09 2017 | SAMSUNG ELECTRONICS CO , LTD | Three-dimensional semiconductor memory device |
5915167, | Apr 04 1997 | ELM 3DS INNOVATONS, LLC | Three dimensional structure memory |
8349681, | Jun 30 2010 | SanDisk Technologies LLC | Ultrahigh density monolithic, three dimensional vertical NAND memory device |
9136130, | Aug 11 2014 | SanDisk Technologies LLC | Three dimensional NAND string with discrete charge trap segments |
9397093, | Feb 08 2013 | SanDisk Technologies LLC | Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof |
9552991, | Apr 30 2014 | SanDisk Technologies LLC | Trench vertical NAND and method of making thereof |
9613977, | Jun 24 2015 | SanDisk Technologies LLC | Differential etch of metal oxide blocking dielectric layer for three-dimensional memory devices |
9711530, | Mar 25 2016 | SanDisk Technologies LLC | Locally-trap-characteristic-enhanced charge trap layer for three-dimensional memory structures |
9875929, | Jan 23 2017 | SanDisk Technologies LLC | Three-dimensional memory device with annular blocking dielectrics and discrete charge storage elements and method of making thereof |
9922987, | Mar 24 2017 | SanDisk Technologies LLC | Three-dimensional memory device containing separately formed drain select transistors and method of making thereof |
9960180, | Mar 27 2017 | SanDisk Technologies LLC | Three-dimensional memory device with partially discrete charge storage regions and method of making thereof |
9991277, | Nov 28 2016 | SanDisk Technologies LLC | Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof |
20090085218, | |||
20090091040, | |||
20090140428, | |||
20140042516, | |||
20150318333, | |||
20160111291, | |||
20160204059, | |||
20170243950, | |||
20170352681, | |||
20170365522, | |||
20170373079, | |||
20180018263, | |||
20180108664, | |||
20180204881, | |||
20180226567, | |||
20190139983, | |||
20190198520, | |||
20190252045, | |||
20190319043, | |||
20190371807, | |||
20200006374, | |||
20200312874, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Feb 18 2020 | CUI, ZHIXIN | SANDISK TECHNOLOGIES LLC, | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 051857 | /0795 | |
Feb 18 2020 | YASUDA, IPPEI | SANDISK TECHNOLOGIES LLC, | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 051857 | /0795 | |
Feb 19 2020 | SanDisk Technologies LLC | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Feb 19 2020 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Date | Maintenance Schedule |
Sep 07 2024 | 4 years fee payment window open |
Mar 07 2025 | 6 months grace period start (w surcharge) |
Sep 07 2025 | patent expiry (for year 4) |
Sep 07 2027 | 2 years to revive unintentionally abandoned end. (for year 4) |
Sep 07 2028 | 8 years fee payment window open |
Mar 07 2029 | 6 months grace period start (w surcharge) |
Sep 07 2029 | patent expiry (for year 8) |
Sep 07 2031 | 2 years to revive unintentionally abandoned end. (for year 8) |
Sep 07 2032 | 12 years fee payment window open |
Mar 07 2033 | 6 months grace period start (w surcharge) |
Sep 07 2033 | patent expiry (for year 12) |
Sep 07 2035 | 2 years to revive unintentionally abandoned end. (for year 12) |