A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
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a mold compound in contact with the semiconductor substrate;
wherein the mold compound comprises a resin, and the resin includes filler particles; and
wherein a largest particle of the filler particles include a size between 5 microns and 32 microns.
12. A semiconductor package, comprising:
#5# an integrated circuit formed on a semiconductor substrate;
a stress buffer layer on the semiconductor substrate; and
a mold compound on a portion of the semiconductor substrate and on a surface of the stress buffer layer opposite the integrated circuit;
wherein the mold compound comprises a resin, and the resin includes filler particles; and
wherein a largest particle of the filler particles include a size between 5 microns and 50 microns.
17. A semiconductor package, comprising:
#5# a semiconductor substrate including a pair of capacitors that are sensitive to stress induced by filler particles in a mold compound, wherein the mold compound covers a portion of the semiconductor substrate; and
a layer of a material capable of impacting a stress induced by the filler particles, over a portion of the semiconductor substrate, wherein the mold compound contacts a surface of the layer;
wherein the mold compound comprises a resin, and the resin includes filler particles; and
wherein filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
2. The semiconductor package of 3. The semiconductor package of 4. The semiconductor package of 5. The semiconductor package of 6. The semiconductor package of 7. The semiconductor package of 8. The semiconductor package of 9. The semiconductor package of 10. The semiconductor package of 11. The semiconductor package of 13. The semiconductor package of 14. The semiconductor package of 15. The semiconductor package of 16. The semiconductor package of 18. The semiconductor package of 19. The semiconductor package of 20. The semiconductor package of
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This application is a continuation of U.S. patent application Ser. No. 15/853,345, filed Dec. 22, 2017, the contents of which are herein incorporated by reference in its entirety.
Many semiconductor devices are fabricated as a semiconductor die residing within a package. The package material includes a mold compound which provides mechanical support for and protects the integrated circuit formed on the semiconductor die. Some high precision analog devices (e.g., data converters, amplifiers, voltage or current references, sensors, etc.) may suffer a reduction in the precision of various parametrics as a result of packaging the die, reliability stresses, surface mounting the die, etc. Such reduction in precision may manifest itself as an increase in parametric distributions (e.g., distributions of offset voltages, reference voltages, etc.) which, in turn limits how narrowly certain parameters can be specified for the device.
In accordance with the disclosed embodiments, during the packaging operation a mold compound is used that includes filler particles having a maximum size in the range of 5 microns to 50 microns. In some embodiments, the maximum size of the filler particles ranges from 5 microns to 32 microns.
In one embodiment, a semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
For a detailed description of various examples, reference will now be made to the accompanying drawings in which:
Stresses from packaging can impact performance of components on a semiconductor substrate, such as transistors, resistors, and capacitors. It has been determined that a source of the problem has to do with the size of filler particles that comprise the mold compound used during the packaging process of the semiconductor substrate. The disclosed embodiments address the aforementioned problem by limiting the maximum size of the filler particles.
The stress buffer layer 110 may comprise polyimide, a silicone-based material, or other suitable material to reduce mold compound-induced stress on the integrated circuit. The stress buffer layer 110 reduces the variations in stress due to filler particles in the mold compound 120 on the semiconductor substrate 102. The stress buffer layer has a thickness designated as T1 in
The mold compound 120 includes a resin 132 (e.g., a polymer resin), and the resin 132 includes filler particles 130 (see blow up image 150 of a portion of the semiconductor package 100). Two filler particles have been identified in
As can be seen in the example of
Reference is made herein to the “size” of the filler particles 130. In the example in which a filler particle 130 is spherical, the size of that particular filler particle is the diameter of the sphere. In examples in which a filler particle 130 is non-spherical and has a non-geometric shape, the size may refer to the largest distance between opposite surfaces of the filler particle. In the blow-up view 150, filler particle 130c is shown to have a size S1 which represents the largest distance across the filler particle.
It has been determined that that filler particles 130 and the resin 132 in which the filler particles 130 reside have different coefficient of thermal expansion (CTE) and moduli (the measure of the ability of a material to withstand changes in length when under lengthwise tension or compression). Because the resin 132 and the filler particles 130 have substantially different values for CTE and modulus, a semiconductor package can experience local stress variations across the semiconductor substrate (die) due to temperature changes. Larger filler particles induce higher stress gradients on the semiconductor substrate. For example,
In accordance with the disclosed embodiments, the size of the largest filler particles 130 in the mold compound 120 is between 5 microns and 50 microns. That is, no filler particle 130 larger than 50 microns are present in the mold compound in such embodiments and one or more of the filler particles 130 in the mold compound 120 has a size of at least 5 microns. Some filler particles may have sizes less than 5 microns.
In some embodiments, the size of the largest filler particles 130 is between 5 microns and 32 microns, which means that no filler particles 130 larger than 32 microns are present in the mold compound in such embodiments and one or more of the filler particles 130 in the mold compound 120 has a size of at least 5 microns. In some embodiments, the range of the maximum particle size may be 10 to 25 microns.
In accordance with the disclosed embodiments, with the largest filler particle sizes being limited as noted above (e.g., between 5 microns and 50 microns, between 5 microns and 32 microns), the largest particle size will be small enough so as not to generate large local stress variations that might otherwise be present. Thus, the regions 180 and 185 above capacitors 106 and 108 in the embodiment of
In an example, multiple semiconductor packages 100 were fabricated, with each semiconductor including an SAR ADC with multiple nominally matching capacitors such as capacitors 106 and 108. Each semiconductor package 100 included a polyimide stress buffer layer 110 and a mold compound 120 including silica filler particles 130 in which the maximum filler particle size was less than or equal to approximately 32 microns. The mismatch in the capacitance of the capacitors was measured. The mismatch between the capacitors 106 and 108 were measured using standard techniques used in testing SAR ADCs which measure the ratio (C106−C108)/(C106+C108), where C106 and C108 are the capacitance of capacitors 106 and 108, respectively. The ratios C106/(C106+C108) and C108/(C106+C108) are nominally one-half. The measurement system makes multiple measurements of these ratios and accounts for offsets and noise in these readings to generate a sufficiently accurate measure of the ratio of (C106−C108)/(C106+C108). These measurements were also performed at different ambient temperatures to examine the variations of these ratios over the operating temperature range of the devices. The variation of this ratio over the temperature range is taken to represent the stability of the capacitance ratio. Further, the semiconductor packages 100 were fabricated with three different thicknesses for the polyimide stress buffer layer 110 (10 microns, 20 microns, and 30 microns). The reference to “1×,’ “2×,’” and “3×” refers to the 10, 20, and 30 micron thicknesses, respectively. Thus, six different types of multiple semiconductor packages were fabricated, and multiple instances of each type:
1. A semiconductor package 100 with stress buffer layer of 10 microns and a mold compound 120 with filler particles 130 having a maximum size of approximately 55 microns.
2. A semiconductor package 100 with stress buffer layer of 20 microns and a mold compound 120 with filler particles 130 having a maximum size of approximately 55 microns.
3. A semiconductor package 100 with stress buffer layer of 30 microns and a mold compound 120 with filler particles 130 having a maximum size of approximately 55 microns.
4. A semiconductor package 100 with stress buffer layer of 10 microns and a mold compound 120 with filler particles 130 having a maximum size of approximately 32 microns.
5. A semiconductor package 100 with stress buffer layer of 20 microns and a mold compound 120 with filler particles 130 having a maximum size of approximately 32 microns.
6. A semiconductor package 100 with stress buffer layer of 30 microns and a mold compound 120 with filler particles 130 having a maximum size of approximately 32 microns.
The disclosed examples are also directed to a method for forming a semiconductor package. In one example, the method includes forming an integrated circuit on a semiconductor substrate, forming a stress buffer layer on the integrated circuit, and attaching the semiconductor substrate to one or more leads. The method further includes applying a mold compound on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin, and the resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
However, with the maximum filler particle size limited to 32 microns for the mold compound 120, the standard deviations dropped to 0.33 for the 10 micron thick stress buffer layer 110, 0.23 for the 20 micron thick stress buffer layer 110, and 0.17 for the 30 micron thick stress buffer layer 110. Thus, reducing the maximum filler particle size from 55 microns to 32 microns for the 10 micron thick stress buffer layer 110 resulted in a 67% reduction in the standard deviation of the capacitor mismatch (a standard deviation reduction from 1 to 0.33), which means a much smaller capacitance mismatch. Further, compared to a mold compound with a maximum filler particle size of 55 microns and a 10 micron stress buffer layer, reducing the filler particle size from 55 microns to 32 microns and increasing the thickness of the stress buffer layer from 10 to 20 microns resulted in a drop in the standard deviation of 1 to 0.23.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Gurrum, Siva Prakash, Nangia, Amit Sureshkumar, Seetharaman, Janakiraman
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
10446414, | Dec 22 2017 | Texas Instruments Incorporated | Semiconductor package with filler particles in a mold compound |
4617708, | Dec 23 1982 | AT&T Technologies, Inc. | Component module for piggyback mounting on a circuit package having dual-in-line leads, and methods of fabricating same |
6321734, | Apr 06 1999 | Hitachi, Ltd.; Hitachi Car Engineering Co., Ltd. | Resin sealed electronic device and method of fabricating the same and ignition coil for internal combustion engine using the same |
7432625, | Aug 19 2004 | Kabushiki Kaisha Toyota Jidoshokki | Armature of motor |
8233261, | Dec 12 2006 | CHEMTRON RESEARCH LLC | Composite organic encapsulants |
8344487, | Jun 29 2006 | Analog Devices, Inc | Stress mitigation in packaged microchips |
8786105, | Jan 11 2013 | Intel Corporation | Semiconductor device with chip having low-k-layers |
9035473, | Sep 30 2008 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Circuit device and method of manufacturing the same |
20080237855, | |||
20150037938, | |||
20160084887, | |||
20170133309, | |||
20170162500, | |||
20180233422, |
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