In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.
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15. A device comprising:
a first semiconductor device, the first semiconductor device comprising a first external connection;
a buffer material located along an outside edge of the first semiconductor device; and
an underfill material extending from a sidewall of the first semiconductor device, around the buffer material, and to a point between the buffer material and the first external connection, the buffer material being fully embedded within the underfill material.
7. A device comprising:
a first semiconductor device comprising a top surface and a sidewall, wherein the top surface and the sidewall are connected by a first surface that is misaligned from the top surface and the sidewall;
a buffer material in physical contact with the top surface and covering the first surface, wherein a second surface of the buffer material shares a plane with the sidewall, the buffer material and the first semiconductor device being on a same side of the plane; and
an underfill material in physical contact with the top surface and the buffer material.
1. A device comprising:
a semiconductor device with an opening located at a corner of the semiconductor device;
a buffer material located at least partially within the opening, wherein the buffer material does not extend across the semiconductor device;
a substrate bonded to the semiconductor device; and
an underfill material located between the semiconductor device and the substrate and also located between the buffer material and an external connection of the semiconductor device in a direction parallel with a surface of the substrate facing the semiconductor device, wherein the buffer material has a first property with a value located between a value of the semiconductor device and a value of the underfill material.
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This application is a division of U.S. patent application Ser. No. 15/869,305, filed on Jan. 12, 2018, which claims the benefit of U.S. Provisional Application No. 62/527,849, filed on Jun. 30, 2017, which applications are hereby incorporated herein by reference.
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., semiconductor dies, chips, substrates, etc.) by continual reductions in device size as well as reductions in the spaces between the devices, which allow more components to be integrated into a given volume. However, as the sizes are reduced, additional problems arise with how the components are bonded and operate, and these additional problems should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Embodiments are described below with reference to semiconductor devices in a chip on wafer on substrate (CoWoS) configuration. However, this is intended to be illustrative and is not intended to be limiting. Rather, the ideas embodied herein may be used in a wide variety of configurations.
With reference now to
The first active devices comprise a wide variety of active devices and passive devices such as transistors, capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional parts of the design for the first semiconductor die 101 and the second semiconductor die 103. The first active devices may be formed using any suitable methods either within or else on the first substrate.
The metallization layers are formed over the first substrate and the first active devices and are designed to connect the various first active devices to form functional circuitry for both the first semiconductor die 101 and the second semiconductor die 103. In an embodiment the metallization layers are formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). In an embodiment there may be four layers of metallization separated from the first substrate by at least one interlayer dielectric layer (ILD), but the precise number of metallization layers is dependent upon the design of the first semiconductor die 101 and the second semiconductor die 103.
The contact pads 107 are formed in order to provide external contacts for the metallization layers and the first active devices. In an embodiment the contact pads 107 are formed of a conductive material such as aluminum, although other suitable materials, such as copper, tungsten, or the like, may alternatively be utilized. The contact pads 107 may be formed using a process such as CVD or PVD, although other suitable materials and methods may alternatively be utilized. Once the material for the contact pads 107 has been deposited, the material may be shaped into the contact pads 107 using, e.g., a photolithographic masking and etching process.
The first external connections 109 may be contact bumps such as controlled collapse chip connection (C4) bumps, ball grid array bumps, or microbumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the first external connections 203 are tin solder bumps, the first external connections 109 may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of about 100 μm. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shapes.
However, while solder bumps have been described as one embodiment of the first external connections 109, this description is intended to be illustrative and is not intended to be limiting. Rather, any suitable connective structures, such as conductive pillars (e.g., copper pillars) may also be utilized. All such structures are fully intended to be included within the scope of the embodiments.
The scribe region 105 is formed by not placing functional structures (such as the first active devices) into the area intended for the scribe regions 105. Other structures, such as test pads or dummy metals used for planarization, could be placed into the scribe region 105, but would not be necessary for the functioning of the first semiconductor die 101 or the second semiconductor die 103 once the first semiconductor die 101 and the second semiconductor die 103 have been separated from each other. The scribe regions 105 may be formed to have a first width W1 of between about 10 μm and about 200 μm, such as about 80 μm.
Once the first external connections 109 have been formed or otherwise placed on the contact pads 107, a first singulation process (represented in
Additionally, the saw blade may be chosen or made such that the saw blade has an angled edge which, when used to saw the wafer 100, will form a beveled edge 115 along both the first semiconductor die 101 and the second semiconductor die 103, although any other suitable method of forming the beveled edge 115 may also be utilized. In an embodiment the beveled edge 115 extends from a top surface of the first semiconductor die 101 towards the scribe region 105. In an embodiment the beveled edge 115 may be formed to have a first angle θ1 from the top surface of the first semiconductor die 101 of between about 20° and about 45°. However, any suitable angle may be utilized.
Additionally, by forming the beveled edge 115 within the first semiconductor die 101, there is formed a second opening (represented within
In an embodiment the buffer material 201 is a material that will act as a buffer between the materials of the first semiconductor die 101 (e.g., a major material of the first semiconductor die 101 such as the silicon material of the semiconductor substrate) and an underfill material 501 (not illustrated in
For example, in some embodiments the buffer material 201 may be a material which has a first Young's modulus that is between a second Young's modulus of the first substrate (within the first semiconductor die 101) and a third Young's modulus of the underfill material 501. In additional embodiments, the buffer material 201 may also have a first coefficient of thermal expansion (CTE) that has a value between a second CTE of the first substrate (within the first semiconductor die 101) and a third CTE of the underfill material 501.
In a particular embodiment the first substrate (within the first semiconductor die 101) is silicon with a Young's modulus of 160 GPa and a CTE of 2.6 μm*m−1*K−1. Additionally, the underfill material 501 is a polymer such as epoxy, with a Young's modulus of 11 GPa and a CTE of 23 μm*m−1*K−1. In such an embodiment the buffer material 201 may be a material such as epoxy, acrylic, or PU, which has a Young's modulus of 15 GPa (between the Young's modulus of silicon and the underfill material 501) and a CTE of 9 μm*m−1*K−1 (between the CTE of silicon and the underfill material 501). However, any suitable material may be utilized.
In the embodiment in which the buffer material 201 is dispensed around the outside edge of the first semiconductor die 101 and the second semiconductor die 103, the buffer material 201 may be formed to have a third width W3 from the edge of the scribe region 105 towards the center of the first semiconductor die 101 of between about 100 μm and about 200 μm, such as about 150 μm. Additionally, the buffer material 201 may maintain the third width W3 all the way around the outside edge of the first semiconductor die 101. As such, the buffer material 201 over the first semiconductor die 101 will have a total width along line A-A′ of double the third width W3, or between about 20 μm and about 200 μm, such as about 50 μm. However, any suitable width may be utilized.
Additionally, the buffer material 201 may be dispensed to continuously extend from the first semiconductor die 101, over the scribe region 105, and over the second semiconductor die 103. In this embodiment the buffer material 201 may have a fourth width W4 of twice the third width W3 (to include the widths of the buffer material 201 over both the first semiconductor die 101 and the second semiconductor die 103) as well as the first width W1 of the scribe region 105. As such, the buffer material 201 may have the fourth width W4 of between about 40 μm and about 400 μm, such as about 130 μm. However, any suitable dimensions may be utilized.
Returning now to
Once the buffer material 201 has been dispensed, the buffer material 201 may be cured in order to solidify the buffer material 201. In an embodiment in which the buffer material 201 is epoxy, the buffer material 201 may be cured at a temperature of between about 110 μm and about 150 μm, such as about 180 μm, for a time period of between about 10 s and about 2 hours, such as about 30 minutes. However, any suitable temperature (including room temperature) and any suitable time of curing may also be utilized.
While the second singulation process 301 separates the first semiconductor die 101 from the second semiconductor die 103, the second singulation process 301 will also cut through and remove material of the buffer material 201. As such, because both the buffer material 201 and the first semiconductor die 101 are sawed, the buffer material 201 will have an exterior sidewall that is aligned with and planar to a sidewall of the first semiconductor die 101 after the second singulation process 301 has occurred.
Additionally, while
Also, as one of ordinary skill in the art will recognize, utilizing a saw blade to singulate the first semiconductor die 101 is merely one illustrative embodiment and is not intended to be limiting. Alternative methods for singulating the first semiconductor die 101, such as utilizing one or more etches to separate the first semiconductor die 101 and the second semiconductor die 103, or even laser ablation may alternatively be utilized. These methods and any other suitable methods may alternatively be utilized to singulate the wafer 100.
The second substrate 401 may have one or more redistribution layers (not separately illustrated) disposed on one or both sides of the second substrate 401. The one or more through vias 405 may comprise conductive material connecting the first RDL at the first side of the second substrate 401 to the second RDL at the second side of the second substrate 401. The RDLs may comprise dielectric layers with conductive lines which may be electrically connected to the one or more through vias 405. For example, the first RDL may connect one or more of the second contact pads 403 (on a first side of the second substrate 401) to one have one or more of the third contact pads 407 (on the second side of the second substrate 401) The third contact pads 407 may be used to connect the second substrate 401 (and, hence, the first semiconductor die 101) to a third substrate 601 (not illustrated in
In an embodiment the second contact pads 403 and the third contact pads 407 may be similar to the contact pads 107 described above with respect to
In another embodiment the second substrate 401 may be another semiconductor wafer with additional semiconductor devices formed thereon. For example, the second substrate 401 may comprise a third semiconductor device (not separately illustrated) that is designed to work in conjunction with the first semiconductor die 101 but which has not yet been singulated from other semiconductor devices within the semiconductor wafer of the second substrate 401.
To bond the first semiconductor die 101 to the second substrate 401, the first external connections 109 are aligned with and placed into physical connection with the second contact pads 403 of the second substrate 401. Once in place, the temperature of the first external connections 109 is raised in order to initiate a reflow of the material of the first external connections 109. Once the reflow process has occurred and, afterwards, the material of the first external connections 109 has solidified, the first semiconductor die 101 is electrically and physically connected to the second substrate 401.
However, while the reflow process is described as one bonding process, this is intended to be illustrative and is not intended to be limiting. Rather, any suitable bonding process, such as copper-copper bonding in embodiments which utilize copper pillars, may also be utilized. All such bonding processes are fully intended to be included within the scope of the embodiments.
Once the first semiconductor die 101 and the second substrate 401 have been bonded together, the first semiconductor die 101 is separated from the second substrate 401 by the standoff height Hso. In an embodiment the standoff height Hso may be between about 30 μm and about 150 μm, such as about 100 μm. However, any suitable standoff height may be utilized.
In addition to sealing the first external connections 109, the underfill material 501 may also be dispensed to form fillets on each side of the first semiconductor die 101, thereby helping to seal and protect the sides of the first semiconductor die 101. In an embodiment the underfill material 501 may be dispensed until the fillet has a fifth width W5 (extending away from the first semiconductor die 101) of less than about 2 mm, such as between about 1.5 mm to about 2 mm. Additionally, the fillet may have a third height H3 that may or may not extend to cover all of the sidewall of the first semiconductor die 101. As such, the third height H3 may be between about 700 mm and about 1000 mm. However, any suitable dimensions may be utilized.
Once singulated, the second substrate 401 and, hence, the first semiconductor die 101, are bonded to the third substrate 601 using, e.g., second external connectors 603. In an embodiment the second external connectors 603 may be contact bumps such as ball grid array bumps, microbumps, or controlled collapse chip connection (C4) bumps, and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the second external connectors 603 are tin solder bumps, the second external connectors 603 may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc, to a thickness of about 100 μm. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shapes.
Once the second external connectors 603 have been formed, the second substrate 401 is bonded to the third substrate 601 using the second external connectors 603. In an embodiment the third substrate 601 may be a printed circuit board such as a laminate substrate formed as a stack of multiple thin layers (or laminates) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, or the like. However, any other suitable substrate, such as a silicon interposer, a silicon substrate, organic substrate, a ceramic substrate, or the like, may alternatively be utilized, and all such redistributive substrates that provide support and connectivity to the second substrate 401 are fully intended to be included within the scope of the embodiments.
The second substrate 401 may be bonded to the third substrate 601 by initially aligning the second substrate 401 with the third substrate 601 with the second external connectors 603 between corresponding contact pads. Once in physical contact, a reflow may be performed to reflow the second external connectors 603 and bond the second external connectors 603 with both the second substrate 401 and the third substrate 601. However, any other suitable bonding may alternatively be utilized.
By placing the buffer material 201 between the first semiconductor die 101 and the underfill material 501, the buffer material 201 can act as a buffer between the materials of the first semiconductor die 101 and the underfill material 501. As such, the negative effects from the differences in coefficients of thermal expansion, such as cracks, that could develop in the underfill material 501 can be reduced or eliminated. Such a reduction leads to an overall improvement in yield and reliability as well as an enlargement of the reliability window in embodiments which utilize a chip on wafer on substrate configuration.
In this embodiment the first opening 113 may be formed to have a fourth height H4 of between about 10 μm and about 90 μm, such as about 20 μm. Additionally, the first opening 113 may also extend into the first semiconductor die 101 from the scribe region 105 a sixth width W6 of between about 10 μm and about 90 μm, such as about 20 μm. However, any suitable dimensions may be utilized.
In this embodiment, because the first opening 113 is formed to have straight sidewalls as well as a straight bottom surface, the buffer material 201 will also have a bottom surface that is straight and parallel with the top surface of the first semiconductor die 101. Additionally, the buffer material 201 will also have a sidewall that intersects the bottom surface at a right angle, forming the buffer material 201 into a stair step shape. However, any suitable shape may be utilized.
Additionally, because the buffer material 201 has a bottom surface that is parallel with the top surface of the first semiconductor die 101, the sidewall of the buffer material 201 formed by the second singulation process 301 (the sidewall facing the second semiconductor die 103) will not only be aligned with the sidewall of the first semiconductor die 101, but will also, in some embodiments, be perpendicular with the bottom surface of the buffer material 201. Such tuning of the shape of the bottom surface of the buffer material 201 allows for greater process variability and provides additional options for process integration.
In an embodiment the corner of the buffer material 201 may be curved away from a right angle such that the corner of the buffer material 201 has a first curvature. For example, the corner of the buffer material 201 may have a first curvature of between about 90 degrees and about 10 degrees, such as about 30 degrees. However, any suitable shape may be utilized.
In a particular embodiment, the buffer material 201 is chosen to be a polymer such as acrylic, which has a hydrophobicity or hydrophilic of SiN. Given this chosen material and its properties, when the buffer material 201 is dispensed the buffer material 201 is pulled out of planarity and into a curved shape. As such, the buffer material 201 may have a fifth height H5 at an edge of the buffer material 201 of between about 10 μm and about 70 μm, such as about 40 μm, and may also have a sixth height H6 at a point over an edge of the scribe region 105 of between about 10 μm and about 100 μm, such as about 50 μm. Additionally, the buffer material 201 may have a seventh height H7 at a midpoint of the buffer material 201 of between about 10 μm and about 150 μm, such as about 60 μm. However, any suitable dimensions may be utilized.
By utilizing the buffer material 201 along the corners of the first semiconductor die 101 and the second semiconductor die 103, the buffer material 201 can provide the desired buffering to help prevent cracks along the corners, but a smaller amount of the buffer material 201 is utilized. Such a reduction of materials leads to an overall reduction in cost and helps to improve throughput.
In an embodiment, a method of manufacturing a device includes forming an opening along an outside edge of a semiconductor die; overfilling at least a portion of the opening with a buffer material; and placing an underfill material adjacent to the buffer material. In an embodiment, the method further includes singulating the semiconductor die from a semiconductor wafer after the overfilling the opening and before the placing the underfill material. In an embodiment, the singulating the semiconductor die is performed by slicing through the buffer material and the semiconductor wafer with a saw. In an embodiment, the method further includes bonding the semiconductor die to a first substrate prior to the placing the underfill material adjacent to the buffer material. In an embodiment, the underfill material flows between the first substrate and the buffer material during the placing the underfill material. In an embodiment, the method further includes bonding the first substrate to a second substrate. In an embodiment, the overfilling at least the portion of the opening with the buffer material leaves the buffer material along an entire perimeter of the semiconductor die.
In another embodiment a method of manufacturing a device includes partially singulating a first wafer to form a first opening within the first wafer, the first wafer comprising a semiconductor substrate of a first material, the first material having a first property with a first value, wherein the first opening extends at least partially into both a first semiconductor device and a second semiconductor device; filling at least a portion of the first opening with a buffer material, the buffer material having the first property with a second value different from the first value; fully singulating the first wafer after the filling the first opening, wherein after the fully singulating the first wafer the buffer material remains within the first opening over the first semiconductor device; bonding the first semiconductor device to a substrate; and dispensing an underfill material between the first semiconductor device and the substrate, wherein the underfill material has the first property with a third value, the second value being between the first value and the third value. In an embodiment, the partially singulating the first wafer forms the first opening to have a beveled edge. In an embodiment, the partially singulating the first wafer forms the first opening to have perpendicular sides. In an embodiment, the first property is Young's modulus. In an embodiment, the first property is a coefficient of thermal expansion. In an embodiment, the filling at least the portion of the first opening places the buffer material into corner regions of the first semiconductor device, wherein the buffer material does not extend beyond the corner regions of the first semiconductor device. In an embodiment, the method further includes rounding the buffer material after the filling at least the portion of the first opening.
In yet another embodiment a device includes a first semiconductor device, the first semiconductor device comprising a first external connection; a buffer material located along an outside edge of the first semiconductor device; and an underfill material extending from a sidewall of the first semiconductor device, around the buffer material, and to a point between the buffer material and the first external connection. In an embodiment, the underfill material is a continuous first material. In an embodiment, the buffer material extends at least partially into the first semiconductor device. In an embodiment, the buffer material has a beveled edge within the first semiconductor device. In an embodiment, the buffer material within the first semiconductor device has a first side parallel with a top surface of the first semiconductor device and a second side at an angle to the first side. In an embodiment, the buffer material within the first semiconductor device has a sidewall which connects to the sidewall of the first semiconductor device.
In yet another embodiment a method of manufacturing a device includes providing a semiconductor wafer with a first semiconductor device and a second semiconductor device; forming a first opening over a scribe region between the first semiconductor device and the second semiconductor device; dispensing a first material into the first opening; and removing a portion of the first material in a singulation process, wherein the singulation process separates the first semiconductor device from the second semiconductor device, the singulation process leaving a first portion of the first material over the first semiconductor device, the first portion having a width of less than 200 μm. In an embodiment, the removing the portion of the first material leaves behind a perpendicular corner. In an embodiment, the removing the portion of the first material leaves behind a rounded corner. In an embodiment, the forming the first opening forms a beveled edge.
In yet another embodiment a device includes a first semiconductor device comprising a top surface and a sidewall, wherein the top surface and the sidewall are connected by a first surface that is misaligned from the top surface and the sidewall; a buffer material in physical contact with the top surface and covering the first surface, wherein a second surface of the buffer material is aligned with the sidewall; and an underfill material in physical contact with the top surface and the buffer material. In an embodiment the buffer material has a stair step shape. In an embodiment the first surface is a beveled surface.
In yet another embodiment a device includes a semiconductor device with an opening located at a corner of the semiconductor device; a buffer material located at least partially within the opening, wherein the buffer material does not extend across the semiconductor device; a substrate bonded to the semiconductor device; and an underfill material located between the semiconductor device and the substrate, wherein the buffer material has a first property with a value located between a value of the semiconductor device and a value of the underfill material. In an embodiment the buffer material has a first sidewall that is aligned with a second sidewall of the semiconductor device. In an embodiment the buffer material has a rounded surface facing away from the semiconductor device.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Huang, Sung-Hui, Wu, Chih-Wei, Kuo, Li-Chung, Shih, Ying-Ching, Huang, Kuan-Yu, Lee, Long Hua, Li, Pai Yuan
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