An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.
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1. An in-memory computation device, comprising:
a memory array, divided into p×q memory tiles, wherein p and q are positive integers larger than 1, and the memory array receives a plurality of input signals, each memory tile is respectively coupled to one of a plurality of global bit lines, where each of the memory tiles has a plurality of local bit lines coupled to a corresponding global bit line through a plurality of bit line selection switches, and the bit line selection switches are respectively controlled by a plurality of control signals to be turned on or cut off;
p×q analog-to-digital converters, respectively coupled to the global bit lines of the memory tiles, and respectively converting electrical signals on the global bit lines to generate p×q digital sub-output signals; and
a ladder adder, coupled to the analog-to-digital converters, and performing an addition operation on the sub-output signals to generate a calculation result.
2. The in-memory computation device as claimed in
3. The in-memory computation device as claimed in
p first sub-ladder adders, each of the first sub-ladder adders being respectively coupled to q of the analog-to-digital converters, and the first sub-ladder adders respectively generating p first direction calculation results; and
a second sub-ladder adder, coupled to the first sub-ladder adders, and generating the calculation result according to the first direction calculation results.
4. The in-memory computation device as claimed in
5. The in-memory computation device as claimed in
6. The in-memory computation device as claimed in
7. The in-memory computation device as claimed in
8. The in-memory computation device as claimed in
9. The in-memory computation device as claimed in
10. The in-memory computation device as claimed in
a normalization circuit, coupled to the ladder adder, and performing a normalization operation on the calculation result according to a scaling factor and a bias factor to generate an adjusted calculation result.
11. The in-memory computation device as claimed in
a quantizer, coupled to the normalization circuit, and performing a quantization operation on the adjusted calculation result according to a reference value to generate an output calculation result.
12. The in-memory computation device as claimed in
13. The in-memory computation device as claimed in
a multiplier, multiplying the calculation result and the scaling factor; and
a full adder, adding an output of the multiplier and the bias factor to generate the adjusted calculation result.
14. The in-memory computation device as claimed in
15. The in-memory computation device as claimed in
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The invention relates to an in-memory computation device, and particularly relates to an in-memory computation device capable of reducing a data storage demand.
In recent years, artificial intelligence (AI) accelerators of deep neural networks (DNN) used for edge computation have become increasingly important for integration and implementation of AI-based Internet of Things (AIoT) applications. In addition to the traditional Von Neumann computation structure, a computation in memory (CIM) framework that may further improve computation efficiency is proposed.
However, in a multiply-add operation of multiple input signals and multiple weights, a large-scale and large amount of data are inevitably generated. Therefore, how to reduce a data storage demand and power consumption required by an in-memory computation device has become an important issue for engineers of the field.
The invention is directed to an in-memory computation device, which is capable of reducing a data storage demand.
The invention provides an in-memory computation device including a memory array, p×q analog-to-digital converters (ADCs) and a ladder adder. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate p×q digital sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.
Based on the above description, in the invention, the memory array is divided into a plurality of memory tiles, and each of the memory tiles can adjust a turned-on number of the bit line selection switches to adjust a bit number of a weight. The memory tiles respectively generate a plurality of sub-output signals according to the received input signals. Then, the ladder adder is used to perform an addition operation on the sub-output signals to generate the calculation result. Through the above framework, in the in-memory computation device, data storage demand for the multiply-add operation is reduced, which effectively reduces the hardware cost and power consumption, and improves a calculation rate.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
The ADCs AD11-ADqp are respectively coupled to the memory tiles MB11-MBqp. In the embodiment, each of the memory tiles MB11-MBqp has a global bit line. The ADCs AD11-ADqp are respectively coupled to the global bit lines of the memory tiles MB11-MBqp. The ADCs AD11-ADqp respectively perform analog-to-digital conversion operations to electrical signals on the global bit lines to generate p×q sub-output signals SV11-SVqp, where the above electrical signals may be voltage signals or current signals.
In the embodiment, each of the memory tiles MB11-MBqp has a plurality of local bit lines. All of the local bit lines corresponding to the same memory tile are coupled to the corresponding global bit line.
The ladder adder 120 is coupled to the ADCs AD11-ADqp. The ladder adder 120 receives the sub-output signals SV11-SVqp, and performs an addition operation on the sub-output signals SV11-SVqp to generate a calculation result CR.
Referring to
Corresponding to the memory tiles MB11-MBqp, the in-memory computation device of the embodiment of the present invention is provided with p×q ADCs AD11-ADqp. The ADCs AD11-ADqp are respectively coupled to the global bit lines GBL_11-GBL_qp, and perform analog-to-digital conversion operations to the electrical signals on the global bit lines GBL_11-GBL_qp to respectively generate p×q sub-output signals.
The memory cells in the memory array 200 may be pre-programmed to a value of 0 or 1, and by making word line voltages received by the memory cells selected or unselected, the memory cells may provide the required weight values.
It should be noted that in the embodiment of
On the other hand, when the memory array 200 has i memory cell rows (i-bit input signals may be provided), by dividing the memory array 200 into p×q memory tiles MB11-MBqp, the number of input signals corresponding to a single memory tile may be reduced to i/p. Therefore, the maximum value of the input signals corresponding to p memory tiles in the embodiment may be p×(2i/p−1).
As described above, based on the division of p×q memory tile MB11-MBqp of the embodiment of the invention, the data storage demand of the memory array 200 having i memory cell rows and j memory cell columns may be reduced from (2i−1)×(2j−1) to p×q×(2i/p−1)×(2j/q−1). Taking i=j=8 and p=q=4 as an example, the data storage demand may be reduced from 65025 to 144.
On the other hand, please refer to
Take
Referring to
In the memory tile MB11, control terminals of the selection switches ST1 and ST2 respectively receive the input signals IN11 and IN12. Gates of the memory cells MC1 and MC2 respectively receive signals MG1 and MG2. The memory cells MC1 and MC2 form a NOR flash memory device of a 2T framework. When an in-memory computation operation is performed, the selection switches ST1 and ST2 respectively provide currents according to the input signals IN11 and IN12, and then use transduction values provided by the memory cells MC1 and MC2 as weight values to generate a multiply-add result. The local bit line BL1 may transmit a voltage generated by the multiply-add operation to the global bit line GBL.
In the embodiment, the global bit line GBL is coupled to the ADC AD11. The ADC AD11 may convert the voltage on the global bit line GBL to obtain a sub-output signal in digital format.
It should be noted that the hardware framework of the ADC AD11 may be implemented by an analog-to-digital conversion circuit that is well known by those of ordinary skills in the art, and is not specifically limited.
Moreover, in
Referring to
The first sub-ladder adder 411 performs an addition operation on the sub-output signals generated by the ADCs AD11-ADq1 to generate a first direction calculation result CDR1. Similarly, the first sub-ladder adders 412-41p may generate a plurality of first direction calculation results CDR2-CDRp through the executed addition operations.
The second sub-ladder adder 420 is coupled to the first sub-ladder adders 411-41p. The second sub-ladder adder 420 is used to perform an addition operation on the first direction calculation results CDR1-CDRp respectively generated by the first sub-ladder adders 411-41p to generate the calculation result CR.
Regarding implementation details of each of the first sub-ladder adders 411-41p and the second sub-ladder adder 420, following embodiments of
In the embodiment, the bit shifters SF11-SF1A are used to shift the received sub-output signals to a high-bit direction. In the embodiment, bit shifting numbers of the bit shifters SF11-SF1A of the first layer LA1 are equal to j/q, where j is a total number of the memory cell columns in the memory array. The full adders FAD11-FAD1A respectively receive the outputs of the bit shifters SF11-SF1A, and perform full addition operations.
It should be noted that in the embodiment, bit shifting numbers of the bit shifters of the second layer are equal to 2×j/q, and the others may be deduced by analogy. Moreover, there are q/2r full adders and q/2r bit shifters in a rth layer of the first sub-ladder adder 500, and the full adders and the bit shifters in the same layer are sequentially arranged in an interleaving manner, and are respectively coupled to output terminals of the full adders of a previous layer, where 1<r≤N.
The Nth layer LAN includes a single full adder FADN1 and a single bit shifter SFN1. A bit shifting number of the bit shifter SFN1 is equal to 2×(log2q−1)×j/q. The full adder FADN1 generates the first direction calculation result CDR1.
The hardware frameworks of the full adders FAD11-FADN1 and the bit shifters SF11-SFN1 in the embodiment may be implemented by full adding circuits and digital shift circuits that are well known to those skilled in the art, and are not specifically limited.
Moreover, in an sth layer of the second sub-ladder adder 600, there are p/2s full adders and p/2s bit shifters, and the full adders and the bit shifters in the same layer are sequentially arranged in interleaving, and are respectively coupled to the output terminals of the full adders of the previous layer, where 1<s≤M. In the last layer LBM, there is a single full adder FADM1a and a single bit shifter SFM1a. The single full adder FADM1a is used to generate the calculation result CR.
In the embodiment, the bit shifters SF11a-SF1Ba of the second sub-ladder adder 600 are used to shift the received sub-output signals to the high-bit direction. Bit shifting numbers of the bit shifters SF11a-SF1Ba in the first layer LB1 are the same, and are equal to i/p, where i is a bit number of the input signal. Moreover, bit shifting numbers of the bit shifters in the second layer of the second sub-ladder adder 600 are all 2×i/p, and the others are deduced by analogy, and a bit shifting number of the bit shifter SFM1a of the last layer LBM may be 2×(log2p−1)×i/p.
The hardware frameworks of the full adders FAD11a-FADM1a and the bit shifters SF11a-SFM1a in the embodiment may be implemented by full adding circuits and digital shift circuits that are well known to those skilled in the art, and are not specifically limited. Moreover, the hardware framework of the full adders FAD11a-FADM1a in the embodiment may be the same as or different from the hardware framework of the full adders FAD11-FADN1 in the embodiment of
Referring to
The above-mentioned scaling factor SF and the bias factor BF may be set by a designer to normalize the calculation result CR to a reasonable value range to facilitate subsequent calculations.
The quantizer 730 is coupled to the normalization circuit 720 to receive the adjusted calculation result NCR, and divides the adjusted calculation result NCR by a reference value DEN to generate an output calculation result OCR. In the embodiment, the quantizer 730 may be a divider 731. The reference value DEN may be a non-zero preset value preset by the designer, which is not specifically limited.
The hardware frameworks of the above-mentioned full adder 722, the multiplier 721, and the divider 731 may be implemented by a full adding circuit, a multiplier circuit, and a divider circuit well known in the art, which are not specifically limited.
It should be noted that the in-memory computation device 700 of the embodiment may be applied to a convolutional neural network (CNN).
In summary, in the invention, by dividing the memory array into p×q memory tiles, the ladder adder is used to complete the required multiply-add operation. Under the framework of the invention, a bit number of a weight can be adjusted according to a turned-on number of the bit line selection switches. Also, a magnitude of values generated during the calculation process may be reduced, so as to effectively reduce the data storage demand, reduce a hardware burden and increase calculation efficiency.
Hsu, Tzu-Hsuan, Hsu, Po-Kai, Lue, Hang-Ting, Yeh, Teng-Hao
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