Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.
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1. A method for forming a memory device, comprising:
providing a substrate;
forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate;
forming at least one gate line slit extending along the first direction;
forming a plurality of tiers of word lines extending along the first direction based on the alternating stack;
forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines, wherein each connection portion being sandwiched by two portions of the at least one gate line slit; and
forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.
2. The method of
alternatingly deposit a sacrificial material layer and an insulating material layer over the substrate to form a material layer comprising a plurality of tiers of sacrificial material layer/insulating material layer pairs extending along the first direction; and
patterning the material layer along the first direction and a second direction substantially perpendicular to the top surface of the substrate to form the plurality of tiers of sacrificial layer/insulating layer pairs, wherein each tier has a length longer in the first direction than an upper adjacent tier.
3. The method of
4. The method of
the at least one gate line slit divides the alternating stack into a plurality of fingers extending along the first direction, each of the plurality of fingers intersects with at least one of the plurality of semiconductor channels; and
the at least one gate line slit comprises at least one opening along the first direction, the at least one opening connecting adjacent fingers.
5. The method of
patterning the alternating stack to form at least one insulating trench extending along the first direction, the at least one insulating trench dividing the alternating stack into the plurality of fingers extending along the first direction, the at least one insulating trench surrounding the plurality of semiconductor channels, the at least one opening connecting adjacent fingers; and
filling the at least one insulating trench with silicon oxide at locations other than the at least one opening.
6. The method of
7. The method of
removing the sacrificial layer of each tier;
filling space between each tier with a conductive material; and
removing excessive conductive material on sidewalls of the alternating stack.
8. The method of
9. The method of
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method
17. The method of
18. The method of
19. The method of
forming a source region in a portion of the substrate exposed by the at least one gate line slit.
20. The method of
forming different connection portions at different tires having a same projected area on the substrate.
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This application is a divisional of U.S. patent application Ser. No. 16/046,814, filed on Jul. 26, 2018, which claims the priority of Chinese Patent Application No. 201710132422.8 filed on Mar. 7, 2017 and PCT Patent Application No. PCT/CN2018/077927 filed on Mar. 2, 2018, the entire contents of which are incorporated herein by reference.
Flash memory devices have undergone rapid development. Flash memory devices can store data for a considerably long time without powering, and have advantages such as high integration level, fast access, easy erasing, and rewriting. To further improve the bit density and reduce cost of flash memory devices, three-dimensional NAND flash memory devices have been developed.
A three-dimensional NAND flash memory device includes a stack of gate electrodes arranged over a substrate, with a plurality of semiconductor channels through and intersecting word lines, into the substrate. The bottom/lower gate electrodes function as bottom/lower selective gates. The top/upper gate electrodes function as top/upper selective gates. The word lines/gate electrodes between the top/upper selective gate electrodes and the bottom/lower gate electrodes function as word lines. The intersection of a word line and a semiconductor channel forms a memory cell. The top/upper selective gates are connected to word lines for row selection, and the bottom/lower selective gates are connected to bit lines for column selection.
Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed herein. The disclosed structures and methods provide numerous benefits, including, but not limited to simplifying the fabrication process, reducing the size of the three-dimensional memory device, and improving the space utility of the chip which the three-dimensional memory device is formed on.
In some embodiments, a three-dimensional memory device includes: a substrate, the substrate including a device region and a connection region adjacent to one another; a plurality of separate stack structures in the device region and the connection region, the stack structures including a plurality of stacking word lines (e.g., gate electrodes); and separation layers (e.g., gate line slits) over the portions of substrate between adjacent stack structures. The three-dimensional memory device also includes connection structures over the connection region and conductively connecting adjacent stack structures. The connection structure includes a plurality of repeating conductive connection portions, and the two ends of each conductive layer each connects word lines of a same height in adjacent stack structures. The three-dimensional memory device further includes a plurality of contact vias on the top surface of word lines of each height. Each contact via is conductively connected to the contacting word line, other word lines of the same height as the contacting word line, and the conductive connection portion of the same height as the contacting word line.
In some embodiments, the conductive connection portions are made of a same material as the word lines.
In some embodiments, the conductive connection portions and the word lines are made of one or more of tungsten, aluminum, and copper.
In some embodiments, the stack structures further include a first insulating portion between adjacent gate structures; and the connection structures further include a second insulating portion between adjacent conductive connection portions.
In some embodiments, the first insulating portion and the second insulating portion are made of silicon oxide.
In some embodiments, the substrate further includes a channel region adjacent to one or more of the connection region and the device region. The stack structures extend to the portion of the substrate of the channel region. In some embodiments, the three-dimensional memory device further includes a plurality of semiconductor channels over the portion of the substrate of the channel region, the semiconductor channels being through the stack structures.
In some embodiments, the three-dimensional memory device further includes a gate dielectric layer between the word lines and the semiconductor channels.
In some embodiments, a method for forming a three-dimensional memory device includes: providing a substrate, the substrate including a device region and a connection region adjacent to one another; forming a plurality of separate stack structures in the device region and the connection region, the stack structures including a plurality of stacking word lines; and forming separation layers (e.g., gate line slits) over the portions of substrate between adjacent stack structures. The method also includes forming connection structures over the connection region and conductively connecting adjacent stack structures. The connection structure includes a plurality of repeating conductive connection portions, and the two ends of each conductive layer each connects word lines of a same height in adjacent stack structures. The method further includes forming a plurality of contact vias on the top surface of word lines of each height. Each contact via is conductively connected to the contacting word line, other word lines of the same height as the contacting word line, and the conductive connection portion of the same height as the contacting word line.
In some embodiments, the stack structures further include an insulating portion between adjacent gate structures, and the connection structures further include an insulating portion between adjacent conductive connection portions. In some embodiments, the operations to form the stack structures and the insulating portions include: forming a composite structure over the portions of the substrate of the device region and the connection region. The composite structure includes a plurality of insulating portions and a plurality of sacrificial layers alternatingly arranged. The composite structure can be patterned to remove portions of the composite structure in the device region and form vertical trenches, where the vertical trenches extend through the composite structure along a direction perpendicular to the substrate. The direction the vertical trenches extend can be perpendicular to the boundary between the device region and the connection region. Further, separation layers (e.g., gate line slits) can be formed in the vertical trenches. After the separation layers are formed, sacrificial layers in the device region and the connection region can be removed, and a horizontal trench can be formed between adjacent insulating portions. Word line layers can be formed in the horizontal trenches in the device region and the connection region. The portion of the word line layers in the device region and the portion of word line layers in the connection region neighboring the separation layers can form word lines. The word line layers in the connection regions can be connected to form the conductive connection portions.
In some embodiments, patterning the composite structure includes: forming a mask layer over the composite structure, the mask layer covering the portion of the composite structure in the connection region and a portion of the composite structure in the device region. The mask layer can be used as an etch mask to etch the composite structure.
In some embodiments, etching the composite structure includes dry etch and/or wet etch.
In some embodiments, before forming the word lines, the method further includes forming a gate dielectric layer at the bottoms and the sidewalls of the portion of horizontal trenches in the device region and the connection region.
In some embodiments, the substrate further includes a channel region adjacent to one or more of the connection region and the device region. The stack structures extend to the portion of the substrate of the channel region. In some embodiments, before removing the sacrificial layers in the device region and the connection region, the method further includes forming a plurality of semiconductor channels over the portion of the substrate of the channel region, the semiconductor channels being through the stack structures
In some embodiments, the insulating portions include silicon oxide; the sacrificial layers include poly-silicon, poly-germanium, and/or silicon nitride; and the word line layers include tungsten, aluminum, and/or copper.
In some embodiments, removing the sacrificial layers in the device region and the connection region includes isotropic dry etch and/or wet etch.
In some embodiments, forming the word lines includes chemical vapor deposition (CVD).
In some embodiments, the conductive connection portions include tungsten, aluminum, and/or copper.
Compared to conventional technology, the present disclosure includes the following advantages.
Using the three-dimensional memory device provided by the present disclosure, a conductive connection portion can connect word lines of the same height in adjacent stack structures, electrical connection of word lines of the same height in adjacent stack structures can be obtained. Accordingly, word lines of the same height in adjacent stack structures can share a same contact via so that these word lines can be connected to an external circuit. Thus, the disclosed method can reduce the number of contact vias, simplify fabrication of the three-dimensional memory device, reduce the size of the memory device, and improve the space utilization of the chip.
Using the method for forming a three-dimensional memory device provided by the present disclosure, connection structures can be formed over the portion of the substrate of the connection region. The connection structure can connect adjacent stack structures. Electrical connection of word lines of the same height in adjacent stack structures can be obtained through the stack structures, and word lines of the same height in adjacent stack structures can share a same contact via so that these word lines can be connected to an external circuit. Thus, the disclosed method can reduce the number of contact vias, simplify fabrication of the three-dimensional memory device, reduce the size of the memory device, and improve the space utilization of the chip.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the common practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of illustration and discussion.
Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).
As used herein, the term “3D memory device” refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND strings) on a laterally-oriented substrate so that the memory strings extend in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.
The trend in three-dimensional NAND memory industry includes the reduction of device dimensions and the simplification of fabrication process. In a three-dimensional NAND memory device, memory cells for storing data are embedded in a stack of word lines (control gate electrodes) and the semiconductor channels formed through the stack. Each word line is separately connected to a metal contact via, which is further connected to a metal interconnect, a bit line, and/or an external circuit (e.g., control circuit), so that writing and erasing data in the memory cells can be controlled from the external circuit. Thus, the number of metal contact vias is often equal to the number of word lines. As the demand of storage capacity increases, numerous memory cells, which are formed by an increased number of word lines and semiconductor channels, are formed in a NAND memory device. Accordingly, more metal contact vias need to be formed to connect to the word lines. Meanwhile, the size of a NAND memory device keeps decreasing. It is thus more difficult to form an increased number of metal contact vias (i.e., as well as metal interconnects) in a reduced device space. For example, to arrange an increased number of metal contact vias into a smaller NAND memory device, the fabrication of the word lines and metal contact vias need to adapt to the reduced dimensions of these parts so that a desired number of word lines and metal contact vias can be formed in a smaller NAND memory device. As a result, the fabrication of the smaller NAND memory device becomes more challenging, and the space in the smaller NAND memory device is not efficiently utilized.
In the present disclosure, for ease of description, “tier” is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as “a tier,” a sacrificial layer and the underlying insulating layer can together be referred to as “a tier,” a word line and the underlying insulating layer can together be referred to as “a tier,” word lines of substantially the same height can be referred to as “a tier of word lines” or similar, and so on.
In
The present disclosure describes a three-dimensional NAND memory device in which one or more word lines of a same tier in a block are conductively connected together and the connected word lines are conductively connected to a shared metal contact via to reduce the number of metal contact vias and metal interconnects. The disclosed method and structure simplify the fabrication process to form the three-dimensional NAND memory device. A benefit, among others, of conductively connecting the word lines of a same tier is largely decreasing the number of metal interconnects connecting to control signals. In other words, in a same tier, connected word lines can share a same metal interconnect. The formed three-dimensional NAND memory device can thus have a reduced number of metal contact vias and metal interconnects, and the total number of metal contact vias is smaller than the total number of word lines. The fabrication of the three-dimensional NAND memory device can thus be simplified, the dimensions of the memory device can be further reduced, and the space in the memory device can be more efficiently utilized.
For illustrative purposes, similar or same parts in a three-dimensional NAND device are labeled using same element numbers. However, element numbers are merely used to distinguish relevant parts in the Detailed Description and do not indicate any similarity or difference in functionalities, compositions, or locations. The structures 200-1000 illustrated in
In some embodiments, base substrate 210 includes any suitable material for forming the three-dimensional memory device. For example, base substrate 210 can include silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), glass, gallium nitride, gallium arsenide, and/or other suitable III-V compound.
In some embodiments, material layer 240 includes an alternating stack of sacrificial material layers 211′ (i.e., first element or first material) and insulating material layers 212′ (i.e., second element or second material), arranged vertically (along the z-axis) over base substrate 210. For illustrative purposes, a sacrificial material layer 211′ and the corresponding underlying insulating material layer 212′ are referred to as a material pair or material pair of the same tier. Sacrificial material layers 211′ can each have the same thickness or have different thicknesses. Insulating material layers 212′ can each have the same thickness or have different thicknesses. In some embodiments, material layer 240 includes more sacrificial material layers and/or more insulating material layers than the material pairs. The additional sacrificial material layer/layers can each have a thickness same as or different from sacrificial material layers 211′ of the material pairs, and the additional insulating material layer/layers can each have a thickness same as or different from insulating material layers 212′ of the material pairs. In some embodiments, sacrificial material layers 211′ are removed subsequently for depositing gate material for forming word lines. In some embodiments, sacrificial material layers 211′ include any suitable material different from insulating material layers 212′. For example, in various embodiments, sacrificial material layers 211′ can include poly-crystalline silicon, silicon nitride, poly-crystalline germanium, and/or poly-crystalline germanium-silicon. In some embodiments, sacrificial material layers 211′ include silicon nitride. Insulating material layers 212′ can include any suitable insulating materials, e.g., silicon oxide. Material layer 240 can be formed by alternatingly depositing insulating material layers 212′ and sacrificial material layers 211′ over base substrate 210. For example, an insulating material layer 212′ can be deposited over base substrate 210, and a sacrificial material layer 211′ can be deposited on insulating material layer 212′, and so on and so forth. The deposition of sacrificial material layers 211′ and insulating material layers 212′ can be include any suitable deposition methods such CVD, physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD). In some embodiments, sacrificial material layers 211′ and insulating material layers 212′ are each formed by CVD.
For illustrative purposes, structure 200 (e.g., or base substrate 210) is divided into three regions, i.e., regions A, B, and C. In the subsequent fabrication of the three-dimensional memory structure, word lines (gate electrodes) are formed through regions A (e.g., device region), B (e.g., connection region), and C (e.g., array region) along a horizontal direction (e.g., y-axis) substantially parallel to the top surface of base substrate 210, semiconductor channels (e.g., also known as memory strings) are formed substantially in region C, and connection portions that conductively connect word lines are substantially formed in region B. It should be noted that, regions A, B, and C are presented for ease of description only, and are not intended to indicate physical division of structure 200 or dimensions of structure 200.
The staircase structure can have various stepped surfaces, referring to
Each semiconductor channel 220 can substantially have a shape of a pillar along the z-axis and can include a plurality of layers surrounding one another (not shown in the figures of the present disclosure). For example, semiconductor channel 220 can include a dielectric core positioned along the z-axis and substantially in the center of semiconductor channel 220. The dielectric core can be surrounded by a semiconductor channel film. The semiconductor channel film can be surrounded by a memory film. The dielectric core, the semiconductor channel film, and the memory film can each include one or more layers, and can together fill in a channel hole to form semiconductor channel 220. In some embodiments, the channel holes can be formed by patterning stack 240′ using a mask, e.g., etching the portions of stack 240′ exposed by a patterned mask using a suitable etching process, e.g., dry etch and/or wet etch. The channel holes can be through stack 240 and substantially into base substrate 210. The mask can be removed after the channel holes are formed.
For example, the memory film can be formed over and contacting the sidewall of a channel hole. In some embodiments, the memory film can include one or more block dielectric layers over the sidewall of the channel hole to insulate other layers in the channel hole from stack 240′ surrounding the channel hole. The memory film can also include a storage unit layer (memory layer) over and surrounded by the block dielectric layers for trapping charges and forming a plurality of charge storage regions along the z-axis. The memory film can also include a tunneling layer (e.g., tunneling dielectric) over and surrounded by the memory layer. Charge tunneling can be performed through the tunneling layer under a suitable electric bias. In some embodiments, charge tunneling can be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operation of the three-dimensional memory device.
The one or more block dielectric layers can include a first block layer which includes a dielectric metal oxide layer with a relatively high dielectric constant. The term “metal oxide” can include a metallic element and non-metallic elements such as oxygen, nitrogen, and other suitable elements. For example, the dielectric metal oxide layer can include aluminum oxide, hafnium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, silicates, nitrogen-doped compounds, alloys, etc. The first block layer can be deposited, for example, by CVD, ALD, pulsed laser deposition (PLD), liquid source misted chemical deposition, and/or other suitable deposition methods.
The one or more block dielectric layers can also include a second block layer which includes another dielectric layer over the dielectric metal oxide. The other dielectric layer can be different from the dielectric metal oxide layer. The other dielectric layer can include silicon oxide, a dielectric metal oxide having a different composition than the first block layer, silicon oxynitride, silicon nitride, and/or other suitable dielectric materials. The second block layer can be deposited, for example, by low pressure chemical vapor deposition (LPCVD), ALD, CVD, and/or other suitable deposition methods. In some embodiments, the one or more block dielectric layers include silicon oxide, which is formed by CVD.
The storage unit layer can be sequentially formed over the one or more block dielectric layers. The storage unit layer can include a charge trapping material, e.g., a dielectric charge trapping material (e.g., silicon nitride) and/or a conductive material (e.g., doped polysilicon). In some embodiments, the dielectric charge trapping material includes silicon nitride and can be formed by CVD, ALD, PVD, and/or other suitable deposition methods.
The tunneling layer can be sequentially formed over the memory layer. The tunneling layer can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides, dielectric metal oxynitride, dielectric metal silicates, alloys, and/or other suitable materials. The tunneling layer can be formed by CVD, ALD, PVD, and/or other suitable deposition methods. In some embodiments, the tunneling layer includes silicon oxide, which is formed by CVD.
The semiconductor channel film can be sequentially formed over the tunneling layer. The semiconductor channel film can include one or more layers of any suitable semiconductor materials such as silicon, silicon germanium, germanium, III-V compound material, II-VI compound material, organic semiconductor material, and/or other suitable semiconductor materials. The semiconductor channel film can be formed by a suitable deposition method such as metal-organic chemical vapor deposition (MOCVD), LPCVD, CVD, and/or other suitable deposition methods. In some embodiments, the semiconductor channel film is formed by depositing a layer of amorphous silicon using CVD, followed by an annealing process such that the amorphous silicon is converted to single-crystalline silicon. In some embodiments, other amorphous material can be annealed to be crystallized to form the semiconductor channel film.
The dielectric core can be formed over the semiconductor channel film and to fill in the space at the center of the channel hole. The dielectric core can include a suitable dielectric material such as silicon oxide and/or organosilicate glass. The dielectric core can be formed by a suitable conformal deposition method (e.g., LPCVD) and/or self-planarizing deposition method (e.g., spin coating). In some embodiments, the dielectric core includes silicon oxide and is formed by LPCVD.
In various embodiments, the number of layers, the methods to form these layers, and the specific order to form these layers may vary according to different designs and should not be limited by the embodiments of the present disclosure.
For illustrative purposes, two adjacent vertical trenches 221′ and 222′ are shown in
Vertical trenches (e.g., 221′ and 222′) can be formed by forming a mask layer over stack 240′ and patterning the mask using, e.g., photolithography, to form openings corresponding to the vertical trenches in the patterned mask layer. A suitable etching process, e.g., dry etch and/or wet etch, can be performed to remove portions of stack 240′ exposed by the openings until the vertical trenches expose base substrate 210. The mask layer can be removed after the formation of vertical trenches. In some embodiments, vertical trenches are through each of the tiers in stack 240′ and divide stack 240′ into a plurality of fingers along the y-axis. A vertical trench can include one or more openings as described above along the y-axis so that sacrificial layer/insulating layer of adjacent fingers in each tier can be connected through opening(s) of the vertical trench in between. In the present disclosure, the term “vertical” refers to “substantially perpendicular to the x-y plane,” or “substantially along the z-axis.” In some embodiments, the vertical trenches are substantially perpendicular to the top surface of base substrate 210.
In some embodiments, a vertical trench can have more than one opening to allow adjacent sacrificial layer/insulating layer of a tier in stack 240′ to be connected at more than one locations. For example, region B can include a plurality of sub-regions, separated by portions of the vertical trench, along the y-axis. That is, subsequently-formed word lines of adjacent fingers of each tier can be conductively connected at more than one locations. In some embodiments, a vertical trench can have more than one opening to allow sacrificial layer/insulating layer of some of the tiers in stack 240′ to be connected at more than one locations. For example, a vertical trench can have one or more openings distributed in region A along the y-axis. That is, subsequently-formed word lines of adjacent fingers of some of the tiers can be conductively connected at more than one locations. Details are described below.
For example, as shown in
The sacrificial layers 211 can be removed by a suitable etching process, e.g., an isotropic dry etch or a wet etch. The etching process can have sufficiently high etching selectivity of the material of sacrificial layers 211 over the materials of other parts of substrate 200, such that the etching process can have minimal impact on the other parts of substrate 200. The isotropic dry etch and/or the wet etch can remove sacrificial layers 211 in various directions to expose the top and bottom surfaces of each insulating layer 212, and the outside sidewall portions of semiconductor channels 220 previously surrounded by sacrificial layers 211. Horizontal trenches 230 can then be formed in each tier. In some embodiments, sacrificial layers 211 include silicon nitride and the etchant of the isotropic dry etch includes one or more of CF4, CHF3, C4F8, C4F6, and CH2F2. The radio frequency (RF) power of the isotropic dry etch can be lower than about 100 W and the bias can be lower than about 10 V. In some embodiments, sacrificial layers 211 include silicon nitride and the etchant of the wet etch includes phosphoric acid.
For example, as shown in
The gate material can include any suitable conductive material, e.g., tungsten, aluminum, and/or copper, for forming the word lines (i.e., gate electrodes or conductor layers). The gate material can be deposited in horizontal trenches 230 using a suitable deposition method such as CVD, sputtering, MOCVD, and/or ALD. In some embodiments, the gate material includes tungsten, which is formed by CVD.
In some embodiments, a gate dielectric material layer (not shown in the figures of the present disclosure) can be formed in a horizontal trench before the deposition of gate metal material. The gate dielectric material layer can be formed over the opposing surfaces of the adjacent insulating layers that forms the horizontal trench, the outside sidewall portions of semiconductor channels 220 between the opposing surfaces, and respective vertical trench. The gate dielectric material layer provides the base material for the subsequently-formed gate dielectric layer. The gate dielectric layer can insulate the respective word line from the underlying insulating layer 212. The gate insulating material layer can include any suitable dielectric material that is electrically insulating. For example, the gate insulating material layer can include one or more of silicon oxide, silicon nitride, and/or silicon oxynitride. In some embodiments, the gate insulating material layer can include a high-k dielectric material (k less than 3.9). In some embodiments, the gate insulating material layer can include a first silicon oxide layer, a silicon nitride layer over the first silicon oxide layer, and a second silicon oxide layer over the silicon nitride layer. The formation of the gate dielectric material layer can include one or more of CVD, PECVD, PVD, and/or ALD.
A connection portion (e.g., 223 or 224) can conductively connect the gate material deposited in the fingers adjacent/connected to the connection portion. In some embodiments, a vertical trench includes more than one opening in a tier, so that more than one connection portion is formed from the openings after the deposition of the gate metal material. In some embodiments, each tier includes the more than one sub-connection portions. The more than one sub-connection portions in one tier can enhance/improve the conductive connection between the gate materials deposited in the fingers adjacent/connected to the more than one sub-connection portions such that electrical connection between these fingers can be ensured. Accordingly, subsequently-formed word lines in the connected fingers can share a same metal contact via, which is further connected to a respective metal interconnect for transmitting electrical signals from an external circuit. The number of metal contact vias can thus be reduced and the fabrication of the three-dimensional memory device can be simplified.
For illustrative purposes, two gate line slits 221 and 222, formed from vertical trenches 221′ and 222,′ are shown in
In some embodiments, gate line slits (e.g., 221 and 222) can be formed by filling vertical trenches (e.g., 221′ and 222′) with a suitable insulating material. For example, a suitable deposition method, such as CVD, PVD, PECVD, and/or ALD, can be utilized to deposit the insulating material into the vertical trenches. The insulating material can include any suitable material that provides electric insulation between fingers. For example, the insulating material can include silicon oxide, silicon nitride, and/or silicon oxynitride. In some embodiments, the insulating material includes silicon oxide. In some embodiments, a recess etch and/or a chemical-mechanical planarization (CMP) are used to remove excessive insulating material over stack 240′ after the deposition such that gate material layer 231′-1 is exposed and the top surfaces of gate line slits level with the top surface of gate material layer 231′-1.
In some embodiments, a doping process is performed before the formation of the gate line slit to dope base substrate 210 at the bottom of a vertical trench (221′ and 222′) with dopant types opposite of base substrate 210. The doped region at the bottom of a vertical trench can form a source region. The insulating material can then be deposited at the bottom and over the sidewall of the vertical trench. Subsequently, a source contact via can be formed in the vertical trench by filling the center of the vertical trench with a source material. Thus, the insulating material can provide electrical insulation between the source contact via and the rest of stack 240′. In some embodiments, the annular bottom surface of the gate line slit contacts the source region and the source contact via is electrically connected with the source region. In some embodiments, ion implantation is utilized to dope base substrate 210 at the bottom of a vertical trench to form the source region, and the insulating material can be deposited to cover the sidewall of the vertical trench such that a cavity is formed in the vertical trench, surrounded by the insulating material. A suitable source metal can be deposited to fill in the cavity and form the source contact via. The insulating material can include silicon oxide, silicon nitride, and/or silicon oxynitride. The source metal can include tungsten and/or other suitable conductive materials. In some embodiments, a barrier layer, e.g., TiN, is formed between the gate line slit and the source contact via to prevent the source metal from penetrating into stack 240′.
In some embodiments, structure 900 can be formed from structure 800 illustrated in
As shown in
For example, structure 900 includes fingers 1, 2, and 3. Word lines 231-1-wl1, 231-2-wl1, 231-3-wl1, and 231-4-wl1 stack along the z-axis in finger 1; word lines 231-1-wl2, 231-2-wl2, 231-3-wl2, and 231-4-wl2 stack along the z-axis in finger 2; and word lines 231-1-wl3, 231-2-wl3, 231-3-wl3, and 231-4-wl3 stack along z-axis in finger 3. Word lines 231-1-wl1, 231-1-wl2, and 231-1-wl3 are in same tier 1 and are conductively connected by connection portions 223 and 224 (e.g., or the sub-connection portions of connection portions 223 and 224). Metal contact via 232-1 is formed over word line 231-1-wl2 to connect word lines 231-1-wl1, 231-1-wl2, and 231-1-wl3. Similarly, word lines 231-2-wl1, 231-2-wl2, and 231-2-wl3 are in same tier 2 and are conductively connected by connection portions 223 and 224; word lines 231-3-wl1, 231-3-wl2, and 231-3-wl3 are in same tier 3 and are conductively connected by connection portions 223 and 224; and word lines 231-4-wl1, 231-4-wl2, and 231-4-wl3 are in same tier 4 and are conductively connected by connection portions 223 and 224. Metal contact vias 232-2, 232-3, and 232-4, are respectively formed over tiers 2-4 to conductively connect to the word lines of each of the tiers. In some embodiments, two adjacent word lines 231-m-wln are conductively connected by more than one connection portions. In some embodiments, some word lines 231-m-wln of the same tier are conductively connected and the connected word lines share one or more metal contact vias 232. In some embodiments, more than one metal contact via 232 is formed to connect to the connected word lines 231-m-wln to ensure/enhance electrical connection between the connected word lines 231-m-wln and the corresponding metal interconnect(s). Depending on the designs, metal contact vias 232 can be formed at any suitable location(s) (in the x-y plane) of a tier. In some embodiments, other structures, e.g., drain region, can be formed in structure 900. For the ease of description, details of formation of the other structures are omitted in the present disclosure.
By using the disclosed method and structure illustrated in
For ease of description, connection portions formed between different fingers align substantially along the x-axis. In various other embodiments, connection portions formed between different fingers can also be staggered or misaligned along the x-axis. For example, in
In operation 1101, a substrate can be provided.
In operation 1102, a plurality of word lines extending horizontally over the base substrate and at least one connection portion conductively connecting two or more word lines can be formed.
Further, referring to
Further, referring to
Further, referring to
In operation 1103, metal contact vias can be formed on the word lines.
In various embodiments, the total number of formed metal contact vias is smaller than the total number of word lines. Thus, the number of metal contact vias can be reduced and the fabrication of the three-dimensional memory device can be simplified. The volume of the three-dimensional memory device can be further reduced and the space in the three-dimensional memory device can be more efficiently utilized.
The present disclosure describes various embodiments of three-dimensional NAND memory device and methods of making the same. In some embodiments, the three-dimensional memory device includes an a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. The memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.
In some embodiments, the method to form the three-dimensional memory device includes: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of conductor layers extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the conductor layers of the plurality of tiers of conductor layers; and forming at least one metal contact via conductively shared by connected conductor layers, the at least one metal contact via being connected to at least one metal interconnect.
In some embodiments, the three-dimensional memory device includes a substrate; a plurality of semiconductor channels, wherein one end portion of each of the plurality of semiconductor channels extends a direction substantially perpendicular to a top surface of the substrate; a drain region over the end portion of each of the plurality of semiconductor channels; a plurality of charge storage regions, each charge storage region being surrounded by a respective one of the plurality of semiconductor channels; and a source region in the substrate. The three-dimensional memory device also includes a plurality of bit lines each over a respective end portion of each of the plurality of semiconductor channels; a plurality of word lines extending along a direction substantially parallel to the top surface of the substrate and comprising an upper selective gate, a lower selective gate, and a plurality of word lines between the upper word line and the lower selective gate; a plurality of metal contact vias connecting to the plurality of word lines through a plurality of metal contact vias; and a driver circuit above the plurality of bit lines. Two or more of the plurality of word lines of substantially a same height over the substrate are conductively connected through at least one connection portion of substantially the same height. The two or more of the plurality of word lines share a metal contact via that electrically connects to a respective metal interconnect, the metal contact via being formed on one of the two or more of the plurality of word lines.
The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Xu, Qiang, He, Jia, Huo, Zongliang, Xia, Zhiliang, Yang, Yaohua, Hua, Wenyu, Liu, Fandong, Hong, Peizhen
Patent | Priority | Assignee | Title |
11792989, | Mar 07 2017 | Yangtze Memory Technologies Co., Ltd. | Word line structure of three-dimensional memory device |
Patent | Priority | Assignee | Title |
10256251, | Apr 09 2013 | SK Hynix Inc. | Nonvolatile memory device and method for fabricating the same |
10651192, | Mar 07 2017 | YANGTZE MEMORY TECHNOLOGIES CO , LTD | Word line structure of three-dimensional memory device |
8188517, | Jun 30 2009 | Hynix Semiconductor Inc. | Three-dimensional nonvolatile memory device and method for fabricating the same |
8704288, | Nov 17 2010 | Samsung Electronics Co., Ltd. | Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating semiconductor devices |
8822285, | Dec 22 2011 | SK Hynix Inc. | Nonvolatile memory device and method of manufacturing the same |
8841729, | Aug 29 2012 | Lapis Semiconductor Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
8957501, | Nov 08 2011 | Kioxia Corporation | Non-volatile semiconductor storage device |
9224751, | Mar 27 2014 | SK Hynix Inc. | Three-dimensional (3D) semiconductor device |
9306041, | Jan 17 2013 | Samsung Electronics Co., Ltd. | Vertical type semiconductor devices |
9331082, | Dec 20 2013 | SK Hynix Inc. | Three-dimensional semiconductor device |
9397043, | Mar 27 2015 | Kioxia Corporation | Semiconductor memory device |
9419013, | Oct 08 2015 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
9640549, | Nov 19 2013 | Samsung Electronics Co., Ltd. | Vertical memory device with gate lines at the same level connected |
9711529, | May 05 2015 | Semiconductor Manufacturing International (Shanghai) Corporation | 3D NAND device and fabrication method thereof |
20110169071, | |||
20110266604, | |||
20120119283, | |||
20120119287, | |||
20120181602, | |||
20130334589, | |||
20140042519, | |||
20140197481, | |||
20140329379, | |||
20150001460, | |||
20150137216, | |||
20160027730, | |||
20180130812, | |||
20190043883, | |||
CN101937919, | |||
CN102468283, | |||
CN103594473, | |||
CN103680611, | |||
CN103681860, | |||
CN104659033, | |||
CN104733462, | |||
CN105990354, | |||
CN106206447, | |||
CN106876397, | |||
JP2012146861, | |||
JP2013102008, | |||
KR1020130072522, | |||
KR1020140093044, | |||
KR1020140122057, | |||
KR1020150002947, | |||
KR1020150057254, | |||
KR1020150113265, |
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