A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.
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18. A method comprising:
forming a gate stack on a semiconductor substrate;
depositing a first spacer layer on a sidewall of the gate stack;
depositing a second spacer layer on the first spacer layer; and
depositing a third spacer layer on the second spacer layer, wherein each of the first spacer layer, the second spacer layer, and the third spacer layer comprises silicon, carbon, nitrogen, and hydrogen; and
after the third spacer layer is deposited, performing a plasma treatment on the third spacer layer.
1. A method comprising:
forming a gate stack on a substrate;
depositing a first spacer layer on a sidewall of the gate stack, the first spacer layer comprising silicon and carbon;
depositing a second spacer layer on the first spacer layer, the second spacer layer comprising silicon, carbon, and nitrogen; and
depositing a third spacer layer on the second spacer layer, the third spacer layer comprising silicon, carbon, and nitrogen, wherein a combination of the first spacer layer, the second spacer layer, and the third spacer layer has a k value of less than 4.0.
11. A method comprising:
forming a gate stack on a semiconductor substrate;
depositing a first spacer layer on a sidewall of the gate stack;
depositing a second spacer layer on the first spacer layer;
depositing a third spacer layer on the second spacer layer, wherein each of the first spacer layer, the second spacer layer, and the third spacer layer comprises silicon, carbon, nitrogen, and hydrogen, and wherein the first spacer layer, the second spacer layer, and the third spacer layer have low k values of less than 3.9; and
etching the first spacer layer, the second spacer layer, and the third spacer layer to form a gate spacer.
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
12. The method of
conducting silylated methyl to a wafer comprising the semiconductor substrate and the gate stack; and
conducting ammonia to the wafer.
13. The method of
14. The method of
15. The method of
16. The method of
performing an annealing process on the first spacer layer, the second spacer layer, and the third spacer layer, wherein the annealing process results in k values of the first spacer layer, the second spacer layer, and the third spacer layer to be lowered.
17. The method of
removing the gate stack through a plasma etching process, wherein the first spacer layer is exposed to the plasma.
19. The method of
20. The method of
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This application is a continuation of U.S. patent application Ser. No. 16/906,621, filed Jun. 19, 2020, entitled “Forming Nitrogen-Containing Low-K Gate Spacer,” which application is a divisional of U.S. patent application Ser. No. 16/057,308, filed Aug. 7, 2018, entitled “Forming Nitrogen-Containing Low-K Gate Spacer,” now U.S. Pat. No. 10,692,773 issued Jun. 23, 2020, which application claims the benefit of U.S. Provisional Application No. 62/692,088, filed Jun. 29, 2018, entitled “Forming Nitrogen-Containing Low-K Gate Spacer,” which applications are hereby incorporated herein by reference.
Transistors are basic building elements in integrated circuits. In previous development of the integrated circuits, the gates of transistors are migrating from polysilicon gates to metal gates, which are typically formed as replacement gates. The formation of the replacement gates involves forming dummy gate stacks, forming gate spacers on sidewalls of the dummy gate stacks, removing the dummy gate stacks to form openings between the gate spacers, depositing gate dielectric layers and metal layers into the openings, and then performing a Chemical Mechanical Polish (CMP) process to remove excess portions of the gate dielectric layers and the metal layers. The remaining portions of the gate dielectric layers and the metal layers are replacement gates.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A Fin Field-Effect Transistor (FinFET) and the method of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the FinFET are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. In accordance with some embodiments of the present disclosure, the gate spacer of the FinFET is doped with nitrogen and still has a lower-k value. With the reduced k value, the parasitic capacitance in the resulting circuit is reduced. With the added nitrogen, the gate spacer is more resistant to the damage incurred by the plasma used in the subsequent dummy gate removal process.
STI regions 22 may include a liner oxide (not shown), which may be a thermal oxide formed through a thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). STI regions 22 may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like.
Referring to
In above-illustrated embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins.
The materials of protruding fins 24′ may also be replaced with materials different from that of substrate 20. For example, protruding fins 24′ may be formed of Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like.
Referring to
In accordance with alternative embodiments, as shown in
Next, referring to
Further referring to
Next, NH3 is purged from the respective chamber. An ALD cycle is used to grow an atomic layer of a dielectric material. The ALD cycle includes processes 132 and 134 and the corresponding purge steps after each of processes 132 and 134. In process 132, silylated methyl is introduced. Silylated methyl may have a chemical formula as (SiCl3)2CH2.
Structure 114 reacts with silylated methyl. The resulting structure is referred to as structure 116. The N—H bonds in structure 114 are broken, and the Si—Cl bond of each of silicon atoms is broken, so that each of silicon atoms is bonded to one of nitrogen atoms. Accordingly, a silylated methyl molecule is bonded to two nitrogen atoms. In process 132, the silylated methyl may be kept in the ALD chamber for a period of time between about 5 seconds and about 15 seconds. Silylated methyl is then purged from the respective chamber.
Next, further referring to process 134 in
A second ALD cycle (process 136) is performed. The second ALD cycle 136 is performed essentially the same as the ALD cycle that includes processes 132 and 134 and the corresponding purge processes. Similarly, in the introduction of silylated methyl in the second ALD cycle, structure 118 (on wafer 10) reacts with silylated methyl. Some of the N—H bonds (structure 118) are broken, and the Si—Cl bonds (
A plurality of ALD cycles, each being essentially the same as the first ALD cycle, are then performed, during each an atomic layer (similar to atomic layer 39) of dielectric layer 37 is grown. Each of the ALD cycles cause the thickness of gate spacers 38 to increase, or example, by about 0.5 Å, and eventually gate spacer layer 37 is formed. The gate spacer layer 37 is then patterned in an anisotropic etching process, resulting in the gate spacers as shown in
It is appreciated that the processes as discussed are not limited to the formation of gate spacers, and can be used for forming dielectric layers and other vertical dielectric features.
The gate spacer layer 37 (
Referring back to
It is appreciated that in subsequent steps (
The sub layers 38A, 38B, 38C, and 38D (as deposited) may have nitrogen atomic percentages in the range between about 3 percent and about 30 percent at the time they are deposited. In accordance with some embodiments of the present disclosure, the entireties of gate spacers 38 (including all sub layers 38A, 38B, 38C, and 38D), as deposited, have a same nitrogen atomic percent. In accordance with alternative embodiments, in the direction from 38A→38B→38C→38D, the nitrogen atomic percentages reduce gradually. Due to the existence of the high-nitrogen sub layer 38A, gate spacers 38 have improved resistance to the damage of plasma in the step shown in
After the deposition (the growth) of gate spacers 38, an anneal is performed. The anneal may be performed either before or after etching gate spacer layer 37 (
The anneal temperature and the anneal duration affect the nitrogen atomic percentage and the k value of the resulting gate spacers 38. Before the anneal, the nitrogen atomic percentage is high, and the k value of gate spacers 38 is also high. For example, when the nitrogen atomic percentage is higher than about 10 percent, the k value of gate spacers 38 is higher than about 3.9. When the anneal temperature is low, with the increase in the temperature, more NH molecules are replaced with oxygen atoms, and more methylene bridges (—CH2) are broken to form Si—CH3 bonds. Accordingly, the k values become lower, and the nitrogen atomic percent also becomes lower. When temperature is further increased or the anneal is further prolonged, however, too much nitrogen atoms are lost, the k values will increase again. In accordance with some embodiments of the present disclosure, gate spacers 38 (when having low-k values) have nitrogen atomic percentage in the range between about 1 percent and about 10 percent, which is reduced from the nitrogen atomic percentage of 3 percent to 30 percent before the anneal. In accordance with some embodiments of the present disclosure, the anneal causes a first nitrogen atomic percentage in the resulting dielectric layers 38/38′ to be reduced to a second nitrogen atomic percentage, and a ratio of the second nitrogen atomic percentage to the first nitrogen atomic percentage may be in a range between about ⅕ and about ½.
Also, the reduction in the nitrogen atomic percentage results in the resistance of gate spacers to the damage of plasma to be lowered. Accordingly, it is desirable that after the anneal, the nitrogen atomic percentage is in the range between about 1 percent and about 10 percent, and may be in the range between about 1 percent and about 5 percent. Accordingly, the anneal temperature is kept in a desirable range of about 400° C. and about 500° C. to achieve low k value without compromising the gate spacer's ability for resisting to the damage of plasma. The nitrogen atomic percentages in gate spacers 38 after the anneal may be as schematically shown in
The anneal also causes the reduction in the density of gate spacers 38. For example, after the anneal, the density of gate spacers 38 may be reduced to lower than about 2.0 g/cm3, and may fall into the range between about 1.6 g/cm3 and about 1.9 g/cm3, as compared to the density higher than about 2.3 g/cm3 before the anneal.
In accordance with some embodiments of the present disclosure, after the anneal, sub layers 38A may have k values higher than other portions of gate spacers 38. Accordingly, sub layers 38A may be used as sealing layers to protect other portions such as sub layers 38B, 38C, and 38D from the damage of the plasma. After the anneal, sealing layers 38A may have a k value higher than, equal to, or lower than 3.9.
In accordance with other embodiments of the present disclosure, sub layers 38A are formed of silicon nitride, silicon oxy-carbide, or the like. The formation may also be performed using ALD, except the process gases are different. For example, when formed of silicon nitride, the process gases may include NH3 and DiChloroSilane (DCS, SiH2Cl2). The resulting sealing layers 38A have a k value higher than 4.0, and the k value may be between about 4.0 and 7.0.
In subsequently illustrated Figures, the structure shown in
Next, epitaxy regions (source/drain regions) 42 are formed by selectively growing a semiconductor material in recesses 40, resulting in the structure in
After the epitaxy step, epitaxy regions 42 may be further implanted with a p-type or an n-type impurity to form source and drain regions, which are also denoted using reference numeral 42. In accordance with alternative embodiments of the present disclosure, the implantation step is skipped when epitaxy regions 42 are in-situ doped with the p-type or n-type impurity during the epitaxy to form source/drain regions. Epitaxy source/drain regions 42 include lower portions that are formed in STI regions 22, and upper portions that are formed over the top surfaces of STI regions 22.
A cross-sectional view of the structure shown in
Next, dummy gate stacks 30, which include hard mask layers 36, dummy gate electrodes 34 and dummy gate dielectrics 32, are replaced with replacement gate stacks. The replacement step includes etching hard mask layers 36, dummy gate electrodes 34, and dummy gate dielectrics 32 as shown in
In the etching of dummy gate stacks 30, gate spacers 38, particularly sub layers 38A, are exposed to the plasma. The sub layers 38A may include nitrogen, and hence gate spacers 38 are more resistant to the damage caused by the plasma. In accordance with some embodiments of the present disclosure, gate spacers 38 have thicknesses in the range between about 20 Å and about 50 Å, and the damaged portions may have a thickness smaller than about 10 Å. The thickness of sealing layers 38A may be reduced in the etching, for example, from a value in the range between about 15 Å and about 30 Å to a value in the range between about 5 Å and about 10 Å. Since sealing layers 38A are more resistant to the damage caused by the plasma, sealing layers 38A will have some portions remaining to protect the sub-layers 38B/38C/38D after the etching, which sub-layers have lower nitrogen atomic percentages, and hence are more prone to the damage.
Next, referring to
Referring again to
Gate electrodes 56 may include a plurality of layers including, and not limited to, a Titanium Silicon Nitride (TSN) layer, a tantalum nitride (TiN) layer, a titanium nitride (TiN) layer, a titanium aluminum (TiAl) layer, an additional TiN and/or TaN layer, and a filling metal. Some of these layers define the work function of the respective FinFET. Furthermore, the metal layers of a p-type FinFET and the metal layers of an n-type FinFET may be different from each other so that the work functions of the metal layers are suitable for the respective p-type or n-type FinFETs. The filling metal may include aluminum, copper, or cobalt.
Next, as shown in
ILD 68 and etch stop layer 66 are etched to form openings. The etching may be performed using, for example, Reactive Ion Etch (RIE). In a subsequent step, as shown in
The embodiments of the present disclosure have some advantageous features. By incorporating nitrogen into gate spacers without increasing the k value of the gate spacers, the gate spacers' resistance to plasma damage (which occurs in the etching of dummy gate stacks) is improved, while the parasitic capacitance resulted from the gate spacers is at least not increased, and possibly reduced.
In accordance with some embodiments of the present disclosure, a method includes forming a dummy gate stack over a semiconductor region of a wafer; and depositing a gate spacer layer using ALD on a sidewall of the dummy gate stack, the depositing the gate spacer layer comprises performing an ALD cycle to form a dielectric atomic layer, wherein the ALD cycle comprises introducing silylated methyl to the wafer; purging the silylated methyl; introducing ammonia to the wafer; and purging the ammonia. In an embodiment, the method further comprises performing an anneal on the wafer after the gate spacer layer is formed, wherein the anneal is performed with the wafer placed in an oxygen-containing gas. In an embodiment, the anneal is performed at a temperature in a range between about 400° C. and about 500° C. In an embodiment, before the anneal, the gate spacer layer has a first nitrogen atomic percentage, and after the anneal, a portion of the gate spacer layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage. In an embodiment, before the anneal, the gate spacer layer has a first k value higher than a k value of silicon oxide, and after the anneal, a portion of the gate spacer layer has a second k value lower than the k value of silicon oxide. In an embodiment, the silylated methyl has a chemical formula of (SiCl3)2CH2. In an embodiment, the method further comprises performing an anisotropic etching on the gate spacer layer to form gate spacers on opposite sides of the dummy gate stack; and removing the dummy gate stack using dry etch, with plasma being generated in the removing the dummy gate stack. In an embodiment, the method further comprises depositing a high-k dielectric layer as a sealing layer, wherein the high-k dielectric layer comprises a portion separating the dummy gate stack from the gate spacer layer. In an embodiment, the method further comprises repeating the ALD cycle until the gate spacer layer has a thickness greater than about 20 Å.
In accordance with some embodiments of the present disclosure, a method incudes forming a dummy gate stack over a semiconductor region of a wafer; forming a dielectric layer comprising SiNOCH, wherein the dielectric layer has a first k value; and performing an anneal on the dielectric layer, wherein after the anneal, the dielectric layer has a second k value lower than the first k value. In an embodiment, the anneal is performed at a temperature in a range between about 400° C. and about 500° C. In an embodiment, the dielectric layer is formed using Atomic Layer Deposition (ALD), and the ALD comprises pulsing silylated methyl and ammonia alternatingly. In an embodiment, the anneal is performed in an oxygen-containing environment comprising H2O, O2, or oxygen radicals. In an embodiment, the anneal results in a k value of the dielectric layer to be reduced from a high-k value higher than 4.0 to a low-k value lower than 3.9. In an embodiment, the anneal results in a nitrogen atomic percentage in the dielectric layer to be reduced from a first value to a second value, wherein the first value is in a range between about 3 percent and about 30 percent, and the second value is in a range between about 1 percent and about 10 percent.
In accordance with some embodiments of the present disclosure, a device includes a semiconductor region; a gate stack over the semiconductor region; a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises SiNOCH, with the SiNOCH being a low-k dielectric material; and a source/drain region on a side of the gate spacer. In an embodiment, the gate spacer comprises an inner sidewall and an outer sidewall, and the outer sidewall is farther from the gate stack than the inner sidewall, and in a direction from the inner sidewall to the outer sidewall, nitrogen atomic percentages gradually reduce. In an embodiment, an entirety of the gate spacer from the inner sidewall to the outer sidewall comprises the SiNOCH having nitrogen atomic percentages in a range between about 1 percent and about 10 percent. In an embodiment, the gate spacer further comprises a high-k dielectric sealing layer in contact with the gate stack. In an embodiment, a nitrogen atomic percentage of the SiNOCH is in a range between about 1 percent and about 10 percent.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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