A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.
|
1. A method of using an analog-to-digital converter system that includes a delay comparator incorporated into a delay-resolving delay-to-digital backend, the delay-resolving delay-to-digital backend is coupled to preamplifiers and the method is comprising:
receiving a sampled voltage corresponding to one of an input voltage and a known voltage;
causing the preamplifiers to generate output signals based on the sampled voltage;
generating first and second signals based on the output signals;
causing the delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals;
adjusting one or more of the preamplifiers based on the single-bit digital signal.
14. An analog-to-digital converter system comprising:
a voltage-to-delay frontend having:
a sampled voltage input corresponding to one of an input voltage and a known voltage;
preamplifiers, each preamplifier having an output based on the sampled voltage; and
a folding multiplexer having an input connected to the output of each preamplifier and having a first delay signal output and second delay signal output, the first delay signal output and the second delay signal output are based on the output of one of the preamplifiers; and
a delay-resolving delay-to-digital backend having:
a first delay multiplexer having an output, a first input connected to the first delay signal output and a second input connected to a DLL signal;
a second delay multiplexer having an output, a first input connected to the second delay signal output and a second input connected to the DLL signal; and
a delay comparator having a first input connected to the output of the first delay multiplexer and a second input connected to the output of the second delay multiplexer.
21. A method of operating an analog-to-digital converter system that includes a delay comparator incorporated into a delay-resolving delay-to-digital backend, the delay-resolving delay-to-digital backend is coupled to a delay-based preamplifier array and the method is comprising:
receiving, by the delay-based preamplifier array, a sampled voltage corresponding to one of an input voltage and a known voltage, wherein the preamplifier array includes preamplifiers having different threshold voltages;
generating, by the delay-based preamplifier array, output signals based on the sampled voltage;
generating first and second signals based on the output signals;
receiving the first and second signals, by the delay comparator;
generating, by the delay comparator, a single-bit digital signal representing an order of receipt of the first and second signals;
transmitting, by the delay comparator, a residue delay signal to a succeeding delay comparator; and
subsequently, transmitting, by a calibration engine/processor, a signal to the preamplifiers to adjust one or more of the preamplifiers based on the single-bit digital signal.
2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
10. The method of
11. The method of
12. The method of
13. The method of
15. The analog-to-digital converter system of
16. The analog-to-digital converter system of
17. The analog-to-digital converter system of
18. The analog-to-digital converter system of
19. The analog-to-digital converter system of
20. The analog-to-digital converter system of
22. The method of
|
An analog-to-digital (A/D) converter (ADC) may be used to generate digital codes which represent the level of an analog signal. A radio-frequency (RF) sampling receiver may be used to receive and digitize a high frequency analog signal. An analog-to-digital converter for digitizing a signal in a radio-frequency sampling receiver may be required to operate at high speed. Analog-to-digital converters are described in United States Patent Application Publications Nos. 2012/0212358 (Shi et al.), 2015/0244386 (El-Chammas), 2019/0007071 (Nagarajan et al.), and 2019/0280703 (Naru et al.).
Some analog-to-digital converters have one or more voltage-to-delay (V2D) components and operate, at least in part, in a delay domain. Delay-based analog-to-digital converters are described in U.S. Pat. No. 10,673,452 (Soundararajan et al.), 10,673,456 (Dusad et al.), and 10,673,453 (Pentakota et al.). The entire disclosures of U.S. Pat. Nos. 10,673,452, 10,673,456, and 10,673,453 are incorporated herein by reference. In addition, the entire disclosures of the five U.S. patent applications identified below in Table 1 are incorporated herein by reference. Delay-based analog-to-digital converters may be operated, if desired, at high speed, with reduced area and power requirements.
TABLE 1 | ||
Title | Inventors | Ser. No. |
PIECEWISE CALIBRATION | Narasimhan Rajagopal, | 17/126,157 |
FOR HIGHLY NON-LINEAR | Visvesvaraya Pentakota | |
MULTI-STAGE ANALOG- | and Eeshan Miglani | |
TO-DIGITAL CONVERTER | ||
DIFFERENTIAL VOLTAGE- | Prasanth K, Eeshan | |
TO-DELAY CONVERTER | Miglani, Visvesvaraya | |
WITH IMPROVED CMMR | Appala Pentakota, | |
Kartik Goel, Venkataraman | ||
Jagannathan and Sai Aditya | ||
Nurani | ||
DELAY FOLDING SYSTEM | Eeshan Miglani, | 17/129,130 |
AND METHOD | Visvesvaraya Pentakota | |
and Chirag Chandrahas | ||
Shetty | ||
SAMPLING NETWORK | Eeshan Miglani, | 17/131,981 |
WITH DYNAMIC VOLTAGE | Visvesvaraya Pentakota | |
DETECTOR FOR DELAY | and Jaganathan | |
OUTPUT | Venkataraman | |
LOOKUP-TABLE-BASED | Visvesvaraya Pentakota, | |
ANALOG-TO-DIGITAL | Narasimhan Rajagopal, | |
CONVERTER | Chirag Shetty, Prasanth | |
K, Neeraj Shrivastava, | ||
Eeshan Miglani and | ||
Jagannathan Venkataraman | ||
The present disclosure relates to a method of using an analog-to-digital converter system, which includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the single-bit digital signal.
According to one aspect of the present disclosure, the analog-to-digital converter system includes a calibration engine/processor for establishing a known calibration voltage during calibration, for controlling a folding multiplexer and overriding its output during calibration, and for adjusting one or more preamplifiers for performance. The calibration engine/processor may include a digital processor. The present disclosure should not be limited, however, to these aspects of the present disclosure.
The present disclosure also relates to an analog-to-digital converter system which includes a voltage-to-delay frontend for receiving a sampled voltage corresponding to one of an input voltage and a known voltage, wherein the frontend includes preamplifiers for generating output signals based on the sampled voltage, and a folding multiplexer, connected to the preamplifiers, for generating first and second delay signals based on signals from one of the preamplifiers, and a delay-resolving delay-to-digital backend, connected to the frontend, for receiving the first and second delay signals from the frontend, wherein the backend includes a delay comparator for comparing timing of first and second inputs, and delay multiplexers, connected to the folding multiplexer, for generating the first and second inputs by multiplexing a third delay signal with the first and second delay signals.
The present disclosure also relates to a method of operating an analog-to-digital converter system, which includes causing a delay-based preamplifier array to receive a sampled voltage corresponding to one of an input voltage and a known voltage, wherein the preamplifier array includes preamplifiers having different threshold voltages, causing the preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, and applying the first and second signals to a delay-resolving delay-to-digital converter backend, which includes a delay comparator, causing the delay comparator to generate a single-bit digital signal representing an order of receipt of the first and second signals, causing the delay comparator to transmit a residue delay signal to a succeeding delay comparator, and causing a calibration engine/processor to transmit a signal to the preamplifiers to adjust one or more of the preamplifiers based on the single-bit digital signal.
Like elements are designated by like reference numerals and other characters throughout the drawings.
As illustrated in
The analog-to-digital converter system 10 (
An example of a folding circuit of the folding delay multiplexer 26 is illustrated in
In the example illustrated in
On the other hand, if the sampled voltage V is closer to the threshold voltage TH2 of the second preamplifier 22 than it is to any of the threshold voltages TH1 and THN of the other preamplifiers 20 and 24, then the second preamplifier 22 is the most relevant preamplifier, and the relative timings of the leading edges of the delay signals OUT_M and OUT_P correspond to the relative timings of the leading edges of the output signals OUT_M2 and OUT_P2 of the second preamplifier 22.
The analog-to-digital converter system 10 (
The analog-to-delay converter backend 28 has a first delay comparator 50 for generating a single-bit digital signal on line 52 to indicate which one of the delay signals OUT_M and OUT_P (or, which one of the signals on lines 253 and 255) reaches the delay comparator 50 first. The digital signal on line 52 is representative of the order in which signals (253 and 255) are received at the delay comparator 50. A residue delay signal is output from the first delay comparator 50, on a suitable line 55, to a second delay comparator (not illustrated in
In the illustrated configuration, the delay-resolving backend 28 includes a cascade of delay-based stages. The first delay-based stage 2070 (
During a calibration phase, a digital (whether binary, hexadecimal or other format) version of known voltage VDAC is established by a digital code generated by the calibration engine/processor 34 and output on line 36. Digital-to-analog (D/A) converter (DAC) 30 (
During the operational phase of the analog-to-digital converter system 10, the input voltage VIN is transmitted (as the sampled voltage V) to the preamplifier array 16, and a digital code representative of the input voltage VIN is generated by the calibration engine/processor 34, using digital information received from the preamplifier array 16 and the comparators of the backend 28, as described in more detail below. The representative digital code is output on an output line 39.
In the example illustrated in
The preamplifier array 16 is configured to generate digital signals that are transmitted to the calibration engine/processor 34 on a suitable line 38 (
In the example illustrated in
The folding delay multiplexer 26 (
In summary, the analog-to-digital converter system 10 has a voltage-to-delay preamplifier array frontend (including preamplifiers 16 and multiplexer 26) followed by a delay-resolving analog-to-digital backend 28. One or more elements of the frontend 16, 26 and the backend 28 may be integrated into an integrated circuit (IC) 54 and/or formed on or over a single semiconductor die (not shown in the drawings) according to various semiconductor and/or other processes. The conductive lines may be metal structures formed in insulating layers over the semiconductor die, doped regions (that may be silicided) formed in the semiconductor die, or doped semiconductor structures (that may be silicided) formed over the semiconductor die. Transistors used to implement the circuit structures of the example embodiments may be bipolar junction transistors (BJT) or metal-oxide-semiconductor field-effect transistors (MOSFET) and can be n-type or p-type. The integrated devices and elements may also include resistors, capacitors, logic gates, and other suitable electronic devices that are not shown in the drawings for the sake of clarity.
The first delay-based stage 2070 (
If desired, the analog-to-digital converter system 10 may be operated at high speed (for example, >3 GSPS) and with high performance (for example, >55 dBFS). Moreover, if desired, the analog-to-digital converter system 10 may consume less power than a conventional pipeline-based analog-to-digital converter. A delay-based analog-to-digital converter system constructed in accordance with the present disclosure may be used, if desired, to overcome barriers of speed, area, and power that are characteristic of conventional analog-to-digital converters.
The preamplifiers 20, 22 and 24 (
Threshold voltage calibration may be achieved by applying suitable offset voltages (having values of n1, n2, n3 . . . ) to the threshold voltage for the most relevant preamplifier within the array 16. The offset which causes the digital output of the first delay comparator 50 (on line 52) to toggle (that is, to change from high (“1”) to low (“0”) and vice versa) is then used as the offset to calibrate the most relevant preamplifier. The example illustrated in
As indicated above, during the calibration phase, the select signal SEL1 is high (“1”), such that the sampled voltage V equals, or corresponds to, the known voltage VDAC. In the example illustrated in
In the example illustrated in
In a different example, if it is determined that applying an offset voltage value of n1 or n2 causes the first preamplifier 20 to toggle the digital output (52) of the first delay comparator 50, then the threshold voltage TH1 of the first preamplifier 20 is corrected to TH1+n2 or TH1+n3, respectively. The offset correction process may be repeated for each one of the preamplifiers 20, 22 and 24 within the array 16. Thus, each preamplifier threshold voltage may be corrected during the calibration phase by setting the digital-to-analog converter 30 so that the known voltage VDAC equals an ideal threshold, and then correcting bulk voltage until the bit generated by the first delay comparator 50 flips from high to low (or from low to high).
After the threshold voltages TH1, TH2 and THN of the preamplifiers 20, 22 and 24 are corrected (to the extent required) by the application of suitable offsets, three adjustment processes may be performed. The three adjustment processes are as follows: One (referred to as “Process One”), maximizing (or at least increasing, if possible) gain of each one of the preamplifiers 20, 22 and 24. Two (referred to as “Process Two”), normalizing (or at least improving normalization of) gains of first and second zones within each one of the preamplifiers 20, 22 and 24. Three (referred to as “Process Three”), normalizing (or at least improving normalization of) gain across the preamplifier array 16. According to a preferred sequence, calibration and maximization of gains of the preamplifiers 20, 22 and 24 occur first, and then gain mismatches across the preamplifier array 16 are corrected. After, or in connection with, each one of the three adjustment processes, a saturation check (discussed in more detail below) may be performed and appropriate action may be taken in response to the saturation check. For example, if a saturation condition is detected, action may be taken to avoid such a condition, as discussed below.
The threshold voltage correction process and the three adjustment processes may all be performed by observing the single-bit output of the first delay comparator 50 (
The transfer function (voltage difference to delay) for each one of the preamplifiers 20, 22 and 24 is non-linear. The delay output for a given preamplifier is the difference in timing between the rising edges of its two outputs. In the example graphically represented in
Referring again to
A saturation condition (SAT) occurs when the gain of the most relevant preamplifier is so large that the later-arriving rising edge of the output signals from the most relevant preamplifier does not arrive before the end of the active phase A. An example of a saturation condition (SAT) is illustrated in
Two different processes for maximizing gains of individual preamplifiers (Process One) are illustrated in
The saturation check (Step 102) may be performed by decreasing the common current on a step-wise basis until a saturation condition is identified, and then setting the common current at the value that was applied immediately before the saturation condition was identified. The lack of a saturation condition at a particular common current may be determined by confirming that neither output from the most relevant preamplifier is low (“0”) throughout a corresponding active phase A across the whole voltage range of the preamplifier. If either of the outputs from the preamplifier is low throughout the active phase A, at any point within the voltage range of the preamplifier, then the preamplifier is subject to a saturation condition at that common current value.
After Step 102, a determination is made as to whether the second preamplifier 22 (n=2, after Step 110) is subject to a saturation condition (Step 104) when the sampled voltage V is in the vicinity of the second threshold voltage TH2. If the second preamplifier 22 is subject to a saturation condition, at any point within the range of the second preamplifier 22, the common current is increased (Step 106) until the second preamplifier 22 is not subject to a saturation condition (by repeating Steps 104 and 106 until the second preamplifier 22 is not subject to a saturation condition).
After each gain-reduction (that is, after each time through Step 106), there is a check for saturation (Step 104), and further reduction of gain (increase in current) (Step 106) if the outcome of the saturation check indicates that it is desirable, before proceeding to the next preamplifier (NO from Step 104, and incrementing value of n by proceeding through Step 112). When gains of all the preamplifiers have been adjusted, that is, when n=N, the process illustrated in
For preamplifiers of the type described herein, delay (gain)=C*V/I, where C is capacitance, I is current, and V is voltage (fixed to VDD). Thus, gain increases as current decreases, and gain increases as capacitance increases. In the illustrated configuration, current I is common across all of the preamplifiers 20, 22 and 24 (
Various suitable circuits and devices may be used to adjust the common current I. In the illustrated configuration, adjustment of the common current I may be made by a variable current circuit 600 (
The process illustrated in
Various suitable circuits and devices may be used to adjust the capacitance of each one of the preamplifiers 20, 22 and 24. In the illustrated configuration, adjustment of capacitance may be made by a variable capacitance circuit 700 (
In the
Referring again to
In the measurement system illustrated in
A similar approach is taken to measure the delay of the first delay signal OUT_M. The first delay signal OUT_M is transmitted to the delay comparator 50 (via multiplexer 250) while line 254 is connected to the comparator 50 (via multiplexer 252), via line 255, instead of the second delay signal OUT_P. The delay in line 254 is incrementally increased until the comparator 50 toggles. In this case, the delay in line 254 at which the delay comparator 50 toggles is a measure of the delay of the first output signal OUT_M. Gain of the preamplifier 20 is then calculated as a function of the two measured delays, as follows: gain=delay out/(V−TH1), where delay_out=|(doutp−doutm)|, and doutp and doutm are the measured delays of the second and first delay signals OUT_P and OUT_M.
There are also other ways to measure gain within the context of the present disclosure. For example, instead of using the delay-locked loop (DLL) line 254, the known calibration voltage may be set to Vth+X, where X is such that the preamplifier is still the relevant preamplifier. The digital code output by the delay-resolving backend 28 is then itself a representation of the gain of the preamplifier.
Referring to Process Two, there are two zones for each one of the N preamplifiers 20, 22 and 24 where, if the sampled voltage V is within one of those zones for a preamplifier, that preamplifier is the most relevant preamplifier. For each preamplifier, the sampled voltage V is greater than the threshold voltage in one of the zones, and the sampled voltage is less than the threshold voltage in the other zone. Therefore, the preamplifier array 16 has 2N zones.
By shifting the threshold voltage TH to another value THC, the relationship between the gain of the preamplifier and the voltage V can be shifted, in both zones of the preamplifier, as represented by dotted lines 174 and 176, such that gain at the opposite ends of the voltage range of the preamplifier is the same (that is, Gain_Diff=0). To achieve such normalization of gain within the two zones of a preamplifier, it is desirable to employ fine gain control which may be achieved by adjusting bulk (body) voltage. Such bulk voltage adjustment may include shifting the threshold voltage of the preamplifier by applying an offset voltage to the threshold voltage. Adjusting the bulk voltage may provide finer gain control than adjusting the capacitance of the preamplifier.
A gain normalization process is illustrated in
In operation, the gains of all of the preamplifiers within the array 16 may be determined using the measuring system illustrated in
Applying a current-kick improves the response time of a preamplifier by taking the preamplifier away from saturation. If the preamplifier without any current kick is close to saturation, then any further increase in capacitance (gain) causes saturation. Since the current kick brings the preamplifier away from saturation, the capacitance (gain) of the preamplifier can be increased without creating a saturation condition. Current kick by itself does not change the gain of the preamplifier. As illustrated in
If the current kick and the increase in capacitance create a saturation condition within the selected preamplifier (YES from Step 508), then gain of the selected amplifier is decreased by decreasing its capacitance (Step 510).
Then, if the selected preamplifier does not still have the minimum gain, the process returns to Step 500 (NO from Step 512). But if the selected preamplifier still has the least gain within the preamplifier array (YES from Step 512), then gain of the preamplifier which has the greatest gain in the array 16 is decreased by decreasing its capacitance (Step 514), and the process is returned to Step 500, unless the capacitance cannot be decreased without creating a saturation condition (YES from Step 516) in which case the process is ended (Step 502).
According to the present disclosure, it may be the case that, even after a current kick is applied and gain for a selected preamplifier is maximized by increasing its capacitance (Step 506), the selected preamplifier still has the least gain after sorting of all of the preamplifiers within the array 16. Where that is the case (YES from Step 512), the preamplifier having the maximum gain is selected and its gain is reduced by reducing its capacitance setting (Step 514), if possible without creating a saturation condition. After every change of gain (Steps 506, 514), a saturation check is done to ensure there is no saturation condition (Steps 508 and 516).
The process illustrated in
A method of using, or operating, an analog-to-digital converting system is illustrated in
Referring to
As illustrated in
In operation, the delay information developed by the preamplifiers 20, 22, 1056 and 24 is processed by first, second, third, fourth and fifth OR gates 1138, 1140, 1142, 1144 and 1146 and first, second, third, fourth and fifth AND gates 1148, 1150, 1152, 1154 and 1156. The processing causes signals generated by the preamplifiers to be folded into a single pair of signals which contain all of the information of interest. If desired, the folding circuit illustrated in
Output signals generated by the first through fourth OR gates 1138, 1140, 1142 and 1144 (on conductive lines 1158, 1160, 1162 and 1164) are input to the fifth AND gate 1156, and output signals generated by the first through fourth AND gates 1148, 1150, 1152 and 1154 (on conductive lines 1180, 1182, 1184 and 1186) are input to the fifth OR gate 1146. In each case, the timing of the output signals generated by the OR gates 1138, 1140, 1142, 1144 and 1146 corresponds to the timing of the first signal to arrive at the respective inputs of the OR gates 1138, 1140, 1142, 1144 and 1146, whereas the timing of the output signals generated by the AND gates 1148, 1150, 1152, 1154 and 1156 corresponds to the timing of the last signal to arrive at the respective inputs of the AND gates 1148, 1150, 1152, 1154 and 1156.
In operation, the preamplifier array 16 generates preamplifier outputs with early and late rising edges. When the system 10 is in the calibration phase, the folding delay multiplexer 26 transmits timing signals directly from a desired preamplifier to lines 1044 and 1190, under the control of select signal SEL2 (
In the operational phase, the fifth AND gate 1156 generates a signal (OUT_P) on conductive line 1044 which preserves the timing of the latest-arriving of the earlier-arriving signals, and the fifth OR gate 1146 generates a signal (OUT_M) on a conductive line 1190 which preserves the timing of the earliest-arriving of the later signals. A method of operating the folding circuit illustrated in
In the illustrated configuration, the second and third AND gates 2078 and 2080 are essentially identical to the first AND gate 2076, and the second and third delay comparators 2084 and 2086 are essentially identical to the first delay comparator 50. The conductive output lines 255 and 253 are both coupled to inputs of the first AND gate 2076. A first one of the conductive lines 255 is also coupled to a first input 2092 of the first delay comparator 50, and the second one of the conductive lines 253 is coupled to a threshold input 2094 of the first delay comparator 50.
An output line 57 from the first AND gate 2076 is electrically coupled to one of the inputs of the second AND gate 2078, and to the first input 2092 of the second delay comparator 2084. A conductive line 55 from the first delay comparator 50 is electrically coupled to the other one of the inputs of the second AND gate 2078, and to the threshold input 2094 of the second delay comparator 2084. In like manner, an output line 2088 from the second AND gate 2078 is electrically coupled to one of the inputs of the third AND gate 2080, and to the first input 2092 of the third delay comparator 2086, and a conductive line 2090 from the second delay comparator 2084 is electrically coupled to the other one of the inputs of the third AND gate 2080, and to the threshold input 2094 of the third delay comparator 2086.
The pattern created by the second and third stages 2072 and 2074 may be continued, if desired, for a fourth stage or for as many additional stages as desired. Each successive stage has an AND gate and a delay comparator essentially identical to the AND gates 2078 and 2080 and the delay comparators 2084 and 2086 of the second and third stages 2072 and 2074, and electrically coupled to the AND gate and delay comparator of a preceding stage in the same way that the third AND gate 2080 and the third delay comparator 2086 are electrically coupled to the second AND gate 2078 and the second delay comparator 2084.
In operation, signals AN and BN (where N=1, 2, 3 . . . for the first, second, third . . . stages 2070, 2072, 2074 . . . respectively) are applied to respective ones of the AND gates 2076, 2078 and 2080, causing the AND gates 2076, 2078 and 2080 to generate corresponding signals AN+1. For each one of the AND gates 2076, 2078 and 2080, the timing of the leading edge of signal AN+1 tracks the timing of the leading edge of the later-arriving of signals AN and BN.
In particular, for each one of the AND gates 2076, 2078 and 2080, the timing of the leading edge of signal AN+1 is equal to the timing of the leading edge of the earlier-arriving of signals AN and BN plus an amount of time (7100,
Meanwhile, signals AN and BN are also applied to the first inputs 2092 and threshold inputs 2094, respectively, of the delay comparators 50, 2084 and 2086, causing the delay comparators 50, 2084 and 2086 to generate corresponding signals BN-pi. For each one of the delay comparators 50, 2084 and 2086, the timing of the leading edge of signal BN+1 tracks the timing of the leading edge of the earlier-arriving of signals AN and BN. In particular, for each one of the delay comparators 50, 2084 and 2086, the timing of the leading edge of signal BN+1 is equal to (1) the timing of the leading edge of the earlier-arriving of signals AN and BN plus (2) a delay 7102 (
Subtracting the delay 7100 generated by the AND gate from the delay 7102 generated by the comparator yields the output signal delay T_OUT (
In operation, the first delay comparator 50 issues a first sign signal (“1” or “0”) on a first digital line 52 to the calibration engine/processor. The first sign signal is based on which one of the leading edges of the signals A1 and B1 is first received by the first delay comparator 50, such that the first sign signal reflects the order of the leading edges of signals A1 and B1 applied to the first and threshold inputs 2092 and 2094 of the first delay comparator 50. Then, the first AND gate 2076 and the first delay comparator 50 generate signals A2 and B2 which are applied to the AND gate 2078 and the delay comparator 2084 of the second stage 2072. The second delay comparator 2084 issues a second sign signal (“1” or “0”) on a second digital line 2112 to the calibration engine/processor 34. The second sign signal is based on which one of the leading edges of the signals A2 and B2 is first received by the second delay comparator 2084, such that the second sign signal reflects the order of the leading edges of the signals A2 and B2 applied to the inputs 2092 and 2094 of the second delay comparator 2084.
Then, the second AND gate 2078 and the second delay comparator 2084 generate signals A3 and B3 which are applied to the AND gate 2080 and the delay comparator 2086 of the third stage 2074. The third delay comparator 2086 issues a third sign signal (“1” or “0”) on a third digital line 2114 to the calibration engine/processor 34. The third sign signal is based on which one of the leading edges of the signals A3 and B3 is first received by the third delay comparator 2086, such that the third sign signal reflects the order of the leading edges of the signals A3 and B3 applied to the inputs 2092 and 2094 of the third delay comparator 2086. The pattern may be continued for a fourth stage or for more than four stages, as desired.
Since the delay between signals A1 and B1 can be predicted as a function of the voltage V, and vice versa, and since the delay between the signals AN+1 and BN+1 output to a successive stage can be predicted as a function of the signals AN and BN received by the preceding stage, and vice versa, the sign signals output on lines 52, 2112 and 2114 by the delay comparators 50, 2084 and 2086 of the cascade of stages 2070, 2072 and 2074 can be predicted as a function of the voltage V, and vice versa. Therefore, during the operation mode, a code made up of the sign signals may be reliably compared to a predetermined correlation to determine an approximation of the input voltage VIN.
Referring now to
The first and second conductive lines 2416 and 2418 of the comparator circuit 2083 are electrically connected to a sign-out circuit 2420 via respective third and fourth conductive lines 2422 and 2424. As illustrated in
In operation, when the delay comparator 50 is enabled by the clock signal on line 2122, a sign signal is generated within the sign-out circuit 2420 on line 52. The sign signal is forwarded to the calibration engine/processor 34 on line 52, and represents the order in which the output signals A1 and B1 arrive at the first and threshold inputs 2092 and 2094 (
The third and fourth conductive lines 2422 and 2424 are also electrically connected to a delay-out circuit 2450. As illustrated in
In operation, a delay signal B2 is generated on line 55, which is electrically connected to the drains of both of the first and second transistors 2442 and 2444 of the delay-out circuit 2450. The timing of the leading edge of the delay signal B2 on line 55 relative to the timing of the earlier-arriving of the leading edges of the signals A1 and B1 on inputs 255 and 253 is the comparator delay. The operation of the delay-out circuit 2450 is controlled by the same inverted clock signal CLKZ that is applied to the third and fourth transistors 2430 and 2432 of the sign-out circuit 2420. The inverted clock signal CLKZ is applied to the gate of the third transistor 2446 of the delay-out circuit 2450. The drain of the third transistor 2446 of the delay-out circuit 2450 is electrically connected to the drains of the first and second transistors 2442 and 2444 of the delay-out circuit 2450.
A clock-less delay comparator 50A is illustrated in
As illustrated in
At the same time, the first and second input signals A1 and B2 are applied to respective inverter gates 2456 and 2458, which generate respective inverted signals −A1, −B1. The logic levels of the inverted signals −A1, −B1 are the opposite of those of the respective input signals A1, B1. In operation, when the clock-less delay comparator 2083A is enabled, a sign signal is generated within the sign-out circuit 2420A, on line 52. As illustrated in
The inverted signals −A1 and −B1 are applied to the third and fourth transistors 2430 and 2432 of the sign out circuit 2420A, and to two extra transistors 2460 and 2462. In the illustrated configuration, the first inverted signal −A1 is applied to the fourth and first-extra transistors 2432 and 2460 of the sign-out circuit 2420A, and the third and first-extra transistors 2430 and 2460 of the sign-out circuit 2420A are electrically connected to each other in series. The second inverted signal −B1 is applied to the third and second-extra transistors 2430 and 2462 of the sign-out circuit 2420A, and the fourth and second-extra transistors 2432 and 2462 of the sign-out circuit 2420A are electrically connected to each other in series. Thus, the operation of the sign-out circuit 2420A is controlled by both of the inverted signals −A1 and −B1.
As illustrated in
Whereas the merged clock-less comparator 50A illustrated in
As illustrated in
The inverted sign signal on line 52B is inverted by one of the inverter gates 2468 to generate the non-inverted sign-out signal on line 52, which is applied to the calibration engine/processor 34 (not illustrated in
The first and second conductive lines 2416 and 2418 are electrically connected to the inverted delay-out circuit 2450B via the third and fourth conductive lines 2422 and 2424, respectively. The inverted delay-out circuit 2450B has first, second, third and fourth transistors 2492, 2494, 2496 and 2498. In operation, when the second clock-less delay comparator 50B is enabled, an inverted delay signal −B2 is generated on line 55B. The inverted delay signal −B2 is inverted by the second inverter 2470 to generate the non-inverted delay signal B2. The timing of the leading edge of the non-inverted delay signal B2 on line 55 relative to the timing of the earlier-arriving of the leading edges of the signals A1 and B1 on the comparator inputs 2092 and 2094 is the comparator delay.
As illustrated in
The present disclosure describes many advantageous features. Among other things, an algorithm has been described by which gain within two zones of a preamplifier can be normalized. The gain normalization may be performed by changing bulk voltage. Moreover, an iterative method of normalizing gain across the array 16, preferably using current kick to reduce response time, has been described. Moreover, a technique has been described herein for detecting a saturation condition of a voltage-to-delay preamplifier.
An advantageous feature described in this disclosure relates to the use of only a single-bit output to perform all calibration and adjustment processes. Moreover, the present disclosure describes a process for calculating gain of a preamplifier by, among other things, measuring delays of output signals using a delay-locked loop-generated signal. The present disclosure also describes a method of maximizing gains of preamplifiers by a combination of current adjustment and capacitance adjustment.
The analog-to-digital converter system 10 described herein may be incorporated into a radio-frequency sampling analog-to-digital converter with high operational speed and performance, and low power usage. The system 10 may be incorporated into a highly integrated radio-frequency sampling based transceiver for use in wireless infrastructure, especially for higher bandwidth multi-band applications. Among other things, devices constructed in accordance with the present disclosure may have low power consumption and small area requirements.
In general, it is possible to reduce non-linearity in certain devices by over-designing the devices. However, the over-design approach tends to undesirably increase area and power requirements, sometimes drastically, especially to accommodate a wide range of temperatures. And over-designing may not be scalable at lower process nodes, since the analog domain at such nodes tends to be more non-linear. Moreover, in general, it may be possible to perform calibration using a factory trim process. However, it may be difficult to trim later stages of an analog-to-digital device where such stages operate in a highly non-linear manner. It may not be possible to track changes, especially in the later stages, as needed for a factory trim process.
The present disclosure represents an improvement over the concept of reducing non-linearity by over-design, because over-design may increase area and power drastically to support wider temperature, and is not scalable at lower process nodes where analog processing is more non-linear. Methods performed in connection with the present disclosure may also represent an improvement over factory-trimming processes, which may still require over-design since trimming is not accurate and cannot track temperature.
What have been described above are examples. This disclosure is intended to embrace alterations, modifications, and variations to the subject matter described herein that fall within the scope of this application, including the appended claims. As used herein, the term “includes” means including but not limited to. The term “based on” means based at least in part on. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements.
Shetty, Chirag Chandrahas, Miglani, Eeshan, Rajagopal, Narasimhan, Shrivastava, Neeraj, K, Prasanth
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
10284188, | Dec 29 2017 | Texas Instruments Incorporated | Delay based comparator |
10673452, | Dec 12 2018 | Texas Instruments Incorporated | Analog-to-digital converter with interpolation |
10673453, | Dec 31 2018 | Texas Instruments Incorporated | Delay-based residue stage |
10673456, | Dec 31 2018 | Texas Instruments Incorporated | Conversion and folding circuit for delay-based analog-to-digital converter system |
10778243, | Dec 31 2018 | Texas Instruments Incorporated | Delay-based residue stage |
10958258, | Dec 29 2017 | Texas Instruments Incorporated | Delay based comparator |
11316525, | Jan 26 2021 | Texas Instruments Incorporated | Lookup-table-based analog-to-digital converter |
11316526, | Dec 18 2020 | Texas Instruments Incorporated | Piecewise calibration for highly non-linear multi-stage analog-to-digital converter |
4612533, | Jun 12 1985 | The United States of America as represented by the Secretary of the Air | Harmonic distortion reduction technique for data acquistion |
4899071, | Aug 02 1988 | Standard Microsystems Corporation | Active delay line circuit |
4928103, | Sep 18 1989 | Analog Devices, Inc. | Parallel analog-to-digital converter using 2(n-1) comparators |
5317721, | Nov 06 1989 | RPX Corporation | Method and apparatus to disable ISA devices for EISA addresses outside the ISA range |
5495247, | Aug 20 1992 | Fujitsu Semiconductor Limited | Analog to digital convertor |
5563533, | Feb 28 1995 | Motorola, Inc. | Method and apparatus for a high speed low power comparator using positive feedback |
5821780, | Jun 30 1995 | NEC Electronics Corporation | Comparator operable with low power supply voltage |
6002352, | Jun 24 1997 | International Business Machines Corporation | Method of sampling, downconverting, and digitizing a bandpass signal using a digital predictive coder |
6046612, | Jul 27 1998 | National Semiconductor Corporation | Self-resetting comparator circuit and method |
6069579, | Feb 27 1998 | Renesas Electronics Corporation | Folding type A/D converter and folding type A/D converter circuit |
6124746, | Jul 31 1997 | STMICROELECTRONICS S A | Adjustable delay circuit |
6144231, | Nov 23 1998 | Qualcomm INC | High speed dynamic latch comparator |
6314149, | Apr 16 1998 | Texas Instruments Incorporated | Method and apparatus for rephasing a voltage controlled clock, or the like |
6377200, | Jun 16 1999 | SAMSUNG ELECTRONICS CO , LTD | Analog-to-digital converter |
6822596, | Nov 05 2001 | austriamicrosystem AG | Analog/digital converter that employs phase comparison |
6836127, | Jul 27 2001 | VALTRUS INNOVATIONS LIMITED | Dual switching reference voltages |
6857002, | Jul 05 2000 | Cirrus Logic, INC | Integrated circuit with a mode control selecting settled and unsettled output from a filter |
7046179, | Feb 13 2004 | National Semiconductor Corporation | Apparatus and method for on-chip ADC calibration |
7233172, | May 15 2001 | Fujitsu Limited | Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude |
7262724, | Mar 31 2005 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | System and method for adjusting dynamic range of analog-to-digital converter |
7379007, | May 27 2005 | Renesas Electronics Corporation | A/D converter, A/D converter apparatus, and sampling clock skew control method |
7405689, | Jan 05 2005 | Exar Corporation | Predictive analog to digital converters and methods of using |
7501862, | Jun 22 2007 | Himax Technologies Limited | Comparator with low offset voltage |
7525471, | Feb 28 2007 | Exar Corporation | Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS |
7557746, | Dec 13 2007 | MORGAN STANLEY SENIOR FUNDING, INC | Time domain interpolation scheme for flash A/D converters |
7737875, | Dec 13 2007 | MORGAN STANLEY SENIOR FUNDING, INC | Time interpolation flash ADC having automatic feedback calibration |
7738265, | Aug 29 2005 | Austriamicrosystems AG | Control system for a voltage converter and method |
7847576, | Feb 26 2009 | Advantest Corporation | Comparator with latching function |
7884748, | Oct 25 2006 | COMMISSARIAT A L ENERGIE ATOMIQUE | Ramp-based analog to digital converters |
7916064, | Jan 22 2009 | NATIONAL TAIWAN UNIVERSITY | Voltage-to-time converter, and voltage-to-digital converting device having the same |
7919994, | Oct 02 2008 | Robert Bosch GmbH | Reception comparator for signal modulation upon a supply line |
8089388, | Jan 28 2010 | LG Display Co., Ltd. | Folding analog-to-digital converter |
8130130, | Mar 25 2009 | Fujitsu Limited | Comparison circuit and analog-to-digital conversion device |
8183903, | Dec 03 2009 | JPMORGAN CHASE BANK, N A , AS SUCCESSOR AGENT | Signal interpolation methods and circuits |
8373444, | Sep 23 2009 | POSTECH ACADEMY - INDUSTRYF OUNDATION | Time-domain voltage comparator for analog-to-digital converter |
8421664, | Nov 02 2010 | Korea Electronics Technology Instutitute; Korea Advanced Institute of Science and Technology | Analog-to-digital converter |
8514121, | Mar 26 2012 | MEDIATEK INC. | Comparison circuits |
8773169, | Oct 22 2010 | Analog Devices, Inc.; Analog Devices, Inc | High frequency signal comparator for SHA-less analog-to-digital converters |
8836375, | Sep 06 2012 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Continuously self-calibrated latched comparator |
8896476, | Jan 25 2013 | TECHNISCHE UNIVERSITEIT EINDHOVEN | Data-driven noise reduction technique for analog to digital converters |
9369137, | Nov 04 2014 | SOCIONEXT INC. | Clock generation circuit, successive comparison A/D converter, and integrated circuit device |
9379007, | Mar 23 2012 | ALSEPHINA INNOVATIONS INC | Electromigration-resistant lead-free solder interconnect structures |
9455695, | Aug 29 2014 | International Business Machines Corporation | High-speed comparator for analog-to-digital converter |
9467160, | Nov 11 2014 | MEDIATEK INC. | Flash ADC with interpolators |
9685971, | May 08 2014 | Olympus Corporation | Successive comparison A/D conversion circuit |
9742424, | Jan 07 2016 | Nanyang Technological University | Analog-to-digital converter |
9917590, | Jun 03 2015 | MARVELL INTERNATIONAL LTD; CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Delay locked loop |
20050104626, | |||
20060158365, | |||
20080297381, | |||
20090302888, | |||
20100085101, | |||
20100085232, | |||
20120105264, | |||
20120176158, | |||
20120212358, | |||
20120326904, | |||
20130009796, | |||
20130021118, | |||
20130169463, | |||
20140361917, | |||
20150008894, | |||
20150244386, | |||
20150260552, | |||
20190007071, | |||
20190280703, | |||
20200195268, | |||
20200204184, | |||
JP5206801, | |||
KR20000028857, | |||
KR2001044806, | |||
KR20020015863, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Dec 24 2020 | Texas Instruments Incorporated | (assignment on the face of the patent) | ||||
Feb 28 2021 | RAJAGOPAL, NARASIMHAN | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 059303 | 0077 | |
Feb 28 2021 | K, PRASANTH | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 059303 | 0077 | |
Mar 30 2021 | SHETTY, CHIRAG CHANDRAHAS | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 059303 | 0077 | |
Jun 23 2021 | MIGLANI, EESHAN | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 059303 | 0077 | |
Oct 07 2021 | SHRIVASTAVA, NEERAJ | Texas Instruments Incorporated | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 059303 | 0077 |
Date | Maintenance Fee Events |
Dec 24 2020 | BIG: Entity status set to Undiscounted (note the period is included in the code). |
Date | Maintenance Schedule |
Sep 06 2025 | 4 years fee payment window open |
Mar 06 2026 | 6 months grace period start (w surcharge) |
Sep 06 2026 | patent expiry (for year 4) |
Sep 06 2028 | 2 years to revive unintentionally abandoned end. (for year 4) |
Sep 06 2029 | 8 years fee payment window open |
Mar 06 2030 | 6 months grace period start (w surcharge) |
Sep 06 2030 | patent expiry (for year 8) |
Sep 06 2032 | 2 years to revive unintentionally abandoned end. (for year 8) |
Sep 06 2033 | 12 years fee payment window open |
Mar 06 2034 | 6 months grace period start (w surcharge) |
Sep 06 2034 | patent expiry (for year 12) |
Sep 06 2036 | 2 years to revive unintentionally abandoned end. (for year 12) |