An ultrasound device, including a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator including a plurality of attenuator stages, the attenuator configured to produce an output signal that is an attenuated version of the input signal.
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11. A method of operation of a handheld ultrasound probe, comprising:
receiving, by ultrasound transducers of the ultrasound probe, ultrasound waves reflected from a target;
outputting, by receive circuitry coupled to the ultrasound transducers, a signal based on the received reflected ultrasound waves received by the ultrasound transducers;
attenuating, by a variable attenuator, the signal and outputting an attenuated signal that varies with time based on control signals received from control circuitry coupled to the variable attenuator, wherein the attenuating of the signal comprises controlling a plurality of selectable attenuation circuits of the variable attenuator, wherein each of first and second attenuation circuits of the plurality of selectable attenuation circuits comprises a switch and a respective resistor, and wherein the switch is controllable by the control signals received from the control circuitry; and
digitizing the attenuated signal and outputting a digitized signal.
1. A handheld ultrasound probe, comprising:
ultrasound transducers configured to transmit ultrasound waves and to receive reflected ultrasound waves from a target;
receive circuitry coupled to the ultrasound transducers and configured to output a signal based on the received reflected ultrasound waves received by the ultrasound transducers;
a variable attenuator coupled to control circuitry and configured to receive the signal from the receive circuitry and to output an attenuated signal that varies with time based on control signals received from the control circuitry, the variable attenuator comprising a plurality of selectable attenuation circuits, wherein each of first and second attenuation circuits of the plurality of selectable attenuation circuits comprises a switch and a respective resistor, and wherein the switch is controllable by the control signals received from the control circuitry; and
digitizing circuitry configured to digitize the attenuated signal and to output a digitized signal.
2. The ultrasound probe of
3. The ultrasound probe of
4. The ultrasound probe of
the variable attenuator comprises first and second legs, and
the plurality of selectable attenuation circuits are arranged in parallel between the first and second legs.
5. The ultrasound probe of
6. The ultrasound probe of
7. The ultrasound probe of
the variable attenuator comprises first and second legs, and
the plurality of selectable attenuation circuits are arranged in series on the first leg.
8. The ultrasound probe of
9. The ultrasound probe of
10. The ultrasound probe of
12. The method of
13. The method of
14. The method of
the variable attenuator comprises first and second legs, and
the plurality of selectable attenuation circuits are arranged in parallel between the first and second legs.
15. The method of
16. The method of
17. The method of
the variable attenuator comprises first and second legs, and
the plurality of selectable attenuation circuits are arranged in series on the first leg.
18. The method of
19. The method of
20. The method of
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This Application is a Continuation claiming the benefit under 35 U.S.C. § 120 of U.S. application Ser. No. 16/109,437, filed Aug. 22, 2018, and entitled “TIME GAIN COMPENSATION CIRCUIT AND RELATED APPARATUS AND METHODS,” now U.S. Pat. No 11,215,703, which is hereby incorporated by reference herein in its entirety.
U.S. application Ser. No. 16/109,437 is a Continuation claiming the benefit under 35 U.S.C. § 120 of U.S. application Ser. No. 14/957,443, filed Dec. 2, 2015, under Attorney Docket No. B1348.70022US00 and entitled “TIME GAIN COMPENSATION CIRCUIT AND RELATED APPARATUS AND METHODS,” now U.S. Pat. No. 10,082,488, which is hereby incorporated by reference herein in its entirety.
The present application relates to ultrasound devices having a time gain compensation circuit.
Ultrasound devices may be used to perform diagnostic imaging and/or treatment. Ultrasound imaging may be used to see internal soft tissue body structures. Ultrasound imaging may be used to find a source of a disease or to exclude any pathology. Ultrasound devices use sound waves with frequencies which are higher than those audible to humans. Ultrasonic images are made by sending pulses of ultrasound into tissue using a probe. The sound waves are reflected off the tissue, with different tissues reflecting varying degrees of sound. These reflected sound waves may be recorded and displayed as an image to the operator. The strength (amplitude) of the sound signal and the time it takes for the wave to travel through the body provide information used to produce an image.
Many different types of images can be formed using ultrasound devices. The images can be real-time images. For example, images can be generated that show two-dimensional cross-sections of tissue, blood flow, motion of tissue over time, the location of blood, the presence of specific molecules, the stiffness of tissue, or the anatomy of a three-dimensional region.
According to an aspect of the present application, there is provided an ultrasound device, comprising a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator comprising a plurality of binary attenuator stages, the attenuator configured to produce an output signal that is an attenuated version of the input signal.
According to an aspect of the present application, there is provided an ultrasound device, comprising a profile generator, an encoder configured to receive a profile signal from the profile generator, and an attenuator configured to receive a signal representing an output of an ultrasound sensor and coupled to the encoder to receive a control signal from the encoder, the attenuator comprising a plurality of stages, each stage in the plurality of stages having a predetermined attenuation, the attenuator configured to produce an output signal that is an attenuated version of the input signal.
Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.
The inventors have recognized and appreciated that the power consumption and the accuracy associated with time gain compensation circuits may be improved by replacing variable amplifiers with amplification circuits comprising variable attenuators and fixed gain amplifiers. This approach can significantly simplify the amplifier design shifting the problem from the design of an active circuit to the design of a passive circuit.
Aspects of the present application relate to variable attenuator circuits for time gain compensation comprising a plurality of resistors that are individually digitally enabled. Because the circuits comprise fixed resistors, high degrees of attenuation accuracy, and consequently high degrees of gain accuracy, may be accomplished. Furthermore, the source of power consumption associated with the variable attenuator is the digital circuits enabling the resistors.
The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect.
The circuit 100 further comprises N circuitry channels 104a . . . 104n. The circuitry channels may correspond to a respective ultrasonic transducer 102a . . . 102n. For example, there may be eight ultrasonic transducers 102a . . . 102n and eight corresponding circuitry channels 104a . . . 104n. In some embodiments, the number of ultrasonic transducers 102a . . . 102n may be greater than the number of circuitry channels.
The circuitry channels 104a . . . 104n may include transmit circuitry, receive circuitry, or both. The transmit circuitry may include transmit decoders 106a . . . 106n coupled to respective pulsers 108a . . . 108n. The pulsers 108a . . . 108n may control the respective ultrasonic transducers 102a . . . 102n to emit ultrasound signals.
The receive circuitry of the circuitry channels 104a . . . 104n may receive the electrical signals output from respective ultrasonic transducers 102a . . . 102n. In the illustrated example, each circuitry channel 104a . . . 104n includes a respective receive switch 110a . . . 110n and an amplifier 112a . . . 112n. The receive switches 110a . . . 110n may be controlled to activate/deactivate readout of an electrical signal from a given ultrasonic transducer 102a . . . 102n. More generally, the receive switches 110a . . . 110n may be receive circuits, since alternatives to a switch may be employed to perform the same function. The amplifiers 112a . . . 112n may be trans-impedance amplifiers (TIAs).
The circuit 100 further comprises an averaging circuit 114, which is also referred to herein as a summer or a summing amplifier. In some embodiments, the averaging circuit 114 is a buffer or an amplifier. The averaging circuit 114 may receive output signals from one or more of the amplifiers 112a . . . 112n and may provide an averaged output signal. The averaged output signal may be formed in part by adding or subtracting the signals from the various amplifiers 112a . . . 112n. The averaging circuit 114 may include a variable feedback resistance. The value of the variable feedback resistance may be adjusted dynamically based upon the number of amplifiers 112a . . . 112n from which the averaging circuit receives signals. The averaging circuit 114 is coupled to an auto-zero block 116.
The auto-zero block 116 is coupled to a time gain compensation circuit 118 which includes an attenuator 120 and a fixed gain amplifier 122. Attenuator 120, as well as attenuator 200 of
The time gain compensation circuit 118 is coupled to an ADC 126 via ADC drivers 124. In the illustrated example, the ADC drivers 124 include a first ADC driver 125a and a second ADC driver 125b. The ADC 126 digitizes the signal(s) from the averaging circuit 114.
While
The components of
According to an embodiment, the components of
The gain of fixed gain amplifier 122 may have values between approximately 1 dB and 100 dB, between approximately 3 dB and 30 dB, between approximately 5 dB and 20 dB, or any other value or range of values. Other values are also possible.
In some embodiments fixed gain amplifier 122 has a gain of 20 dB.
The attenuation of variable attenuator 120 may have values between approximately 1 dB and 100 dB, between approximately 3 dB and 30 dB, between approximately 5 dB and 20 dB, or any other value or range of values. Other values are also possible.
Circuit 200, shown in
Each switch 206i may have 2 possible states: closed or open. When switch 206i is closed, circuit 210i represents a resistor having a resistance equal to the sum of resistors 205i and 207i.Contrarily, when switch 206i open, circuit 210i has a resistance equal to infinite. According to some embodiments, the overall resistance seen by the input signal may be varied by changing the state of switches 206i. In this configuration, the overall resistance may be defined by a digital code of m bits in length, where a bit equal to 1 represents a closed switch and a bit equal to 0 represents an open switch. Each switch 206i may assume a closed or open state, independently of the state of the other switches.
Resistors 203 and 204, and each resistor 205i and 207i may have values between approximately 1Ω and 10Ω, between approximately 100Ω and 100 MΩ, between approximately 1 KΩ and 1 MΩ, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 205i and 207i may be chosen to progressively increase or decrease by a constant factor x as a function of i. For example, if resistor 205i is set to R, resistor 2052 may be equal to xR, resistor 2053 may be equal to x2R, and resistor 205m may be equal to xm−1R. Factor x may have values between approximately 0.001 and 1000, between approximately 0.1 and 10, between approximately 0.5 and 2, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 205, are all equal to each other and resistors 207i are all equal to each other, for any value of i.
In some embodiments, a fixed attenuation stage may be obtained by closing some or all switches 206i and by setting resistors 203, 204 and each of the resistors 205i and 207i to a predefined value.
Circuit 220, shown in
Each switch 226i and 228i may have 2 possible states: closed or open. According to some embodiments, the overall resistance seen by the input signal may be varied by independently adjusting the state of each switch 226i and 228i. As in the parallel circuit described previously, a bit sequence may be used to determine the state of each switch.
Resistors 223 and 224, and each resistor 225i and 227i may have values between approximately 1Ω and 10 GΩ, between approximately 100Ω and 100 MΩ, between approximately 1 KΩ and 1 MΩ, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 225i and 227i may be chosen to progressively increase or decrease by a constant factor x as a function of i. For example, if resistor 225i is set to R, resistor 2252 may be equal to xR, resistor 2253 may be equal to x2R, and resistor 225m may be equal to xm−1R. Factor x may have values between approximately 0.001 and 1000, between approximately 0.1 and 10, between approximately 0.5 and 2, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 225i are all equal to each other and resistors 227i are all equal to each other, for any value of i.
In some embodiments, a fixed attenuation stage may be obtained by closing some or all switches 226i and 228i and by setting resistors 223, 224 and each of the resistors 225i and 227i to a predefined value.
While circuit 200 represents a differential parallel embodiment of attenuator 120, circuit 220 represents a differential series embodiment of attenuator 120. As may be appreciated by a person of ordinary skills in the art, any suitable combination of parallel and series arrangements may be used.
Circuit 240, shown in
Each switch 246i may have 2 possible states: closed or open. According to some embodiments, the overall resistance seen by the input signal may be varied by independently adjusting the state of each switch 246i. As in the parallel circuits described previously, a bit sequence may be used to determine the state of each switch.
Resistors 243, and each resistor 245i may have values between approximately 1Ω and 10 GΩ, between approximately 100Ω and 100 MΩ, between approximately 1 KΩ and 1 MΩ, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 245i may be chosen to progressively increase or decrease by a constant factor x as a function of i. For example, if resistor 2451 is set to R, resistor 2452 may be equal to xR, resistor 2453 may be equal to x2R, and resistor 245m may be equal to xm−1R. Factor x may have values between approximately 0.001 and 1000, between approximately 0.1 and 10, between approximately 0.5 and 2, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 245i are all equal to each other.
In some embodiments, a fixed attenuation stage may be obtained by closing each switch 246i and by setting resistors 243 and each of the resistors 245i to a predefined value, for any value of i.
Circuit 260, shown in
Each switch 266i may have 2 possible states: closed or open. According to some embodiments, the overall resistance seen by the input signal may be varied by independently adjusting the state of each switch 266i. As in the parallel circuits described previously, a bit sequence may be used to determine the state of each switch.
Resistors 263, and each resistor 265i may have values between approximately 1Ω and 10 GΩ, between approximately 100Ω and 100 MΩ, between approximately 1 KΩ and 1 MΩ, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 265i may be chosen to progressively increase or decrease by a constant factor x as a function of i. For example, if resistor 2651 is set to R, resistor 2652 may be equal to xR, resistor 2653 may be equal to x2R, and resistor 265m may be equal to xm−1R. Factor x may have values between approximately 0.001 and 1000, between approximately 0.1 and 10, between approximately 0.5 and 2, or any other value or range of values. Other values are also possible.
In some embodiments, resistors 265i are all equal to each other.
According to some embodiments, a fixed attenuation stage may be obtained by closing some or all switches 266i and by setting resistors 263 and each of the resistors 265i to a predefined value, for any value of i.
While circuit 240 represents a single-ended parallel embodiment of attenuator 120, circuit 260 represents a single-ended series embodiment of attenuator 120. As may be appreciated by a person of ordinary skills in the art, any suitable combination of parallel and series arrangements may be used.
As may readily be appreciated by a person of ordinary skill in the art, while
As may further be appreciated by a person of ordinary skill in the art, while
In some embodiments, flip-flops 317i, where i may assume any value between 1 and m, may be used to set the state of complementary switches 206i. The output port of each flip-flop 317i may be connected to the gate of each nMOS transistor 310i. As further described below, in some embodiments, instead of connecting the gates of the two transistors through inverters 315i the Q port of each flip-flop 317i may be connected to the gate of each nMOS transistor 310i while the
In some embodiments, flip-flops 317i may be controlled by encoder 350. In turn, encoder 350 may be controlled by profile generator 351. According to some aspects of the present application, profile generator 351 may be a circuit that generates a target time gain compensation response and sources the control signals necessary to track the desired profile. The target time gain compensation response may be manually defined by a user, automatically defined by a computer, or defined in any other suitable manner.
In some embodiments, 2-to-1 multiplexers 470i may be used to set the state of each bit of shift register 402. Each multiplexer 470i may have two input ports Ai and Bi and one output port Zi. When the value of the Inc_Dec is set to 0, Zi may assume the value of Ai, independently of the value of Bi. Contrarily, when the value of the Inc_Dec is set to 1, Zi may assume the value of Bi, independently of the value of Ai. However any other suitable logic may be used. In some embodiments, ports A1 and B4 may be set by the profile generator, while all other port Ai and Bi are set by the output Q of the neighboring flip-flop. In a non-limiting example, Ai may be set by Qi−1 and Bi may be set by Qi+1.
In some embodiments, when Inc_Dec signal 491 is set to 0 and the register is triggered by shift signal 490, the bits stored in the register may shift from the least significant flip-flop 3171 to the most significant flip-flop 3174. Contrarily, when Inc_Dec is set to 1 and the register is triggered by shift signal 490, the bits stored in the register may shift from the most significant flip-flop 3174 to the least significant flip-flop 3171.
In some embodiments, each binary attenuation stage can provide about 0.2 dB of attenuation.
In some other embodiments, it may be desirable to generate a gain response that causes the compensated signal to have any suitable time-dependent behavior. For example, in order to improve the contrast of an ultrasound image, it may be desirable to magnify the response of one layer of the target while attenuating the response of another layer. The time gain compensation response may be manually defined by the user, automatically defined by a computer, or defined in any other suitable manner.
Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described.
As described, some aspects may be embodied as one or more methods. The acts performed as part of the method(s) may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.
The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases.
As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
As used herein, the term “between” used in a numerical context is to be inclusive unless indicated otherwise. For example, “between A and B” includes A and B unless indicated otherwise.
In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.
Ralston, Tyler S., Chen, Kailiang
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