The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. The first transistor is controlled by a enable signal. The second transistor is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit generates the second control signal according to the first control signal and the enable signal.
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1. An interface circuit, comprising:
a first transistor, wherein a first end of the first transistor receives a power voltage, and the first transistor is controlled by a enable signal;
a second transistor, coupled between an output end of the interface circuit and a reference ground end, and being controlled by a first control signal;
a first switch, coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal;
a first logic circuit, coupled to the second transistor, generating the first control signal according to the enable signal and at least one indication signal; and
a second logic circuit, coupled to the first logic circuit and the first switch, wherein the second logic circuit generates the second control signal according to the first control signal and the enable signal,
wherein when the first transistor is turned-on according to the enable signal, the second transistor is turned-on according to the first control signal, and the first switch is cut-off according to the second control signal.
2. The interface circuit according to
3. The interface circuit according to
an inverter, having an input end for receiving the enable signal, and having an output end being coupled to a control end of the first transistor.
4. The interface circuit according to
5. The interface circuit according to
an OR gate, performing an OR logic operation on the at least one indication signal to generate an operation result; and
an AND gate, performing an AND logic operation on the operation result and the enable signal to generate the first control signal.
6. The interface circuit according to
a second switch, coupled between the output end of the interface circuit and the second transistor, wherein the second switch is controlled by the second control signal.
7. The interface circuit according to
8. The interface circuit according to
a first resistor, coupled between the output end of the interface circuit and the first switch in series; and
a second resistor, coupled between the output end of the interface circuit and the second switch in series.
9. The interface circuit according to
10. The interface circuit according to
11. The interface circuit according to
12. The interface circuit according to
an electrostatic discharge (ESD) protection circuit, coupled to the pad.
13. The interface circuit according to
14. The interface circuit according to
an output switch, coupled between the output end of the interface circuit and an external circuit, and controlled by the enable signal.
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The present invention generally relates to an interface circuit, and more particularly to the interface circuit with weak pull-up structure.
Please refer to
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The present invention provides an interface circuit which can overcome process variation and provide correct output signal.
The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. A first end of the first transistor receives a power voltage, and the first transistor is controlled by a enable signal. The second transistor is coupled between an output end of the interface circuit and a reference ground end, and is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit is coupled to the second transistor and generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit is coupled to the first logic circuit and the first switch, wherein the second logic circuit generates the second control signal according to the first control signal and the enable signal.
Accordingly, the interface circuit provides the first switch to cut off a connection path between the first transistor and the output end of the interface circuit when the second transistor is turned on. Such as that, the second transistor needs not to fight with the first transistor when the interface circuit generates an output signal with a low voltage. A waveform of the output signal is not affected by a process variation, and the interface circuit can provide the output signal with good quality.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiment of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Please refer to
In this embodiment, the inverted enable signal ENB is generated by an inverter IV1. The inverter IV1 receives an enable signal EN and generated the inverted enable signal to the control end of the transistor MP1. The enable signal EN is used to indicate the interface circuit 200 to be at an input mode or an output mode. In here, when the enable signal EN is at logic 1, the interface circuit 200 is at the output mode, and when the enable signal EN is at logic 0, the interface circuit 200 is at the input mode.
The logic circuit 230 includes an OR logic gate OR1 and an AND logic gate AD2. The OR logic gate may have a plurality of input end to receives a plurality of indication signals A1˜AM, and the OR logic gate generates an operation result OA1 by performing a logic OR operation on indication signals A1˜AM. The AND logic gate receives the operation result OA1 and the enable signal EN, and generates the control signal CTA by performing an AND logic operation on the operation result OA1 and the enable signal EN.
The logic circuit 220 is used to perform an AND logic operation on the enable signal EN and the control signal CTA. In this embodiment, the logic circuit 220 includes an AND gate AD1. The AND gate AD1 receives the enable signal EN and the control signal CTA and generates the control signal CTB according to the enable signal EN and the control signal CTA.
About a detail operation of the interface circuit 200, when the interface circuit 200 is at the output mode, the enable signal is set to logic 1, and the transistor MP1 is turned-on. At this time, if at least one of the indication signals A1˜AM is at logic 1, the AND gate can generate the control signal CTA which is at logic 1, too. Accordingly, the transistor MN1 can be turned-on.
It should be noted here, since the control signal CTA is at logic 1, the logic circuit 220 can generate the control signal CTB with logic 1. Such as that, the switch 210 is cut-off, and a connection path between the transistor MP1 and the output end of the interface circuit 200 is cut-off correspondingly. It can be realized, the output signal ALTN can be pulled to the reference ground voltage VSS successfully by the transistor MN1 without fighting with the transistor MP1. Since the transistor MN1 doesn't fight with the transistor MP1 to pull down the output signal ALTN, variations on the driving abilities of the transistor MP1 and MN1 makes low effect on the output signal ALTN.
Please refer to
Moreover, after all of the indication signals A1˜AM return to logic 0, and the logic circuit 230 can set the control signal CTA to logic 0. The transistor MN1 can be cut-off according to the control signal CTA with logic 0. After a delay time Td2, the logic circuit 220 can set the control signal CTB to logic 0. When the control signal CTB is at logic 0, the switch 210 can be turned-on, and the output signal ALTN can be pulled-up toward to the power voltage VDD during a time period T4.
Please refer to
In this embodiment, the indication signals A1˜AM may be alert signals of the integrated circuit. According to the embodiment, the interface circuit 200 can provide the output signal ALTN with correct definition. Such as that, an external electronic circuit coupled to the pad PD can identify the output signal ALTN successfully.
Please refer to
On the other hand, since the transistor MN2 and a transistor MP2 in the switch 410 have different conductive types and the transistors MN2 and MP2 are controlled by the same control signal CTB, the turned-on or cut-off statuses of the transistors MN2 and MP2 are different. In an output mode, the transistor MP2 can be cut-off according to the control signal CTB and the transistor MN2 can be turned on according to the control signal CTB.
The ESD protection circuit 450 is coupled to a pad PD which is coupled to the output end of the interface circuit 401. The ESD protection circuit 450 can be implemented by any ESD protection circuit structure well known by a person skilled in this art. Furthermore, in this embodiment, the switches 410 and 440 may be disposed adjacent to the pad PD, and the transistors MP2 and MN2 can be auxiliary ESD protection circuits. Such as that, a circuit structure of the ESD protection circuit 450 can be simplified to reduce a circuit size of the interface circuit 401.
In this embodiment, the interface circuit 401 further includes an output switch SW1 which is coupled between the pad PD and an external circuit 460. The output switch SW1 can be controlled by the enable signal EN, and if the enable signal EN indicates the interface circuit 401 to be in the output mode, the output switch SW1 can be cut-off. On the contrary, if the enable signal EN indicates the interface circuit 401 to be in an input mode, the output switch SW1 can be turned-on. In the output mode, the enable signal EN can be at logic 1, and in the input mode, the enable signal EN can be at logic 0. It should be noted here, in the input mode, the transistors MP1, MP2, MN2 and MN1 can be cut-off according to the enable signal EN. The pad PD can be in floating status.
Detail operation of the interface circuit 401 is similar to the interface circuit 200, and no more description here.
In
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Detail operation of the interface circuit 501 is same to the interface circuit 401, and no more description here.
In
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Detail operation of the interface circuit 601 is same to the interface circuit 401, and no more description here.
In
In summary, the interface circuit of presented disclosure provides the switch which is coupled between an output end and a first transistor of the interface circuit, where the first transistor is used to pull up an output signal on the output end. When the interface circuit is in an output mode, and the interface circuit needs to generate the output signal with a low voltage level, a second transistor used to pull down the output signal is turned on and the switch is cut-off accordingly. Such as that, the second transistor needs not to fight with the first transistor, and the output signal can be pulled down successfully. On the other hand, in the output mode, during a normal operation, the second transistor is cut-off and the first transistor is turned-on to weakly pull up a signal on the pad. During an alert event, the first transistor can be cut-off and the second transistor is turned-on to pull down the signal on the pad to generate. By alternatively pulling up and pulling down the signal on the pad, an alert signal with pulses transited between logic 1 and 0 can be transported to an external device. Since the first transistor and the output end can be isolated by the switch in output mode, an influence to the output signal caused by process variation can be minimized. The output signal can be identified by external circuit, and the performance of the interface circuit can be enhanced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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