layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. layered structure includes a semiconductor device, comprising a iii-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the iii-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.
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19. A layered structure, comprising:
a rare-earth-nitride (RE-N) layer, wherein the RE-N layer has an orientation that is not polar; and
a polar rare-earth oxide layer grown over the RE-N layer,
wherein the orientation of the RE-N layer comprises an atomic arrangement such that a portion of rare-earth metal atoms of the polar rare-earth oxide layer are vertically aligned with nitrogen atoms of the RE-N layer, and
wherein the orientation of the RE-N layer comprises a <1-100> orientation or a <11-20> orientation.
1. A layered structure, comprising:
a group iii-nitride (iii-N) layer, wherein the iii-N layer has an orientation that is not polar; and
a polar rare-earth oxide layer grown over the iii-N layer,
wherein the orientation of the iii-N layer comprises an atomic arrangement such that a portion of rare-earth metal atoms of the polar rare-earth oxide layer are vertically aligned with nitrogen atoms of the iii-N layer, and
wherein the orientation of the iii-N layer comprises a <1-100> orientation or a <11-20> orientation.
11. A semiconductor device, comprising:
a group iii-nitride (iii-N) layer, wherein the iii-N layer has an orientation that is not polar;
a polar rare-earth oxide layer grown over the iii-N layer;
a gate terminal deposited or grown over the polar rare-earth oxide layer;
a source terminal that is deposited or epitaxially grown over the layer; and
a drain terminal that is deposited or grown over the layer,
wherein the orientation of the iii-N layer comprises an atomic arrangement such that a portion of rare-earth metal atoms of the polar rare-earth oxide layer are vertically aligned with nitrogen atoms of the iii-N layer, and
wherein the orientation of the iii-N layer comprises a <1-100> orientation or a <11-20> orientation.
4. The layered structure of
a rare-earth silicide layer grown over the polar rare-earth oxide layer.
5. The layered structure of
an epitaxial metal layer epitaxially grown over the polar rare-earth oxide layer.
6. The layered structure of
7. The layered structure of
8. The layered structure of
a group IV substrate; and
an epi-twist rare-earth oxide layer over the group IV substrate,
wherein the iii-N layer is over the epi-twist rare-earth oxide layer.
9. The layered structure of
an epitaxial metal layer between the epi-twist rare-earth oxide layer and the iii-N layer.
12. The semiconductor device of
13. The semiconductor device of
a silicon dioxide layer between the polar rare-earth oxide layer and the gate terminal.
14. The semiconductor device of
a silicon substrate; and
an epi-twist rare-earth oxide layer over the silicon substrate,
wherein the iii-N layer is over the epi-twist rare-earth oxide layer.
15. The semiconductor device of
a second iii-N layer over a second region on the epi-twist rare-earth oxide layer, wherein the first region and the second region are non-overlapping;
a transparent electrode over a first sub-region of the second iii-N layer; and
an electrode over a second sub-region of the iii-N layer,
wherein the second iii-N layer, the transparent electrode, and the electrode form a photonic device.
16. The semiconductor device of
17. The semiconductor device of
a silicon device integrated into the silicon substrate at a third region between the first region of the epi-twist rare-earth oxide layer and the second region of the epi-twist rare-earth oxide layer.
18. The semiconductor device of
an element that comprises a rare-earth pnictide over the silicon substrate at the third region between the first region of the epi-twist rare-earth oxide layer and the second region of the epi-twist rare-earth oxide layer; and
a iii-N device over the rare-earth pnictide element.
22. The layered structure of
a rare-earth silicide layer grown over the polar rare-earth oxide layer.
23. The layered structure of
an epitaxial metal layer epitaxially grown over the polar rare-earth oxide layer.
24. The layered structure of
25. The layered structure of
26. The layered structure of
a group IV substrate; and
an epi-twist rare-earth oxide layer over the group IV substrate,
wherein the RE-N layer is over the epi-twist rare-earth oxide layer.
27. The layered structure of
an epitaxial metal layer between the epi-twist rare-earth oxide layer and the RE-N layer.
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This disclosure claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 62/631,163, filed Feb. 15, 2018, which is hereby incorporated by reference herein in its entirety.
This application relates to integrating various semiconductor devices over a layered structure of a polar-oriented rare-earth oxide layer grown over another semiconductor layer.
The dielectric permittivity of non-polar rare-earth oxide (REO) layers is usually limited to a range of 12 to 14. The low dielectric permittivity limits the thickness of non-polar rare-earth oxide layers. The limitation on the thickness of the non-polar rare-earth oxide layers increases current leakage and thus does not allow for growth of an efficient electronic devices over the non-polar rare-earth oxide layer. Thus, conventional methods do not allow for the formation of efficient electronic devices with two-dimensional electron gas (2DEG) over III-N layers with a non-polar orientation.
Polar REO layers demonstrate higher dielectric permittivity. Increased dielectric permittivity would be beneficial because it allows the growing of thicker field-effect transistor (FET) gate layers while maintaining the same equivalent oxide thickness and decreasing leakage current.
Layered structures described herein include devices with 2DEG between polar-oriented rare-earth oxide layers on a III-N layer. In some embodiments, the orientation of the III-N layer is non-polar or semi-polar. In some embodiments, the layered structure further comprises a rare-earth silicide layer grown over the polar rare-earth oxide layer. In some embodiments, the layered structure further comprises an epitaxial metal layer epitaxially grown over the polar rare-earth oxide layer.
In some embodiments, the polar rare earth oxide layer of the layered structure has at least a first portion of electrons that diffuse to an interface between the polar rare-earth oxide layer and the III-N layer or are transferred to the III-N layer to form an n-type 2-dimensional electron gas (2DEG) on the III-N layer. In some embodiments, the III-N layer and the polar rare-earth oxide layer are selected to yield a conduction band offset between the III-N layer and the polar rare-earth oxide layer that is sufficient for electrons to diffuse from the polar rare-earth oxide layer into the III-N layer.
In some embodiments, the layered structure further comprises a group IV substrate, an epi-twist rare-earth oxide layer over the group IV substrate, and wherein the III-N layer is over the epi-twist rare earth oxide layer. In some embodiments, the layered structure further comprises an epitaxial metal layer between the epi-twist rare-earth oxide layer and the III-N layer. In some embodiments, the III-N layer of the layered structure comprises of gallium nitride.
Layered structure includes a semiconductor device, comprising a III-N layer, a polar rare-earth oxide layer grown over the III-N layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer. In some embodiments, the gate terminal of the semiconductor device includes rare earth silicide or an epitaxial metal element. In some embodiments, the semiconductor device further comprises a silicon dioxide layer between the polar rare-earth oxide layer and the gate terminal.
In some embodiments, the semiconductor device further comprises a silicon substrate; an epi-twist rare-earth oxide layer over the silicon substrate, and wherein the III-N layer is over the epi-twist rare earth oxide layer. In some embodiments, the III-N layer of the semiconductor device aligns with a first region on the epi-twist rare-earth oxide layer, and the layered structure further comprises a second III-N layer over a second region on the epi-twist rare-earth oxide layer, wherein the first region and the second region are non-overlapping. In some embodiments, the layered structure further comprises a transparent electrode over a first sub-region of the second III-N layer, and an electrode over a second sub-region of the III-N layer, wherein the second III-N layer, the transparent electrode and the electrode form a photonic device.
In some embodiments, the first region of the epi-twist rare-earth oxide layer and the second region of the epi-twist rare-earth oxide layer of the semiconductor device are discontinuous. In some embodiments, the semiconductor device further comprises a silicon device integrated into the silicon substrate at a third region between the first region of the epi-twist rare-earth oxide layer and the second region of the epi-twist rare-earth oxide layer. In some embodiments, the semiconductor device further comprises an element that comprises a rare-earth pnictide over the silicon substrate at the third region between the first region of the epi-twist rare-earth oxide layer and the second region of the epi-twist rare-earth oxide layer, and a III-V device over the rare-earth pnictide element.
Layered structures described herein include devices with 2DEG between polar-oriented cubic rare-earth oxide layers on a RE-N semiconductor. In some embodiments, the orientation of the RE-N layer is non-polar or semi-polar. In some embodiments, the layered structure further comprises a rare-earth silicide layer grown over the polar rare-earth oxide layer. In some embodiments, the layered structure further comprises an epitaxial metal layer epitaxially grown over the polar rare-earth oxide layer.
In some embodiments, the polar rare earth oxide layer of the layered structure has at least a first portion of electrons that diffuse to an interface between the polar rare-earth oxide layer and the RE-N layer or are transferred to the RE-N layer to form an n-type 2-dimensional electron gas (2DEG) on the RE-N layer. In some embodiments, the RE-N layer and the polar rare-earth oxide layer are selected to yield a conduction band offset between the RE-N layer and the polar rare-earth oxide layer that is sufficient for electrons to diffuse from the polar rare-earth oxide layer into the III-N layer.
In some embodiments, the layered structure further comprises a group IV substrate, an epi-twist rare-earth oxide layer over the group IV substrate, and wherein the RE-N layer is over the epi-twist rare earth oxide layer. In some embodiments, the layered structure further comprises an epitaxial metal layer between the epi-twist rare-earth oxide layer and the RE-N layer.
Further features of the disclosure, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which:
Structures and methods described herein provide an electronic device with 2-dimensional electron gas (2DEG) between a polar-oriented rare-earth oxide layer on a semiconductor layer having non-polar or semi-polar orientation.
In some embodiments, surface atoms of non-polar or semi-polar oriented wurtzite semiconductors, such as III-N semiconductors in a form of AlxInyGa1-x-yN (0≤x, y≤1) (e.g., GaN <1-100> or GaN <11-20> when x=y=0), are arranged in a pattern that may be suitable for growth of rare earth oxides (REO) <100> with off-plane orientation. In some embodiments, the <100> orientation of the REO layer may be polar. The polar orientation allows electrons from oxygen vacancies of the REO layer to diffuse to the III-N semiconductor (e.g., GaN) and form a 2-dimensional electron gas (2DEG) in the III-N semiconductor (e.g., GaN). An exemplary form of an REO with a polar <100> structure is RE2O3 (e.g. Gd2O3). In this way, 2DEG electronic or photonic devices may be formed in non-polar or semi-polar III-N semiconductors.
This opens-up a way for integration of electronic and photonic devices on the same substrate of non-polar or semi-polar III-N. Additionally, in some embodiments, the polar oriented REO may be used as a base for a gate of an electronic device. The polar orientation enhances the dielectric permittivity of the gate dielectric (dielectric constant (k) can reach k>20 vs k≈14) and therefore leads to increased efficiency in the electronic devices grown over the polar oriented REO layers.
In some embodiments, non-polar substrate 102 may include semiconductors with cubic structure REN, GaAs, SiGe or II-VI etc, which can be used to form the 2DEG in a similar manner as discussed in
In some embodiments, polar-oriented REO <100> 104 may be grown over non-polar or semi-polar oriented <1-100> III-N substrate 102 because of the similar arrangement of atoms between the polar-orientated REO <100> 104 and non-polar oriented <1-100> III-N substrate 102. For example: (non-polar oriented <1-100> III-N substrate) GaN c=5.186 Å, (cubic polar-oriented REO <100>104) Lu2O3 ½ a=5.196 Å. In some embodiments, growth of cubic polar-orientated REO <100> 104 should be started with metal-first. In this way, RE metal atoms would be bound to N-atoms of non-polar oriented <1-100> III-N substrate 102.
In some embodiments, cubic polar-oriented REO <100> 104 may be grown over non-polar oriented <11-20> III-N substrate 102 because of the similar arrangement of atoms between the cubic polar-orientated REO <100> 104 and non-polar oriented <11-20> III-N substrate 102. For example, a non-polar oriented <1-100> III-N substrate (e.g., GaN) may have an edge length of 5.186 Å, and polar-oriented REO <100> layer (e.g., Lu2O3) may have half an edge length of 5.196 Å. Therefore, the structure of the polar oriented REO <100> is double of the edge length of the non-polar III-N substrate <1-100>. Thus, the atoms of the two layers align and reduce mismatch between the two layers. In some embodiments, growth of cubic polar-orientated REO <100> 104 should be started with metal-first. In this way, RE metal atoms would be bound to N-atoms of non-polar oriented <11-20> III-N substrate 102.
In some embodiments, absence of polarization fields in non-polar III-N (GaN <11-20>) semiconductors leads to an improvement in the efficiency of a photonic devices. In some embodiments, 2DEG regions in electronic devices (e.g. layered structure 1100) may be formed with non-polar III-Ns using polar REO <100> 1106 as a dielectric for gate terminal 1110. In such embodiments, stress may not be used to induce diffusion of electrons to form 2DEG in non-polar or semi-polar III-N semiconductors due to the absence of piezoelectric fields in non-polar or semi-polar III-Ns. Due to the lack of stress induced by non-polar III-N 1102 on a substrate, a photonic device 1608 and an electronic device 1602 may be formed on the same Si <100> substrate 1302, using epi-twist REO 1304.
Structure 1700 is similar to
Structure 1800 is similar to
The growth and/or deposition described herein may be performed using one or more of chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), organometallic vapor phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phase epitaxy (HVPE), pulsed laser deposition (PLD), and/or physical vapor deposition (PVD).
As described herein, a layer means a substantially-uniform thickness of a material covering a surface. A layer may be either continuous or discontinuous (i.e., having gaps between regions of the material). For example, a layer may completely cover a surface, or be segmented into discrete regions, which collectively define the layer (i.e., regions formed using selective-area epitaxy).
An REO layer is a layer that contains one or more rare earths (REs) and oxygen. The rare earths include Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy). Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Luthium (Lu), Scandium (Sc) and Yttrium (Y).
III-N materials include one or more species from Group III of the Periodic Table (such as B, Al, Ga, In, and Tl) and nitrogen. Examples of III-nitride materials include GaN, InxAlyGa1-x-yN (0≤x, y≤1), AlxGa1-xN (0≤x≤1), InxAl1-xN (0≤x≤1), InN, and/or AlN.
Monolithically-integrated means formed on the surface of the substrate, typically by depositing layers disposed on the surface.
Disposed on means “exists on” an underlying material or layer. This layer may comprise intermediate layers, such as transitional layers, necessary to ensure a suitable surface. For example, if a material is described to be “disposed on a substrate,” this can mean either (1) the material is in intimate contact with the substrate; or (2) the material is in contact with one or more transitional layers that reside on the substrate.
Single-crystal means a crystalline structure that comprises substantially only one type of unit-cell. A single-crystal layer, however, may exhibit some crystalline defects such as stacking faults, dislocations, or other commonly occurring crystalline defects.
Single-domain means a crystalline structure that comprises substantially only one structure of unit-cell and substantially only one orientation of that unit cell. In other words, a single-domain crystal exhibits no twinning or anti-phase domains.
Single-phase means a crystalline structure that is both single-crystal and single-domain.
Substrate means the material on which deposited layers are formed. Exemplary substrates include, without limitation: bulk silicon wafers, in which a wafer comprises a homogeneous thickness of single-crystal silicon; composite wafers, such as a silicon-on-insulator wafer that comprises a layer of silicon that is disposed on a layer of silicon dioxide that is disposed on a bulk silicon handle wafer; or any other material that serves as base layer upon which, or in which, devices are formed. Examples of such other materials that are suitable, as a function of the application, for use as substrate layers and bulk substrates include, without limitation, germanium, alumina, gallium-arsenide, indium-phosphide, silica, silicon dioxide, borosilicate glass, pyrex, and sapphire. A substrate may have a single bulk wafer, or multiple sub-layers. Specifically, a substrate may include multiple non-continuous porous portions. The multiple non-continuous porous portions may have different densities and may be horizontally distributed or vertically layered.
Miscut Substrate means a substrate which comprises a surface crystal structure that is oriented at an angle to that associated with the crystal structure of the substrate. For example, a 6° miscut <100> silicon wafer comprises a <100> silicon wafer that has been cut at an angle to the <100> crystal orientation by 6° toward another major crystalline orientation, such as <110>. Typically, but not necessarily, the miscut will be up to about 20°. Unless specifically noted, the phrase “miscut substrate” includes miscut wafers having any major crystal orientation. That is, a <111> wafer miscut toward the <011> direction, a <100>wafer miscut toward the <110> direction, and a <011> wafer miscut toward the <001> direction.
Semiconductor refers to any solid substance that has a conductivity between that of an insulator and that of most metals. An example semiconductor layer includes silicon. The semiconductor layer may include a single bulk wafer, or multiple sub-layers. Specifically, a silicon semiconductor layer may include multiple non-continuous porous portions. The multiple non-continuous porous portions may have different densities and may be horizontally distributed or vertically layered.
Semiconductor-on-Insulator means a composition that comprises a single-crystal semiconductor layer, a single-phase dielectric layer, and a substrate, wherein the dielectric layer is interposed between the semiconductor layer and the substrate. This structure is reminiscent of prior-art silicon-on-insulator (“SOI”) compositions, which typically include a single-crystal silicon substrate, a non-single-phase dielectric layer (e.g., amorphous silicon dioxide, etc.) and a single-crystal silicon semiconductor layer. Several important distinctions between prior-art SOI wafers and the inventive semiconductor-on-insulator compositions are that:
Semiconductor-on-insulator compositions include a dielectric layer that has a single-phase morphology, whereas SOI wafers do not. In fact, the insulator layer of typical SOI wafers is not even single crystal.
Semiconductor-on-insulator compositions include a silicon, germanium, or silicon-germanium “active” layer, whereas prior-art SOI wafers use a silicon active layer. In other words, exemplary semiconductor-on-insulator compositions include, without limitation: silicon-on-insulator, germanium-on-insulator, and silicon-germanium-on-insulator.
A first layer described and/or depicted herein as “configured on,” “on” or “over” a second layer can be immediately adjacent to the second layer, or one or more intervening layers can be between the first and second layers. A first layer that is described and/or depicted herein as “directly on” or “directly over” a second layer or a substrate is immediately adjacent to the second layer or substrate with no intervening layer present, other than possibly an intervening alloy layer that may form due to mixing of the first layer with the second layer or substrate. In addition, a first layer that is described and/or depicted herein as being “on,” “over,” “directly on,” or “directly over” a second layer or substrate may cover the entire second layer or substrate, or a portion of the second layer or substrate.
A substrate is placed on a substrate holder during layer growth, and so a top surface or an upper surface is the surface of the substrate or layer furthest from the substrate holder, while a bottom surface or a lower surface is the surface of the substrate or layer nearest to the substrate holder. Any of the structures depicted and described herein can be part of larger structures with additional layers above and/or below those depicted. For clarity, the figures herein can omit these additional layers, although these additional layers can be part of the structures disclosed. In addition, the structures depicted can be repeated in units, even if this repetition is not depicted in the figures.
From the above description it is manifest that various techniques may be used for implementing the concepts described herein without departing from the scope of the disclosure. The described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the techniques and structures described herein are not limited to the particular examples described herein, but can be implemented in other examples without departing from the scope of the disclosure. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.
Hammond, Richard, Clark, Andrew, Pelzel, Rodney, Dargis, Rytis, Lebby, Michael
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
8846504, | Nov 08 2013 | IQE plc | GaN on Si(100) substrate using epi-twist |
20060060131, | |||
20140239307, | |||
20150069409, | |||
20150125976, | |||
20150203990, | |||
20170141750, | |||
WO2017210622, |
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