A photodetector is provided. The photodetector includes a bottom electrode region in a semiconductor layer, a light absorption material in the semiconductor layer, and a first buffer layer sandwiched between a bottom surface of the light absorption material and the semiconductor layer. The first buffer layer includes, from bottom to top, a first si layer, a first sige layer, a second si layer, and a second sige layer. A first atomic percentage of ge in the first sige layer is less than a second atomic percentage of ge in the second sige layer. The photodetector further includes a top electrode region over the light absorption material.
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11. A photodetector, comprising:
bottom electrode regions above a buried oxide layer;
a semiconductor layer between the bottom electrode regions;
a light absorption material at least partially embedded within the semiconductor layer;
a first buffer layer above the light absorption material, wherein the first buffer layer comprises alternatingly stacking ge layers and first sige layers; and
a top electrode region above the first buffer layer.
17. A method for forming a photodetector, comprising:
forming a bottom electrode region in a semiconductor layer;
etching a semiconductor layer to form a first cavity;
forming a light absorption material in the first cavity;
forming a buffer layer over the light absorption material, wherein the forming the buffer layer comprises repeating steps of:
delivering a germanium-containing precursor to grow a ge layer; and
delivering a silicon-containing precursor and the germanium-containing precursor to grow a sige layer; and
forming a top electrode region over the buffer layer.
1. A photodetector, comprising:
a bottom electrode region in a semiconductor layer;
a light absorption material in the semiconductor layer;
a first buffer layer sandwiched between a bottom surface of the light absorption material and the semiconductor layer, wherein the first buffer layer comprises, from bottom to top, a first si layer, a first sige layer, a second si layer, and a second sige layer, and a first atomic percentage of ge in the first sige layer is less than a second atomic percentage of ge in the second sige layer; and
a top electrode region over the light absorption material.
2. The photodetector as claimed in
a buried oxide layer below the semiconductor layer, wherein the bottom electrode region is in contact with the buried oxide layer.
3. The photodetector as claimed in
4. The photodetector as claimed in
5. The photodetector as claimed in
6. The photodetector as claimed in
7. The photodetector as claimed in
8. The photodetector as claimed in
9. The photodetector as claimed in
10. The photodetector as claimed in
a dielectric layer sandwiched between a sidewall of the first buffer layer and the semiconductor layer and between a sidewall of the light absorption material and the semiconductor layer.
12. The photodetector as claimed in
13. The photodetector as claimed in
14. The photodetector as claimed in
a second buffer layer between the light absorption material and the semiconductor layer, wherein the second buffer layer comprises alternatingly stacking si layers and sige layers.
15. The photodetector as claimed in
16. The photodetector as claimed in
18. The method for forming the photodetector as claimed in
forming a protection layer to cover the semiconductor layer and the light absorption material; and
forming a second cavity through the protection layer until the light absorption material is exposed, wherein the buffer layer and the top electrode region are formed in the second cavity.
19. The method for forming the photodetector as claimed in
20. The method for forming the photodetector as claimed in
forming a dielectric layer to cover a top surface of the semiconductor layer and side surfaces of the semiconductor layer exposed from the first cavity before forming the light absorption material.
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This application is a Continuation Application of U.S. application Ser. No. 16/994,982, filed on Aug. 17, 2020, entitled “PHOTODETECTOR AND METHOD FOR FORMING THE SAME,” which claims the benefit of U.S. Provisional Application No. 62/903,046, filed on Sep. 20, 2019 and entitled “Photodetector and method for forming the same,” all of which are incorporated herein by reference.
There is a constant drive within the semiconductor industry to reduce costs and increase the performance of such semiconductor devices as photodetectors, diodes, light-emitting diodes, transistors, latches, and many others. This drive has resulted in continuing demand for integrating one type of semiconductor device into another semiconductor process.
For example, in photodetectors that are comprised of an array of p-n junctions or p-i-n structures, it is advantageous to make the p-n junctions and/or p-i-n structures out of low band-gap materials, such as germanium (Ge) and InGaAs, because the photodetectors are able to detect infrared light. In the interests of cost-efficiency, it is preferable to produce a thin film of III-V or other non-silicon materials on low-cost large-size silicon wafers to reduce the cost of high-performance III-V devices. It is further desired to integrate non-silicon p-n junctions and/or p-i-n structures (e.g. Ge or InGaAs based) into a silicon process so that other circuitry in the system, such as a photodetector, can be fabricated using a standard silicon process, such as a standard CMOS (complementary-metal-oxide-semiconductor) process.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.
Wavelengths of 1310 nm and 1550 nm generally are applied in data-communication and telecommunication, respectively. To convert a light signal to an electrical signal for data- and telecommunication applications, a photodetector needs to be able to efficiently absorb the light signal within the wavelength of about 1200 nm to about 1600 nm. For silicon photonic devices (i.e., including photonic components made of silicon and integrated on a silicon substrate), such as optical transceiver, photodetectors, optical modulators, grating couplers, light-emitting diodes, and/or the like, a silicon waveguide is able to confine and connect infrared light (wavelength greater than about 700 nm) due to its strong refractive index (about 3.47) in contrast to its silicon oxide cladding layers (about 1.45). Germanium and/or silicon germanium are easy to integrate with silicon photonic devices on the same silicon substrate (wafer) so that the application of the germanium and/or silicon germanium in photonic devices may significantly reduce overall manufacturing cost of photonic devices.
The aspect of the embodiments of the present disclosure is direct to a photodetector and a method for forming the photodetector. The photodetector may include a semiconductor layer, a superlattice structure in the semiconductor layer, and a light absorption material above the first superlattice structure. The superlattice structure includes pairs of silicon layer/silicon germanium layer, which may mitigate or eliminate misfit dislocations between the semiconductor layer and the light absorption material, thereby reducing the likelihood of the formation of crystalline defects in the light absorption material. Therefore, the performance of the photodetector may be enhanced, e.g., lower dark current, lower signal-to-noise ratios, and/or higher responsivity.
In some embodiments, the semiconductor substrate 104 is a silicon substrate. In some embodiments, the semiconductor substrate 104 includes an elementary semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof.
In some embodiments, the buried oxide layer 106 is made of an oxide such as silicon oxide. In some embodiments, the buried oxide layer 106 has a thickness in a range from about 500 nm to 5000 nm. In some embodiments, the semiconductor layer 107 is made of silicon, such as intrinsic silicon. For example, an impurity (or an n-type dopant and/or a p-type dopant) in the semiconductor layer 107 has a concentration of less than about 1014 cm−3. In some embodiments, the semiconductor layer 107 has a thickness in a range from about 200 to 600 nm.
An ion implantation process 1000 is blanket performed on the structure of
A patterned mask layer 110 is formed over the upper surface of the semiconductor layer 108, as shown in
An ion implantation process 1050 is performed on the structure of
In some embodiments, the first electrode regions 114 are heavily-doped n-type (also referred to as n++ herein) doped regions. The heavily-doped first electrode regions 114 have lower resistance and may allow a sufficient ohmic contact with subsequently formed contact plugs, thereby providing the resulting photodetector a lower contact resistance. In some embodiments, the n-type dopant in the first electrode regions 114 has a dopant concentration in a range from about 1×1020 cm−3 to about 3×1020 cm−3. That is, the dopant concentration of the first electrode regions 114 is greater than the dopant concentration of the semiconductor layer 108, in accordance with some embodiments. After the ion implantation process 1050, the patterned mask layer 110 is removed using such as an ashing process. In some embodiments, an anneal process may be optionally performed to active the dopant in the semiconductor layer 108.
A protection layer 116 is blanket formed over the upper surface of the semiconductor layer 108 and the upper surface of the first electrode regions 114, as shown in
A patterned mask layer 118 is formed over the upper surface of the protection layer 116, as shown in
An etching process is performed on the structure of
An etching process is performed on the structure of
In some embodiments, the etching depth D1 is controlled (e.g., by an etching time) and is in a range from about 150 nm to about 350 nm. In some embodiments, the cavity 124 has a width D2 greater than about 300 nm (e.g., 300-700 nm). If the width D2 of the cavity 124 is too small, it is potentially difficult to grow a semiconductor material in a subsequent epitaxial growth process. In some embodiments, a portion of the semiconductor layer 108 remaining below the cavity 124 has a thickness D3 in a range from 100 nm to about 200 nm. In some embodiments, the etched surfaces of the semiconductor layer 108, e.g., sidewalls 124S and a bottom surface 124B of the cavity 124, are rough, especially the bottom surface 124B.
A smoothing process 1100 is performed on the structure of
The smoothing process 1100 includes at least one cycle of an oxidation process and an oxide-removal process, in accordance with some embodiments. In some embodiments, the oxidation process is performed using a dry plasma oxidation and/or wet chemical oxidation to oxidize exposed portions of the semiconductor layer 108, thereby forming an oxide layer (e.g., silicon oxide) at the sidewalls 124S and the bottom surface 124B of the cavity 124. In some embodiments, the oxidation process is performed within a temperature range of about 400-600° C. In some embodiments, the oxide-removal process uses such as dilute hydrofluoric (dHf) acid to removes the oxide layer. In some embodiments, the cycle of an oxidation process and an oxide-removal process may repeat about 1-10 times.
A first (lower) superlattice structure 126 is formed on the semiconductor layer 108 from the cavity 124, as shown in
In some embodiments, each of the silicon layers 128 has a thickness D4 in a range from about 3 nm to about 15 nm. In some embodiments, each of the silicon germanium layers 130 has a thickness D5 in a range from about 3 nm to about 15 nm. In some embodiments, the first-level (bottommost) silicon layer 1281 is thickest among the layers of the first superlattice structure 126. In some embodiments, the first superlattice structure 126 has a thickness D6 in a range from about 30 to about 150 nm. The thicknesses D6 of the first superlattice structure 126 may be adjusted by adjusting the number of the pairs of silicon layer 128/silicon germanium layer 130 and/or the thickness D4 of the silicon layers 128 and/or the thickness D5 of the silicon germanium layers 130, which may depend on the device performance requirement, e.g., speed, responsivity, etc.
In some embodiments, the silicon germanium layers 130 are made of Si1-xGex, wherein x represents the atomic percentage of germanium and 0<x<1 such as 0.1≤x≤0.9. In some embodiments, the atomic percentages of germanium (x) in the silicon germanium layers 130 vary with their levels “i”. In detail, the atomic percentages of germanium in the silicon germanium layers 130 of the first superlattice structure 126 increase in order as the level “i” of a silicon germanium layer 130i increases from the first-level (bottommost silicon germanium layer 1301) to the top-level (topmost silicon germanium layer 130), in accordance with some embodiments.
For example, the increase in atomic percentage may be consistent. In an embodiment where the top level “j” is 4, the silicon germanium layers 1301, 1302, 1303 and 1304 are made of Si0.8Ge0.2, Si0.6Ge0.4, Si0.4Ge0.6 and Si0.2Ge0.8 respectively. In an embodiment where the top level “j” is 9, the silicon germanium layers 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308 and 1309 are made of Si0.9Ge0.1, Si0.8Ge0.2, Si0.7Ge0.3, Si0.6Ge0.4, Si0.5Ge0.5, Si0.4Ge0.6, Si0.3Ge0.7, Si0.2Ge0.8 and Si0.1Ge0.9, respectively.
For example, the increase in atomic percentage may be inconsistent. In an embodiment where the top level “j” is 4, the silicon germanium 1301, 1302, 1303 and 1304 are made of Si0.9Ge0.1, Si0.8Ge0.2, Si0.5Ge0.5 and Si0.2Ge0.8.
The first superlattice structure 126 including multiple pairs of silicon layer 128i/silicon germanium layer 130i is in-situ doped with a first conductive type dopant (such as an n-type dopant), in accordance with some embodiments. The n-type dopant may be phosphorous (P) or Arsenic (As). In some embodiments, the first superlattice structure 126 is a lightly-doped n-type (also referred to as n- herein) doped region and the n-type dopant in each of the silicon layers 128 and the silicon germanium layers 130 has a dopant concentration in a range from about 1×1017 cm−3 to about 9×1017 cm−3. In some other embodiments, the first superlattice structure 126 is a moderately-doped n-type (also referred to as n+ herein) doped region and the n-type dopant in the first superlattice structure 126 has a dopant concentration in a range from about 3×1018 cm−3 to about 3×1019 cm−3. That is, the dopant concentration of the first superlattice structure 126 is equal to or less than the dopant concentration of the semiconductor layer 108, in accordance with some embodiments. In alternative embodiments, the first superlattice structure 126 is undoped.
In some embodiments, the silicon layers 128 and the silicon germanium layers 130 are formed using an epitaxial growth process, such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or other suitable techniques. For example, the epitaxial growth process may include multiple cycles of growing a silicon layer 128 and growing a silicon germanium layer 130. In an embodiment where first superlattice structure 126 is doped with phosphorous, a silicon-containing precursor, e.g., silane (SiH4) gas and/or dichlorosilane (DCS) gas, along with a doping precursor, e.g., PH3, PF3, and/or PF5, may be delivered to an epitaxial growth chamber; the silicon-containing precursor may react to the exposed surface of the semiconductor layer 108 uncovered by the protection layer 116 and begin to grow a phosphorous-doped first-level silicon layer 1281. The silicon-containing precursor, e.g., silane gas and/or dichlorosilane gas and a germanium-containing precursor, e.g., germane (GeH4) gas, along with the doping precursor, e.g., PH3, PF3, and/or PF5, may be delivered to the epitaxial growth chamber; the silicon-containing precursor and the germanium-containing precursor may react to the surface of the first-level silicon layer 1281 and begin to grow a phosphorous-doped first-level silicon germanium layer 1301. The cycle of growing a silicon layer 128 and growing a silicon germanium layer 130 may repeat for 2-15 times to form the first superlattice structure 126. Furthermore, a ratio of a flow rate of the germanium-containing precursor to a total rate of the silicon-containing precursor and the germanium-containing precursor during growing a silicon germanium layer 130i may be adjusted higher than growing a silicon germanium layer 130i-1 of a previous cycle, thereby allowing the silicon germanium layers 130 having increasing atomic percentages of germanium as the level increases.
A light absorption material 132 is formed on the top-level silicon germanium layer 130k of the first superlattice structure 126 from the cavity 124, as shown in
In some embodiments, the light absorption material 132 is formed using an epitaxial growth process, such as MBE, MOCVD, or VPE, or other suitable techniques. In some embodiments, the light absorption material 132 is formed with faceted surfaces. After the formation of the light absorption material 132, the protection layer 116 may be optionally removed.
A protection layer 134 is blanket formed over the upper surface of the semiconductor layer 108 and covers the light absorption material 132, as shown in
A patterned mask layer 136 is formed over the upper surface of the protection layer 134, as shown in
An etching process is performed on the structure of
A second (upper) superlattice structure 142 is formed on the light absorption material 132 from the cavity 140, as shown in
In some embodiments, each of the germanium layers 144 has a thickness D8 in a range from about 3 nm to about 15 nm. In some embodiments, each of the silicon germanium layers 146 has a thickness D9 in a range from about 3 nm to about 15 nm. In some embodiments, the second superlattice structure 142 has a thickness D10 in a range from about 30 to about 150 nm. In some embodiments, a ratio of the thickness D10 to the thickness D7 is in a range from about 0.1 to about 0.3. The thicknesses D10 of the second superlattice structure 142 may be adjusted by adjusting the number of the pairs of germanium layer 144/silicon germanium layer 146 and/or the thickness D8 of the germanium layers 144 and/or the thickness D9 of the silicon germanium layers 146, which may depend on the device performance requirement, e.g., speed, responsivity, etc.
In some embodiments, the silicon germanium layers 146 are made of Si1-yGey, wherein y represents the atomic percentage of germanium and 0<y<1 such as 0.1≤y≤0.9. In some embodiments, the atomic percentages of germanium (y) in the silicon germanium layers 146 vary with their levels “k”. In detail, the atomic percentages of germanium in the silicon germanium layers 146 of the second superlattice structure 142 decrease in order as the level “k” of a silicon germanium layer 146k increases from the first-level (bottommost silicon germanium layer 1461) to the top-level (topmost silicon germanium layer 146m), in accordance with some embodiments.
For example, the decrease in atomic percentage may be consistent. In an embodiment where the top level “m” is 4, the silicon germanium layers 1461, 1462, 1463 and 1464 are made of Si0.2Ge0.8, Si0.4Ge0.6, Si0.6Ge0.4 and Si0.8Ge0.2, respectively. In an embodiment where the top level “m” is 9, the silicon germanium layers 1461, 1462, 1463, 1464, 1465, 1466, 1467, 1468 and 1469 are made of Si0.1Ge0.9, Si0.2Ge0.8, Si0.3Ge0.7, Si0.4Ge0.6, Si0.5Ge0.5, Si0.6Ge0.4, Si0.7Ge0.3, Si0.8Ge0.2 and Si0.9Ge0.1, respectively.
For example, the decrease in atomic percentage may be inconsistent. In an embodiment where the top level “m” is 4, the silicon germanium layers 1461, 1462, 1463 and 1464 are made of Si0.1Ge0.9, Si0.2Ge0.8, Si0.5Ge0.5 and Si0.8Ge0.2.
The second superlattice structure 142 including multiple pairs of germanium layer 144k/silicon germanium layer 146k is in-situ doped with a second conductive type dopant (such as a p-type dopant), in accordance with some embodiments. The p-type dopant may be boron (B) or BF2. In some embodiments, the second superlattice structure 142 is a lightly-doped p-type (also referred to as p- herein) doped region and the p-type dopant in each of the germanium layers 144 and the silicon germanium layers 146 has a dopant concentration in a range from about 1×1017 cm−3 to about 9×1017 cm−3. In some other embodiments, the second superlattice structure 142 is a moderately-doped p-type (also referred to as p+ herein) doped region and the p-type dopant in the second superlattice structure 142 has a dopant concentration in a range from about 3×1018 cm−3 to about 3×1019 cm−3. In alternative embodiments, the second superlattice structure 142 is undoped.
In some embodiments, the second superlattice structure 142 is formed using an epitaxial growth process, such as MBE, MOCVD, or VPE, or other suitable techniques. For example, the epitaxial growth process may include multiple cycles of growing a germanium layer 144 and growing a silicon germanium layer 146. In an embodiment where second superlattice structure 142 is doped with boron, a germanium-containing precursor, e.g., germane (GeH4) gas, along with a doping precursor, e.g., BF3, B2H6, and/or BCl3, may be delivered to an epitaxial growth chamber; the germanium-containing precursor may react to the exposed surface of the light absorption material 132 and begin to grow a boron-doped first-level germanium layer 1441. A silicon-containing precursor, e.g., silane gas, and/or dichlorosilane gas and the germanium-containing precursor, e.g., germane (GeH4) gas, along with the doping precursor, e.g., BF3, B2H6, and/or BCl3, may be delivered to the epitaxial growth chamber; the silicon-containing precursor and the germanium-containing precursor may react to the surface of the first-level germanium layer 1441 and begin to grow a boron-doped first-level silicon germanium layer 1461. The cycle of growing a germanium layer 144 and growing a silicon germanium layer 146 may repeat for 2-15 times to form the second superlattice structure 142. Furthermore, a ratio of a flow rate of the germanium-containing precursor to a total rate of the silicon-containing precursor and the germanium-containing precursor during growing a silicon germanium layer 146i may be adjusted lower than growing a silicon germanium layer 146i-1 of a previous cycle, thereby allowing the silicon germanium layers 144 having decreasing atomic percentages of germanium as the level increases.
A second (or top) electrode region 148 is formed on the top-level silicon germanium layer 146m of the second superlattice structure 142 from the cavity 140, as shown in
In some embodiments, the second electrode region 148 made of silicon (Si). In some embodiments, the second electrode region 148 is formed using an epitaxial growth process, such as MBE, MOCVD, or VPE, or other suitable techniques. The second electrode region 148 is in-situ doped with a second conductive type dopant (such as a p-type dopant) during the epitaxial growth process, in accordance with some embodiments. The p-type dopant may be boron (B) or BF2. In some embodiments, the second electrode region 148 is a heavily-doped p-type (also referred to as p++ herein) doped region. The heavily-doped second electrode region 148 has lower resistance and may allow a sufficient ohmic contact with a subsequently formed contact plug, thereby providing the resulting photodetector a lower contact resistance. In some embodiments, the p-type dopant in the second electrode region 148 has a dopant concentration in a range from about 1×1020 cm−3 to about 3×1020 cm−3. That is, the dopant concentration of the second electrode region 148 is greater than the dopant concentration of the second superlattice structure 142, in accordance with some embodiments.
The protection layer 134 is removed using an etching process to expose the semiconductor layer 108, as shown in
A dielectric layer 150 is formed over the upper surface of the semiconductor layer 108 and covers the second electrode region 148 and the light absorption material 132, as shown in
A patterned mask layer 152 is formed over the upper surface of the dielectric layer 150, as shown in
An etching process is performed on the structure of
A silicide layer 162 is formed on the upper surfaces of the first electrode regions 114 exposed from the contact openings 158 and on the upper surface of the second electrode region 148 exposed from the contact opening 160, as shown in
A conductive material 164 is formed over the upper surface of the dielectric layer 150 and overfill the contact openings 158 and 160, as shown in
A planarization process is performed on the structure of
The first (bottom) electrode regions 114 and the second (top) electrode region 148 of the photodetector 100 are disposed vertically opposite to one another with respect to the light absorption material 132, and therefore the photodetector 100 is referred to as a vertical-type photodetector, in accordance with some embodiments. Once light absorption material 132 absorbs a light signal and generates an electron-hole pair, hole passes through the first superlattice structure 126 and the semiconductor layer 108 to be swept to the first electrode regions 114 (cathode) while the electron passes through the second superlattice structure 142 to be swept to the second electrode region 148 (anode). Because the thickness D7 of the light absorption material 132 is less than the width D2 of the light absorption material 132, the vertical configuration of the first electrode regions 114 and the second electrode regions 148 may improve the speed of the photodetector 100 due to a short transfer path.
Because silicon and germanium has a 4.2% of lattice mismatch, in some instance where a germanium light absorption material is in direct contact with a silicon layer, the lattice mismatch may lead to the formation of crystalline defects (e.g., misfit dislocation and/or threading dislocation) at the silicon and germanium interface and/or in the germanium light absorption material. The crystalline defects may induce dark current, which decreases signal-to-noise ratios for a photodetector. Embodiments of the present disclosure utilizes the first superlattice structure 126 as a buffer layer between the light absorption material 132 and the underlying semiconductor layer 108 and the second superlattice structure 142 as a buffer layer between the light absorption material 132 and overlying the second electrode region 148. Therefore, the first superlattice structure 126 and the second superlattice structure 142 may mitigate or eliminate misfit dislocations between the germanium light absorption material 132 and the silicon layer (e.g., the semiconductor layer 108 and the second electrode region 148), which may reduce dark current, thereby enhancing the performance of the photodetector, e.g., signal-to-noise ratios. Moreover, the superlattice structures may reduce the band-gap offset between silicon and germanium, which may improve the performance of the photodetector, e.g., responsivity.
Furthermore, the first superlattice structure 126 includes the silicon germanium layer 130 having the atomic percentage of germanium increasing in order as the level of the silicon germanium layer 130 increase, lattice mismatch between the light absorption material 132 and the semiconductor layer 108 may be further mitigated or eliminated. Similarly, the second superlattice structure 142 includes the silicon germanium layer 146 having the atomic percentage of germanium decreasing in order as the level of the silicon germanium layer 146 increase, lattice mismatch between the light absorption material 132 and the second electrode region 148 may be further mitigated or eliminated.
In addition, because the first superlattice structure 126 and the second superlattice structure 142 may be in-situ doped with dopants during the epitaxial growth processes instead of using ion implantation, an anneal process may be omitted, thereby lowering a thermal budget during fabricating the photodetector 100. The lower thermal budget may mitigate or prevent the diffusion of dopants (such as from the semiconductor layer and/or the first electrode region) into the light absorption material 132, which in turn allows the light absorption material to maintain large active region and high electric field. As a result, the performance of the photodetector 100 (e.g., speed) may be further enhanced.
During the epitaxial growth process for forming the first superlattice structure 126, the silicon-containing precursor may react to the exposed semiconductor surfaces of the semiconductor layer 108 so that the first-level silicon layer 1281 extends along the sidewalls 124S and the bottom surface 124B of the cavity 124 and has a U-shape profile, in accordance with some embodiments. The first-level silicon germanium layer 1301 is then formed on the first-level silicon layer 1281 and conforms with the profile of the first-level silicon layer 1281, in accordance with some embodiments. As a result, after the completion of the epitaxial growth process, the first superlattice structure 126 extends along the sidewalls 124S and the bottom surface 124B of the cavity 124 and has a U-shape profile. In some embodiments, a thickness of the first superlattice structure 126 along the sidewall 124S of the cavity 124 is less than the thickness D6 (
A substrate 102 is provided, and the steps described above with respect to
The ion implantation process 1000 described above with respect to
The steps described above with respect to
The steps of forming the second electrode region 148 as described in
The light absorption material 132 is formed not protruding the cavity 124, as shown in
After the formation of the second electrode region 148, the protection layer 116 may be removed. The steps described in
Many variations and/or modifications can be made to embodiments of the disclosure.
A dielectric layer 602 is formed over the structure of
A patterned mask layer 604 is formed over the upper surface of the dielectric layer 602, as shown in
An etching process is performed on the structure of
A remainder of the dielectric layer 602 includes a horizontal portion 602A over the upper surface of the semiconductor layer 108 and vertical portions 602B covering the sidewalls of the original cavity 124 and defining the cavity 608, in accordance with some embodiments. The bottom surface of the cavity 608 is also denoted as 124B. After the etching process, the patterned mask layer 604 is removed, in accordance with some embodiments.
Optionally, the smoothing process 1100 described above with respect to
The steps described above with respect to
The steps described above with respect to
The steps described above with respect to
As described above, the embodiments of the present disclosure provide a photodetector including a semiconductor layer 108, a first superlattice structure 126 in the semiconductor layer 108, and a light absorption material 132 above the first superlattice structure 126. The first superlattice structure 126 includes pairs of silicon layer 128/silicon germanium layer 130, which may mitigate or eliminate misfit dislocations between silicon from the semiconductor layer 108 and germanium from the light absorption material 132, thereby reducing the likelihood of the formation of crystalline defects in the light absorption material 132. Therefore, the performance of the photodetector may be enhanced, e.g., lower dark current, lower signal-to-noise ratios, and/or higher responsivity.
Embodiments of a photodetector may be provided. The photodetector may include a first superlattice structure between the semiconductor layer and the light absorption material. Therefore, the performance of the photodetector may be enhanced, e.g., lower dark current, lower signal-to-noise ratios, and/or higher responsivity.
In some embodiments, a photodetector is provided. The photodetector includes a bottom electrode region in a semiconductor layer, a light absorption material in the semiconductor layer, and a first buffer layer sandwiched between a bottom surface of the light absorption material and the semiconductor layer. The first buffer layer includes, from bottom to top, a first Si layer, a first SiGe layer, a second Si layer, and a second SiGe layer. A first atomic percentage of Ge in the first SiGe layer is less than a second atomic percentage of Ge in the second SiGe layer. The photodetector further includes a top electrode region over the light absorption material.
In some embodiments, a photodetector is provided. The photodetector includes bottom electrode regions above a buried oxide layer, a semiconductor layer between the bottom electrode regions, a light absorption material at least partially embedded within the semiconductor layer, and a first buffer layer above the light absorption material. The first buffer layer comprises alternatingly stacking Ge layers and first SiGe layers. The photodetector further includes a top electrode region above the first buffer layer.
In some embodiments, a method for forming a photodetector is provided. The method includes forming a bottom electrode region in a semiconductor layer, etching a semiconductor layer to form a first cavity, forming a light absorption material in the first cavity, and forming a buffer layer over the light absorption material. Forming the buffer layer includes repeating steps of delivering a germanium-containing precursor to grow a Ge layer, and delivering a silicon-containing precursor and the germanium-containing precursor to grow a SiGe layer. The method further includes forming a top electrode region over the buffer layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
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