A signature device (30) acquires a signature key SK(x→) in which an attribute vector x→ is set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces. The signature device (30) generates a signature sig for a message MSG by setting predicate information of arithmetic branching programs (ABP) for the signature key SK(x→). The signature device (30) outputs the signature sig and the message MSG to a verification device (40).
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10. A signature method comprising:
acquiring a signature key in which an attribute vector is set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces;
generating a signature for a message by setting predicate information of arithmetic branching programs (ABP) for the signature key; and
outputting the signature and the message,
wherein the signature key includes elements respectively corresponding to elements of the attribute vector, and in each of the element of the signature key, index information I* associated with a corresponding one of the elements of the attribute vector is set as a coefficient of one or more but not all basis vectors in the basis b*.
1. A signature device comprising:
processing circuitry to:
acquire a signature key in which an attribute vector is set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces,
generate a signature for a message by setting predicate information of arithmetic branching programs (ABP) for the acquired signature key, and
output the generated signature and the message,
wherein the signature key includes elements respectively corresponding to elements of the attribute vector, and in each of the element of the signature key, index information I* associated with a corresponding one of the elements of the attribute vector is set as a coefficient of one or more but not all basis vectors in the basis b*.
11. A non-transitory computer readable medium storing a signature program that causes a computer to function as a signature device to perform:
an acquisition process of acquiring a signature key in which an attribute vector is set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces;
a signature process of generating a signature for a message by setting predicate information of arithmetic branching programs (ABP) for the signature key acquired by the acquisition process; and
an output process of outputting the signature generated by the signature process and the message,
wherein the signature key includes elements respectively corresponding to elements of the attribute vector, and in each of the element of the signature key, index information I* associated with a corresponding one of the elements of the attribute vector is set as a coefficient of one or more but not all basis vectors in the basis b*.
12. A verification method comprising:
acquiring a signature in which an attribute vector and predicate information of arithmetic branching programs (ABP) are set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces; and
verifying the signature by performing a pairing operation on the signature and verification data in which verification information is set over the basis b,
wherein the signature includes elements respectively corresponding to elements of the attribute vector, and in each of the elements of the signature, index information I* associated with a corresponding one of the elements of the attribute vector is set as a coefficient of one or more but not all basis vectors in the basis b*, and
wherein the verification data includes one or more elements corresponding to one or more elements of the attribute vector, and in each element of the verification data, index information I is set as a coefficient of each basis vector in the basis b corresponding to the one or more but not all basis vectors, the index information I being such that a sum of inner products of the index information I and the index information I* becomes 0.
6. A verification device comprising:
processing circuitry to:
acquire a signature in which an attribute vector and predicate information of arithmetic branching programs (ABP) are set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces, and
verify the signature by performing a pairing operation on the acquired signature and verification data in which verification information is set over the basis b,
wherein the signature includes elements respectively corresponding to elements of the attribute vector, and in each of the elements of the signature, index information I* associated with a corresponding one of the elements of the attribute vector is set as a coefficient of one or more but not all basis vectors in the basis b*, and
wherein the verification data includes one or more elements corresponding to one or more elements of the attribute vector, and in each element of the verification data, index information I is set as a coefficient of each basis vector in the basis b corresponding to the one or more but not all basis vectors, the index information I being such that a sum of inner products of the index information I and the index information I* becomes 0.
13. A non-transitory computer readable medium storing a verification program that causes a computer to function as a verification device to perform:
an acquisition process of acquiring a signature in which an attribute vector and predicate information of arithmetic branching programs (ABP) are set over a basis b* of a basis b and the basis b*, which are dual bases in dual vector spaces; and
a verification process of verifying the signature by performing a pairing operation on the signature acquired by the acquisition process and verification data in which verification information is set over the basis b,
wherein the signature includes elements respectively corresponding to elements of the attribute vector, and in each of the elements of the signature, index information I* associated with a corresponding one of the elements of the attribute vector is set as a coefficient of one or more but not all basis vectors in the basis b*, and
wherein the verification data includes one or more elements corresponding to one or more elements of the attribute vector, and in each element of the verification data, index information I is set as a coefficient of each basis vector in the basis b corresponding to the one or more but not all basis vectors, the index information I being such that a sum of inner products of the index information I and the index information I* becomes 0.
2. The signature device according to
wherein the predicate information is obtained from an arithmetic span program (ASP) representation corresponding to the ABP.
3. The signature device according to
wherein the predicate information includes an element Ωj indicated in Formula 1, and
wherein the processing circuitry conceals an element of the attribute vector by the element Ωj
d is an integer of 1 or more,
n is the number of elements in an attribute vector, and
m,L are integers of 1 or more.
4. The signature device according to
wherein the predicate information includes an element Ω′j and an element Ω″j indicated in Formula 2, and
wherein the processing circuitry conceals an element of the attribute vector and the element Ωj by the element Ω′j and the element Ω″j
H is a hash function, MSG is a message, and b* is a basis vector of a basis b*.
7. The verification device according to
wherein the predicate information and the verification information are obtained from an arithmetic span program (ASP) representation corresponding to the ABP.
8. The verification device according to
wherein the predicate information includes Ωj indicated in Formula 4
[Formula 4]
d is an integer of I or more,
n is the number of elements in an attribute vector, and
m,L are integers of I or more.
9. The verification device according to
wherein the signature is sig indicated in Formula 5, and
wherein the verification data is c indicated in formula 6
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This application is a Continuation of PCT International Application No. PCT/JP2019/047995, filed on Dec. 9, 2019, which claims priority under 35 U.S.C. 119(a) to Patent Application No. 2019-048622, filed in Japan on Mar. 15, 2019, all of which are hereby expressly incorporated by reference into the present application.
The present invention relates to a signature technique using arithmetic branching programs (ABP).
Non-Patent Literature 1 describes an attribute-based signature (ABS) scheme for a general predicate determined by a polynomial-sized circuit, a polynomial-time computable Turing machine, and the like.
However, the scheme described in Non-Patent Literature 1 is highly theoretical, and it is difficult to achieve efficiency that allows actual use.
It is an object of the present invention to allow a practical ABS scheme to be constructed.
A signature device according to the present invention includes
an acquisition unit to acquire a signature key in which an attribute vector is set over a basis B* of a basis B and the basis B*, which are dual bases in dual vector spaces;
a signature unit to generate a signature for a message by setting predicate information of arithmetic branching programs (ABP) for the signature key acquired by the acquisition unit; and
an output unit to output the signature generated by the signature unit and the message.
In the present invention, a signature is generated by setting a predicate vector of ABP for a signature key in which an attribute vector is set. This allows a practical ABS scheme to be constructed.
Notations to be used in the following description will be described.
Formula 101 denotes a security parameter, and 1λ represents unary encoding.
λ∈ [Formula 101]
Formula 102 denotes a finite field modulo q. Formula 102 will be written as a field Fq or simply as Fq.
for any prime q∈
[Formula 102]
For Formula 103, Formula 104 is defined.
d∈,
c∈∪{0}(c<d) [Formula 103]
[d]={1, . . . , d},
[c,d]={c, . . . , d} [Formula 104]
Formula 105 denotes a process of uniformly sampling an element z from a set Z.
#Z denotes the size or cardinality of the set Z.
For a probabilistic algorithm P, Formula 106 denotes a process of sampling II from the output distribution of the algorithm P on input Θ with a uniform random tape.
For a deterministic algorithm D, Π=V(Θ) denotes output of the algorithm D on input Θ.
It is assumed that each algorithm is given the unary representation 1λ of the security parameter λ as input without any explicit indication of the input when it is clear from the context.
For Formula 107, Formula 108 denotes a vector indicated in Formula 109. Formula 108 will be written as v→.
, d∈
[Formula 107]
{right arrow over (v)} [Formula 108]
(v1, . . . , vd) ∈d
where vi∈for all i∈[d] [Formula 109]
An all zero vector over a field Fqd will be written as indicated in Formula 110.
Ōd [Formula 110]
A normal basis vector over the field Fqd is represented as indicated in Formula 111.
For two vectors indicated in Formula 112, Formula 113 denotes the inner product of a vector v→ and a vector w→. That is, Formula 113 denotes Formula 114.
Formula 115 denotes a subspace of the field Fqd formed by Formula 116.
for any s∈, and any {
qd [Formula 115]
SPAN [Formula 116]
Formula 117 denotes a multiplicative cyclic group. Formula 117 will be written as a group G or simply as G.
[Formula 117]
For the group G and a generator g of the group G, v denotes a d-dimensional vector of group elements. That is, this is expressed in Formula 118.
v=(gv1, . . . , gvd) ∈d for some d∈
where d [Formula 118]
M=(mk,i) denotes a d×r matrix with entries mi,k ∈Fq. MT denotes a transpose of the matrix M. Note that det(M) denotes a determinant of the matrix M. In describing matrices, I denotes an identity matrix, and 0 denotes a zero matrix. GL(d, Fq) denotes a set of all d×d invertible matrices over Fqd×d.
Definitions of terms and the like to be used in the following description will be described.
In a first embodiment, an ABS scheme using a predicate of ABP will be described. In the first embodiment, an arithmetic span program (ASP) representation of a predicate of ABP is used. Therefore, ABP and ASP will be described.
<ABP>
A branching program (BP) Γ is defined by five elements indicated in Formula 119.
Γ=(,
,V0, V1, ϕ) [Formula 119]
Formula 120 denotes a set of vertices, and Formula 121 denotes a set of edges. Formula 120 will be written simply as V, and Formula 121 will be written simply as E.
[Formula 120]
[Formula 121]
(V, E) is a directed acyclic graph. V0 and V1 ∈ V are special vertices called a source and a sink respectively, and φ is a labeling function for edges in E.
An ABP F over the finite field Fq computes a function f indicated in Formula 122.
ƒ:qn→
qfor some n∈
[Formula 122]
Note that the labeling function φ assigned to each edge in E is a degree one polynomial in one variable with coefficients over Fq or a constant over Fq. Let p be a set of all paths from the source V0 to the sink V1 in the ABP Γ. The output of the function f computed by the ABP Γ on some input x→=(x1, . . . , xd) ∈ Fqd is defined as indicated in Formula 123.
Formula 124 denotes an evaluation value of the function φ(E) at x→.
E∈,ϕ(E)|
The following content is described in Non-Patent Literature “Ishai, Y., Kushilevitz, E.: Perfect constant-round secure computation via perfect randomizing polynomials. In: International Colloquium on Automata, Languages, and Programming-ICALP 2002. pp. 244-256. Springer (2002)”.
If ABP Γ=(V, E, V0, V1, φ) computing a function f is given, it is possible to efficiently and deterministically compute a function L mapping input x→ ∈Fqd to a (#V-1)×(#V-1) matrix L(x→) over Fq. The following (1) to (3) hold:
Specifically, the matrix L is obtained by removing the column corresponding to V0 and the row corresponding to V1 from a matrix AΓ-I, where the matrix AΓ is an adjacency matrix for Γ and I is an identity matrix.
Note that there exists a linear-time algorithm that converts any Boolean formula, Boolean branching program, or arithmetic formula to an ABP.
<ASP>
An access structure S=(U, ρ) in n variables is a set U of a pair of vectors indicated in Formula 125 and a function p indicated in Formula 126.
={
[Formula 125]
where for all j∈[m],(qL)2 for L∈
[Formula 125]
ρ: [m]→[n] [Formula 126]
If and only if Formula 127 holds, an attribute vector x→ indicated in Formula 128 satisfies the access structure S.
xρ(j)
[Formula 127]
qn [Formula 128]
ABP and ASP are related to each other as described below.
Non-Patent Literature “Ishai, Y., Wee, H.: Partial garbling schemes and their applications. In: ICALP2014. pp. 650-662. Springer” discusses that for Formula 129, if ABP Γ=(V, E, V0, V1, φ) of a size m+1 computing a function f indicated in Formula 130 is given, there exists an efficient algorithm that constructs an access structure S of ASP indicated in Formula 131.
n,m∈N [Formula 129]
ƒ: qn→
q [Formula 130]
=(
={
q(m+1))2,ρ: [m]→[n])
such that for all qn,f(
accepts
Formula 132 signifies that f(x→)=0 and that the access structure S accepts x→ are equivalent.
ƒ(accepts
In the first embodiment, ABS is realized in dual pairing vector spaces (DPVS), which are dual vector spaces. Therefore, DPVS and a bilinear group, which is a prerequisite for DPVS, will be described.
<Bilinear Group>
Note that paramG, which is a bilinear group, indicated in Formula 133 includes a prime q, cyclic multiplicative groups G1, G2, and GT of order q, a generator g1 of the group G1, a generator g2 of the group G2, and a bilinear map e indicated in Formula 134.
params=(q,G1,G2,GT,g1,g2,e) [Formula 133]
e: G1×G2→GT [Formula 134]
The bilinear map e has the following two properties of bilinearity and non-degeneracy:
(Bilinearity)
Formula 135 holds.
e(g1γ,g2{circumflex over (γ)})=e(g1,g2)γ{circumflex over (γ)} for all γ,{circumflex over (γ)}∈ [Formula 135]
(Non-Degeneracy)
Formula 136 holds. Note that Formula 137 denotes an identity element of the group GT.
e(g1,g2)≠ [Formula 136]
[Formula 137]
In the following description, let GBPG( ) be a bilinear group generation algorithm. That is, GBPG is an algorithm that generates paramG.
<Dual Pairing Vector Spaces (hereinafter, DPVS)>
Note that paramv, which is DPVS, indicated in Formula 138 is formed by the direct product of paramG, which is a bilinear group, and paramv includes a prime q, a d-dimensional vector space V=G1d and a d-dimensional vector space V*=G2d over the field Fq under vector addition and scalar multiplication defined for each element, canonical bases At, indicated in Formula 139, of the vector space V and the vector space V*, and a pairing operation e indicated in Formula 140.
In Formula 139, Formula 141 is identity elements.
,
[Formula 141]
The map e in paramv has the following two properties of bilinearity and non-degeneracy:
(Bilinearity)
Formula 142 holds.
e(γv,{circumflex over (γ)}w)=e(v,w)γ{circumflex over (γ)} for all γ,{circumflex over (γ)}∈q,v ∈
,w ∈
* [Formula 142]
(Non-degeneracy)
Formula 143 holds.
Formula 143 holds even if v and w are interchanged.
For a basis W of the vector space V (or the vector space V*) indicated in Formula 144 and a vector v→ ∈Fqd, Formula 145 denotes a vector of the vector space V (or the vector space V*) formed by a linear combination of elements of the basis W and elements of the vector v→. That is, Formula 145 denotes Formula 146.
For a set of vectors indicated in Formula 147, Formula 148 denotes a subspace of the vector space V formed by the set of vectors indicated in Formula 147.
{v(i)}i∈[s]of (or
*),s ∈
[Formula 147]
SPANv(i)|i ∈[s]
[Formula 148]
In the following description, let GDPVS(1λ, d) be a DPVS generation algorithm. That is, GDPVS is an algorithm that takes as input a unary encoded security parameter 1λ and a natural number d indicating a dimension, and generates paramv with a d-dimensional vector space V and a d-dimensional vector space V.
In the first embodiment, ABS is realized using a collision-resistant hash function. Therefore, the collision-resistant hash function to be used in the first embodiment will be described.
<Collision-Resistant Hash Function>
A hash function family H, which is related to a bilinear group generation function GBPG and a polynomial poly(·) is composed of two polynomial-time algorithms, a KGen algorithm and a H(λ,polykh algorithm.
The KGen algorithm is a hash key generation algorithm. The KGen algorithm is a probabilistic algorithm that takes as input a unary encoded security parameter 1λ, and samples a hash key hk from a key space HKλ. The key space HKλ is a probabilistic space on a bit string parameterized by λ.
The H(λ,poly)kh algorithm is a function that performs mapping indicated in Formula 149.
={0,1}poly(λ)→
q\{0}
[Formula 149]
That is, the H(λ,poly)kh algorithm is a deterministic function that takes as input a unary encoded security parameter 1λ, and maps an element of D={0, 1}poly(λ) to an element of the field Fq excluding 0. Note q is the first element of paramG, which is the output of the bilinear group generation function GBPG.
In the following description, it is assumed that q indicated in Formula 150 is a certain prime, and Formula 151 denotes a class of all functions indicated in Formula 152. In Formula 152, p is an arbitrary polynomial realized by a certain polynomial-sized ABP over the field Fq.
q∈ [Formula 150]
ABP(q) [Formula 151]
ƒ: qn→
q for any n=p(λ)∈
[Formula 152]
In the first embodiment, the ABS scheme for a predicate family R(q)Z-ABP indicated in Formula 153 will be described.
Z-ABP(q)={
Z-ABP(q)(f,·):
qn→{0,1}|f:
qn→
q∈
ABP(q)}[Formula 153]
Note that Formula 154 holds.
Z-ABP(q)(f,
Z-ABP(q)(f,
for all f: qn→
q∈
ABP(q),
qn [Formula 154]
As stated in the description of ASP, there exists a polynomial-time algorithm that generates an access structure S of ASP indicated in Formula 156 for an input of any function f indicated in Formula 155.
ƒ: qn→
q∈
ABP(q) [Formula 155]
=(
,ρ) [Formula 156]
such that for any qn, it holds that
Z-ABP(q)(f,
accepts
In Formula 156, Formula 157 signifies R(q)Z-ABP(f, x→)=1, f(x→)=0, and that the access structure S accept x→ are equivalent.
Z-ABP(q)(f,
[Formula 157]
In the following description, it is assumed that a predicate R(q)Z-ABP(f, ·) ∈ R(q)Z-ABP is identified by an access structure S=(U, ρ), which is a corresponding ASP representation computed by a polynomial-time algorithm.
<Construction of ABS>
The ABS scheme is a scheme for a certain predicate family R(q)Z-ABP including a message space M indicated in Formula 158 and a signature space Σ.
⊆{0,1}* [Formula 158]
Note that * in Formula 158 denotes that the number of elements is arbitrary.
The ABS scheme includes a Setup algorithm, a KeyGen algorithm, a Sig algorithm, and a Verify algorithm.
The Setup algorithm takes as input a unary encoded security parameter 1λ, and outputs a public parameter MPK and a master secret key MSK.
The KeyGen algorithm takes as input a public parameter MPK, a master secret key MSK, and an attribute vector x→ indicated in Formula 159, and outputs a signature key SK(x→).
qn for some n=p(λ) ∈
[Formula 159]
The Sig algorithm takes as input a public parameter MPK, an attribute vector x→ indicated in Formula 159, a signature key SK(x→) for the attribute vector x→, an access structure S=(U, ρ), which is an ASP representation of a signature policy R(q)Z-ABP(f, ·):Fnq→{0, 1} ∈ R(q)Z-ABP, and a message MSG ∈ M, and outputs a signature sig or an identification symbol ⊥ indicating a failure.
The Verify algorithm takes as input a public parameter MPK, an access structure S=(U, ρ), which is an ASP representation of a signature policy R(q)Z-ABP(f, ·):Fnq→{0, 1} ∈ R(q)Z-ABP, and a pair of a message MSG ∈ M and a signature sig ∈Σ, and outputs 1 or 0.
<Configuration of Signature System 1>
Referring to
The signature system 1 includes a setup device 10, a key generation device 20, a signature device 30, and a verification device 40. The setup device 10, the key generation device 20, the signature device 30, and the verification device 40 are computers. The setup device 10, the key generation device 20, the signature device 30, and the verification device 40 are connected via communication channels.
Referring to
The setup device 10 is a computer that executes the Setup algorithm.
The setup device 10 includes hardware of a processor 11, a memory 12, a storage 13, and a communication interface 14. The processor 11 is connected with the other hardware components via signal lines and controls these other hardware components.
The setup device 10 includes, as functional components, an acceptance unit 111, a master key generation unit 112, and an output unit 113. The functions of the functional components of the setup device 10 are realized by software.
The storage 13 stores programs for realizing the functions of the functional components of the setup device 10. These programs are read by the processor 11 into the memory 12 and executed by the processor 11. This realizes the functions of the functional components of the setup device 10.
Referring to
The key generation device 20 is a computer that executes the KeyGen algorithm.
The key generation device 20 includes hardware of a processor 21, a memory 22, a storage 23, and a communication interface 24. The processor 21 is connected with the other hardware components via signal lines and controls these other hardware components.
The key generation device 20 includes, as functional components, an acquisition unit 211, a signature key generation unit 212, and an output unit 213. The functions of the functional components of the key generation device 20 are realized by software.
The storage 23 stores programs for realizing the functions of the functional components of the key generation device 20. These programs are read by the processor 21 into the memory 22 and executed by the processor 21. This realizes the functions of the functional components of the key generation device 20.
Referring to
The signature device 30 is a computer that executes the Sig algorithm.
The signature device 30 includes hardware of a processor 31, a memory 32, a storage 33, and a communication interface 34. The processor 31 is connected with the other hardware components via signal lines and controls these other hardware components.
The signature device 30 includes, as functional components, an acquisition unit 311, a signature unit 312, and an output unit 313. The functions of the functional components of the signature device 30 are realized by software.
The storage 33 stores programs for realizing the functions of the functional components of the signature device 30. These programs are read by the processor 31 into the memory 32 and executed by the processor 31. This realizes the functions of the functional components of the signature device 30.
Referring to
The verification device 40 is a computer that executes the Verify algorithm.
The verification device 40 includes hardware of a processor 41, a memory 42, a storage 43, and a communication interface 44. The processor 41 is connected with the other hardware components via signal lines and controls these other hardware components.
The verification device 40 includes, as functional components, an acquisition unit 411, a verification data generation unit 412, and a verification unit 413. The functions of the functional components of the verification device 40 are realized by software.
The storage 43 stores programs for realizing the functions of the functional components of the verification device 40. These programs are read by the processor 41 into the memory 42 and executed by the processor 41. This realizes the functions of the functional components of the verification device 40.
Each of the processors 11, 21, 31, and 41 is an integrated circuit (IC) that performs processing. Specific examples of each of the processors 11, 21, 31, and 41 are a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU).
Each of the memories 12, 22, 32, and 42 is a storage device to temporarily store data. Specific examples of each of the memories 12, 22, 32, and 42 are a static random access memory (SRAM) and a dynamic random access memory (DRAM).
Each of the storages 13, 23, 33, and 43 is a storage device to store data. A specific example of each of the storages 13, 23, 33, and 43 is a hard disk drive (HDD). Alternatively, each of the storages 13, 23, 33, and 43 may be a portable recording medium, such as a Secure Digital (SD, registered trademark) memory card, CompactFlash (CF, registered trademark), a NAND flash, a flexible disk, an optical disc, a compact disc, a Blu-ray (registered trademark) disc, or a digital versatile disc (DVD).
Each of the communication interfaces 14, 24, 34, and 44 is an interface for communicating with external devices. Specific examples of each of the communication interfaces 14, 24, 34, and 44 are an Ethernet (registered trademark) port, a Universal Serial Bus (USB) port, and a High-Definition Multimedia Interface (HDMI, registered trademark) port.
Referring to
In the following description, a function p in the description of ASP does not need to be injective. Therefore, the ABS scheme to be described below supports multiple uses of unlimited attributes in a signature policy. “Unlimited” signifies that the number of attributes is not limited by the public parameter MPK. “Multiple uses” signifies that the same attribute can be used at multiple places.
Referring to
The operation of the setup device 10 according to the first embodiment corresponds to a setup method according to the first embodiment. The operation of the setup device 10 according to the first embodiment also corresponds to processes of a setup program according to the first embodiment.
(Step S11: Acceptance Process)
The acceptance unit 111 accepts input of a unary encoded security parameter 1λ. The acceptance unit 111 writes the security parameter 1λ in the memory 12.
(Step S12: Basis Generation Process)
The master key generation unit 112 generates params and orthonormal dual bases {Bι, B*ι }ι
Specifically, the master key generation unit 112 retrieves the security parameter 1λ from the memory 12. The master key generation unit 112 executes an algorithm GOB indicated in Formula 160, where N=2, d0=4, d1=14, and d2=8, to generate params and the dual bases {Bι, B*ι }ι
(Step S13: Partial Basis Generation Process)
The master key generation unit 112 generates a partial basis B{circumflex over ( )}ι and a partial basis B{circumflex over ( )}*ι from the dual bases {Bι, B*ι }ι
Specifically, the master key generation unit 112 retrieves params and the dual bases {Bι, B*ι }ι
0={b(0,1),b(0,4)},
0*={b*(0,3)},
1={b(1,1), . . . ,b(1,4),b(1,13),b(1,14)},
1*={b(1,1), . . . ,b*(1,4),b*(1,11),b*(1,12)},
2={b(2,1),b(2,2),b(2,7)b(2,8)},
2*={b(2,1),b*(2,2)b*(2,5),b*(2,6)} [Formula 161]
(Step S14: Hash Key Generation Process)
The master key generation unit 112 samples a hash key hk by the KGen algorithm, as indicated in Formula 162.
Note that the KGen algorithm is an algorithm for a hash function family H related to a bilinear group generation function GBPG and a polynomial poly(·). The polynomial poly(λ) represents the length of a bit string formed by concatenating a message belonging to a message space M and a binary ASP representation representing a signature policy predicate in a predicate family R(q)Z-ABP.
(Step S15: Master Key Setting Process)
The master key generation unit 112 sets, as a public parameter MPK, params generated in step S12, the partial basis B{circumflex over ( )}ι and the partial basis B{circumflex over ( )}*ι for each integer ι of ι ∈ [0, 2] generated in step S13, and the hash key hk generated in step S14. The master key generation unit 112 sets a basis vector b*(0,1) as a master secret key MSK.
Then, the master key generation unit 112 writes the public parameter MPK and the master secret key MSK in the memory 12.
(Step S16: Output Process)
The output unit 113 outputs the public parameter MPK and the master secret key MSK that are set in step S15.
Specifically, the output unit 113 retrieves the public parameter MPK and the master secret key MSK from the memory 12. The output unit 113 publishes the public parameter MPK by a method such as transmitting the public parameter MPK to a server for publication. This allows the key generation device 20, the signature device 30, and the verification device 40 to acquire the public parameter MPK. The output unit 113 transmits the master secret key MSK to the key generation device 20 in secrecy. To transmit in secrecy means to transmit after encryption by an existing encryption scheme, for example.
That is, the setup device 10 executes the Setup algorithm indicated in Formula 163.
Referring to
The operation of the key generation device 20 according to the first embodiment corresponds to a key generation method according to the first embodiment. The operation of the key generation device 20 according to the first embodiment also corresponds to processes of a key generation program according to the first embodiment.
(Step S21: Acquisition Process)
The acquisition unit 211 acquires the public parameter MPK and the master secret key MSK that are output in step S16. The acquisition unit 211 acquires an attribute vector x→∈ Fnq. The attribute vector x→ here is an attribute of a user of a signature key SK(x→) to be generated. Note that n in the attribute vector x→∈Fnq represents the number of elements in the attribute vector x→. That is, the attribute vector x→=(x1, . . . , xn), where n is an integer of 1 or more.
The acquisition unit 211 writes the public parameter MPK, the master secret key MSK, and the attribute vector x→ in the memory 22.
(Step S22: Signature Key Generation Process)
The signature key generation unit 212 samples a random number ω and a random number φ0 to generate an element k*(0), as indicated in Formula 164.
The signature key generation unit 212 samples a random number 6t and a random number φ→(l) to generate an element k*(ι), for each integer ι of ι ∈ [n], as indicated in Formula 165.
A basis vector b*(1,1) and a basis vector b*(1,2) of the basis B*1 are an index part, and σι (1, ι) set in the index part as a coefficient is index information I* associated with an element xι of the attribute vector x→. The index information I* is such that the sum of element-wise inner products of the index information I* and corresponding index information I, which is used in the Verify algorithm to be described later, becomes 0.
The signature key generation unit 212 samples a random number φ→(n+1,1) and a random number φ→(n+1,2) to generate an element k*(n+1,1) and an element k*(n+1,2), as indicated in Formula 166.
The signature key generation unit 212 writes the element k*(0), the element k*(ι) for each integer ι of ι ∈ [n], the element k*(n+1,1), and the element k*(n+1,2) in the memory 22 as the signature key SK(x→).
(Step S23: Output Process)
The output unit 213 outputs the signature key SK(x→) generated in step S22.
Specifically, the output unit 213 retrieves the signature key SK(x→) from the memory 22. The output unit 213 transmits the signature key SK(x→) to the signature device 30 in secrecy.
That is, the key generation device 20 executes the KeyGen algorithm indicated in Formula 167.
Referring to
The operation of the signature device 30 according to the first embodiment corresponds to a signature method according to the first embodiment. The operation of the signature device 30 according to the first embodiment also corresponds to processes of a signature program according to the first embodiment.
(Step S31: Acquisition Process)
The acquisition unit 311 acquires the public parameter MPK output in step S16. The acquisition unit 311 acquires the signature key SK(x→) output in step S23.
The acquisition unit 311 acquires the attribute vector x→∈ Fnq of the user, an access structure S, which is an ASP representation of a signature policy R(q)Z-ABP(f, ·):Fnq→*{0, 1} ∈ R(q)Z-ABP, and a message MSG ∈ M. The access structure S is as indicated in Formula 168.
=(
={
qL)2,ρ: [m]→[n] [Formula 168]
L is the number of elements in each of a vector y→(j) and a vector z→(j), and is an integer of 1 or more.
The acquisition unit 311 writes the public parameter MPK, the signature key SK(x→), the attribute vector x→∈ Fnq of the user, the access structure S, and the message MSG in the memory 32.
(Step S32: Determination Process)
The signature unit 312 determines whether the access structure S accepts the attribute vector x→.
If acceptance is determined, the signature unit 312 advances the process to step S33. If acceptance is not determined, the signature unit 312 outputs an identification symbol ⊥ indicating a failure, and ends the process.
(Step S33: Variable Computation Process)
The signature unit 312 computes a scalar (Ωj)j ∈[m] ∈ Fmq indicated in Formula 169.
Note that if and only if Formula 127 holds, the attribute vector x→ indicated in Formula 128 satisfies the access structure S. Therefore, the scalar (Ωj)j∈[m] ∈ Fmq indicated in Formula 169 exists and can be computed.
The signature unit 312 samples a random number a random number ξ, a random number (Ω′j)j∈[m] ∈ Fmq, and a random number (Ω″j)j∈[m] ∈ Fmq indicated in Formula 170.
The signature unit 312 writes the scalar (Ωj)j∈[m], the random number the random number (Ω′j)j∈[m], and the random number (Ω″j)j∈[m] in the memory 32.
(Step S34: Signature Element Generation Process)
The signature unit 312 samples a random number r*(0) to generate an element s*(0), as indicated in Formula 171.
The random number ξ and the random number r*(0) conceal the random number ω and the random number φ0 that are set in the element k*(0) of the signature key SK(x→).
The signature unit 312 samples a random number σ′j and a random number r*(j) to generates an element s*(j), for each integer j of j ∈ [m], as indicated in Formula 172.
The random number ξ and the scalar Ωj conceal the element of the attribute vector x→ set in the element k*(ι) of the signature key SK(x→). The random number Ωj conceals ΩjXρ(j). The random number Ω″j conceals the random number Ω′j.
The random number σ′j conceals the index information I* set in the element k*(ι) of the signature key SK(x→). The random number r*(ι) conceals the random number φ→(l) set in the element k*(ι) of the signature key SK(x→).
The signature unit 312 samples a random number r*(m+1) to generate an element s*(m+1), as indicated in Formula 173.
The random number ξ and the random number r*(m+1) conceal the random number ω, the random number φ→(n+1,1), and the random number φ→(n+1,2) that are set in the element k*(n+1,1) and the element k*(n+1,2) of the signature key SK(x→).
The signature unit 312 writes the element s*(0), the element s*(j) for each integer j of j ∈ [m], and the element s*(m+1) in the memory 32 as a signature sig.
(Step S35: Output Process)
The output unit 313 outputs a pair of the message MSG acquired in step S31 and the signature sig generated in step S34.
Specifically, the output unit 313 retrieves the message MSG and the signature sig from the memory 32. The output unit 313 transmits the message MSG and the signature sig to the verification device 40.
That is, the signature device 30 executes the Sig algorithm indicated in Formula 174.
Referring to
The operation of the verification device 40 according to the first embodiment corresponds to a verification method according to the first embodiment. The operation of the verification device 40 according to the first embodiment also corresponds to processes of a verification program according to the first embodiment.
(Step S41: Acquisition Process)
The acquisition unit 411 acquires the public parameter MPK output in step S16. The acquisition unit 411 acquires the pair of the message MSG and the signature sig output in step S35. The acquisition unit 411 acquires the access structure S, which is the ASP representation of the signature policy R(q)Z-ABP(f, ·):Fnq>{0, 1} ∈ R(q)Z-ABP.
The acquisition unit 411 writes the public parameter MPK, the pair of the message MSG and the signature sig, and the access structure S in the memory 42.
(Step S42: Verification Data Generation Process)
The verification data generation unit 412 samples a random number u→ to generate a variable sj and a variable s′j, which are verification information, for each integer j of j ∈ [m], as indicated in Formula 175.
The verification data generation unit 412 samples a random number u and a random number η0 to generate an element c(0), as indicated in Formula 176.
The verification data generation unit 412 executes the following for each integer j of j ∈ [m].
First, the verification data generation unit 412 determines whether Formula 177 holds for the target integer j.
s*(j)∉1* [Formula 177]
If it holds, the verification data generation unit 412 outputs 0 indicating that the validity of the signature sig cannot be confirmed, and ends the process. If it does not hold, the verification data generation unit 412 samples a random number μj and a random number η→(j) to generate an element c(j) for the target integer j, as indicated in Formula 178.
A basis vector b(1,1) and a basis vector b(1,2) of the basis B1 are an index part. The basis vector b(1,1) and the basis vector b(1,2) of the basis B1 are basis vectors corresponding to the basis vector b*(1,1) and the basis vector b*(1,2) of the basis B*1. The basis vectors corresponding to each other signifies the basis vectors of which an inner product is computed by a pairing operation.
Note that μj(ρ(j), −1) set in the index part as a coefficient is index information I. The index information I is such that the sum of element-wise inner products of the index information I and the corresponding index information I*, which is used in the signature key SK(x→), becomes 0. That these pieces of index information correspond to each other signifies that ι and ρ(j) correspond to each other, and signifies ι=ρ(j).
Specifically, the index information I* is σι (1, ι) and the index information I is μj(ρ(j), −1). Since ι=ρ(j), then σι μj(1·ι-1·ι)=0.
The verification data generation unit 412 samples a random number κ and a random number η→(m+1) to generate an element c(m+1) as indicated in Formula 179.
(Step S43: First Verification Process)
The verification unit 413 determines whether Formula 180 holds.
e(b(0,1),s*(0)= [Formula 180]
If it holds, the verification unit 413 outputs 0 indicating that the validity of the signature sig cannot be confirmed, and ends the process. If it does not hold, the verification unit 413 advances the process to step S44.
(Step S44: Second Verification Process)
The verification unit 413 determines whether Formula 181 holds.
If it holds, the verification unit 413 outputs 1 indicating that the validity of the signature sig has been successfully confirmed, and ends the process. If it does not hold, the verification unit 413 outputs 0 indicating that the validity of the signature sig cannot be confirmed, and ends the process.
As indicated in Formula 182, if the signature sig is valid, Formula 181 holds.
That is, the verification device 40 executes the Verify algorithm indicated in Formula 183.
As described above, the signature system 1 according to the first embodiment realizes the ABS scheme using a predicate vector of ABP. Thus, the ABS scheme that is practical is realized.
The signature system 1 according to the first embodiment sets the index information I* as a coefficient in the index part of the signature key SK(x→), and sets the index information I as a coefficient in the index part of the verification data. If t of the index information I* and ρ(j) of the index information I correspond to each other, the index part becomes 0 when a pairing operation is performed on the element s*(j) of the signature sig and the element c(j) of the verification data. If ι of the index information I* and ρ(j) of the index information I do not correspond to each other, the index part does not become 0 when a pairing operation is performed on the element s*(j) of the signature sig and the element c(j) of the verification data.
This allows security to be secured even when the basis B1 and the basis B*1 that are common to all elements of the attribute vector x→ are used instead of using a different bases for each element of the attribute vector x→. As a result, it is sufficient that the basis B{circumflex over ( )}1 and the basis B{circumflex over ( )}*1 be included in the public parameter MPK, regardless of the number of elements in the attribute vector x→. That is, the number of elements in the attribute vector x→ to be used can be changed arbitrarily without changing the public parameter MPK.
<First Variation>
In the first embodiment, basis vectors of two dimensions are used as the index part. However, provided that the sum of inner products of the index information I* and the index information I becomes 0, basis vectors of any number of dimensions can be used as the index part.
<Second Variation>
In the first embodiment, the functional components are realized by software. However, as a second variation, the functional components may be realized by hardware. With regard to the second variation, differences from the first embodiment will be described.
Referring to
When the functional components are realized by hardware, the setup device 10 includes an electronic circuit 15 in place of the processor 11, the memory 12, and the storage 13. The electronic circuit 15 is a dedicated circuit that realizes the functions of the functional components, the memory 12, and the storage 13.
Referring to
When the functional components are realized by hardware, the key generation device 20 includes an electronic circuit 25 in place of the processor 21, the memory 22, and the storage 23. The electronic circuit 25 is a dedicated circuit that realizes the functions of the functional components, the memory 22, and the storage 23.
Referring to
When the functional components are realized by hardware, the signature device 30 includes an electronic circuit 35 in place of the processor 31, the memory 32, and the storage 33. The electronic circuit 35 is a dedicated circuit that realizes the functions of the functional components, the memory 32, and the storage 33.
Referring to
When the functional components are realized by hardware, the verification device 40 includes an electronic circuit 45 in place of the processor 41, the memory 42, and the storage 43. The electronic circuit 45 is a dedicated circuit that realizes the functions of the functional components, the memory 42, and the storage 43.
Each of the electronic circuits 15, 25, 35, and 45 is assumed to be a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, a logic IC, a gate array (GA), an application specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).
The respective functional components may be realized by one electronic circuit 15, one electronic circuit 25, one electronic circuit 35, and one electronic circuit 45, or the respective functional components may be distributed among and realized by a plurality of electronic circuits 15, a plurality of electronic circuits 25, a plurality of electronic circuits 35, and a plurality of electronic circuits 45.
<Third Variation>
As a third variation, some of the functional components may be realized by hardware, and the rest of the functional components may be realized by software.
Each of the processors 11, 21, 31, 41, the memories 12, 22, 32, 42, the storages 13, 23, 33, 43, and the electronic circuits 15, 25, 35, 45 is also referred to as processing circuitry. That is, the functions of the functional components are realized by the processing circuitry.
Takashima, Katsuyuki, Okamoto, Tatsuaki, Datta, Pratish
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