In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.
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1. A silicon carbide semiconductor device comprising:
an electric field effect transistor including
a silicon carbide semiconductor substrate of a first conductive type having a first impurity concentration;
a drain electrode electrically connected to the back surface of the silicon carbide semiconductor substrate;
a semiconductor layer of the first conductive type formed on the silicon carbide semiconductor substrate and having a second impurity concentration lower than the first impurity concentration;
a first semiconductor region comprising a body layer region formed from the upper surface of the semiconductor layer at an inside of the semiconductor layer and having a second conductive type different from the first conductive type;
a second semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at an inside of the first semiconductor region;
a third semiconductor region of a second conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region, adjacent to the second semiconductor region, and electrically connected to the first semiconductor region;
a fourth semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region separated from the second semiconductor region and the third semiconductor region;
a fifth semiconductor region of the first conductive type formed from the upper surface of the semiconductor layer at the inside of the semiconductor layer in contact with the semiconductor layer and having a third impurity concentration equal to or higher than the second impurity concentration;
a trench formed on the upper surface of the first semiconductor region to be shallower than the first semiconductor region and including a first lateral surface and a second lateral surface facing each other and a third lateral surface intersecting each of the first lateral surface and the second lateral surface;
a gate electrode formed in the trench with a gate insulating film therebetween;
a source electrode formed on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region, wherein
the second semiconductor region is in contact with the first lateral surface or the third lateral surface of the trench, the second lateral surface of the trench is in contact with the fourth semiconductor region, and the third lateral surface of the trench is in contact with the first semiconductor region between the second semiconductor region and the fourth semiconductor region,
the fourth semiconductor region includes a first portion extending in a first direction orthogonal to the third lateral surface of the trench and in contact with the trench and the fifth semiconductor region, and a second portion extending in a second direction orthogonal to the first direction in a plan view and in contact with the fifth semiconductor region,
a plurality of periodic structures each including the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the trench are arranged side by side in the first direction on the upper surface of the semiconductor layer, and
in a plan view, the two first portions and the two second portions form an annular pattern surrounding the second semiconductor region and the third semiconductor region.
8. A power conversion device comprising:
a switching element comprising a silicon carbide semiconductor device including an electric field effect transistor, the silicon carbide semiconductor device comprising
a silicon carbide semiconductor substrate of a first conductive type having a first impurity concentration;
a drain electrode electrically connected to the back surface of the silicon carbide semiconductor substrate;
a semiconductor layer of the first conductive type formed on the silicon carbide semiconductor substrate and having a second impurity concentration lower than the first impurity concentration;
a first semiconductor region comprising a body layer region formed from the upper surface of the semiconductor layer at an inside of the semiconductor layer and having a second conductive type different from the first conductive type;
a second semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at an inside of the first semiconductor region;
a third semiconductor region of a second conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region, adjacent to the second semiconductor region, and electrically connected to the first semiconductor region;
a fourth semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region separated from the second semiconductor region and the third semiconductor region;
a fifth semiconductor region of the first conductive type formed from the upper surface of the semiconductor layer at the inside of the semiconductor layer in contact with the semiconductor layer and having a third impurity concentration equal to or higher than the second impurity concentration;
a trench formed on the upper surface of the first semiconductor region to be shallower than the first semiconductor region and including a first lateral surface and a second lateral surface facing each other and a third lateral surface intersecting each of the first lateral surface and the second lateral surface;
a gate electrode formed in the trench with a gate insulating film therebetween;
a source electrode formed on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region, wherein
the second semiconductor region is in contact with the first lateral surface or the third lateral surface of the trench, the second lateral surface of the trench is in contact with the fourth semiconductor region, and the third lateral surface of the trench is in contact with the first semiconductor region between the second semiconductor region and the fourth semiconductor region,
the fourth semiconductor region includes a first portion extending in a first direction orthogonal to the third lateral surface of the trench and in contact with the trench and the fifth semiconductor region, and a second portion extending in a second direction orthogonal to the first direction in a plan view and in contact with the fifth semiconductor region,
a plurality of periodic structures each including the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the trench are arranged side by side in the first direction on the upper surface of the semiconductor layer, and
in a plan view, the two first portions and the two second portions form an annular pattern surrounding the second semiconductor region and the third semiconductor region.
10. An automobile comprising:
a power conversion device configured to drives wheels of the automobile, the power conversion device including
a silicon carbide semiconductor device including an electric field effect transistor, the silicon carbide semiconductor device comprising
a silicon carbide semiconductor substrate of a first conductive type having a first impurity concentration;
a drain electrode electrically connected to the back surface of the silicon carbide semiconductor substrate;
a semiconductor layer of the first conductive type formed on the silicon carbide semiconductor substrate and having a second impurity concentration lower than the first impurity concentration;
a first semiconductor region comprising a body layer region formed from the upper surface of the semiconductor layer at an inside of the semiconductor layer and having a second conductive type different from the first conductive type;
a second semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at an inside of the first semiconductor region;
a third semiconductor region of a second conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region, adjacent to the second semiconductor region, and electrically connected to the first semiconductor region;
a fourth semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region separated from the second semiconductor region and the third semiconductor region;
a fifth semiconductor region of the first conductive type formed from the upper surface of the semiconductor layer at the inside of the semiconductor layer in contact with the semiconductor layer and having a third impurity concentration equal to or higher than the second impurity concentration;
a trench formed on the upper surface of the first semiconductor region to be shallower than the first semiconductor region and including a first lateral surface and a second lateral surface facing each other and a third lateral surface intersecting each of the first lateral surface and the second lateral surface;
a gate electrode formed in the trench with a gate insulating film therebetween;
a source electrode formed on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region, wherein
the second semiconductor region is in contact with the first lateral surface or the third lateral surface of the trench, the second lateral surface of the trench is in contact with the fourth semiconductor region, and the third lateral surface of the trench is in contact with the first semiconductor region between the second semiconductor region and the fourth semiconductor region,
the fourth semiconductor region Includes a first portion extending in a first direction orthogonal to the third lateral surface of the trench and in contact with the trench and the fifth semiconductor region, and a second portion extending in a second direction orthogonal to the first direction in a plan view and in contact with the fifth semiconductor region,
a plurality of periodic structures each including the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the trench are arranged side by side in the first direction on the upper surface of the semiconductor layer, and
in a plan view, the two first portions and the two second portions form an annular pattern surrounding the second semiconductor region and the third semiconductor region.
11. A railway vehicle comprising:
a power conversion device configured to drive wheels of the railway vehicle, the power conversion device including
a silicon carbide semiconductor device including an electric field effect transistor, the silicon carbide semiconductor device comprising
a silicon carbide semiconductor substrate of a first conductive type having a first impurity concentration;
a drain electrode electrically connected to the back surface of the silicon carbide semiconductor substrate;
a semiconductor layer of the first conductive type formed on the silicon carbide semiconductor substrate and having a second impurity concentration lower than the first impurity concentration;
a first semiconductor region comprising a body layer region formed from the upper surface of the semiconductor layer at an inside of the semiconductor layer and having a second conductive type different from the first conductive type;
a second semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at an inside of the first semiconductor region;
a third semiconductor region of a second conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region, adjacent to the second semiconductor region, and electrically connected to the first semiconductor region;
a fourth semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region separated from the second semiconductor region and the third semiconductor region;
a fifth semiconductor region of the first conductive type formed from the upper surface of the semiconductor layer at the inside of the semiconductor layer in contact with the semiconductor layer and having a third impurity concentration equal to or higher than the second impurity concentration;
a trench formed on the upper surface of the first semiconductor region to be shallower than the first semiconductor region and including a first lateral surface and a second lateral surface facing each other and a third lateral surface intersecting each of the first lateral surface and the second lateral surface;
a gate electrode formed in the trench with a gate insulating film therebetween;
a source electrode formed on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region, wherein
the second semiconductor region is in contact with the first lateral surface or the third lateral surface of the trench, the second lateral surface of the trench is in contact with the fourth semiconductor region, and the third lateral surface of the trench is in contact with the first semiconductor region between the second semiconductor region and the fourth semiconductor region,
the fourth semiconductor region Includes a first portion extending in a first direction orthogonal to the third lateral surface of the trench and in contact with the trench and the fifth semiconductor region, and a second portion extending in a second direction orthogonal to the first direction in a plan view and in contact with the fifth semiconductor region,
a plurality of periodic structures each including the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the trench are arranged side by side in the first direction on the upper surface of the semiconductor layer, and
in a plan view, the two first portions and the two second portions form an annular pattern surrounding the second semiconductor region and the third semiconductor region.
9. A three-phase motor system for driving a three-phase motor by converting DC power into AC power, the three-phase motor system comprising:
a power conversion device including
a silicon carbide semiconductor device including an electric field effect transistor, the silicon carbide semiconductor device comprising
a silicon carbide semiconductor substrate of a first conductive type having a first impurity concentration;
a drain electrode electrically connected to the back surface of the silicon carbide semiconductor substrate;
a semiconductor layer of the first conductive type formed on the silicon carbide semiconductor substrate and having a second impurity concentration lower than the first impurity concentration;
a first semiconductor region comprising a body layer region formed from the upper surface of the semiconductor layer at an inside of the semiconductor layer and having a second conductive type different from the first conductive type;
a second semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at an inside of the first semiconductor region;
a third semiconductor region of a second conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region, adjacent to the second semiconductor region, and electrically connected to the first semiconductor region;
a fourth semiconductor region of the first conductive type formed from the upper surface of the first semiconductor region at the inside of the first semiconductor region separated from the second semiconductor region and the third semiconductor region;
a fifth semiconductor region of the first conductive type formed from the upper surface of the semiconductor layer at the inside of the semiconductor layer in contact with the semiconductor layer and having a third impurity concentration equal to or higher than the second impurity concentration;
a trench formed on the upper surface of the first semiconductor region to be shallower than the first semiconductor region and including a first lateral surface and a second lateral surface facing each other and a third lateral surface intersecting each of the first lateral surface and the second lateral surface;
a gate electrode formed in the trench with a gate insulating film therebetween,
a source electrode formed on the semiconductor layer and electrically connected to the second semiconductor region and the third semiconductor region, wherein
the second semiconductor region is in contact with the first lateral surface or the third lateral surface of the trench, the second lateral surface of the trench is in contact with the fourth semiconductor region, and the third lateral surface of the trench is in contact with the first semiconductor region between the second semiconductor region and the fourth semiconductor region,
the fourth semiconductor region Includes a first portion extending in a first direction orthogonal to the third lateral surface of the trench and in contact with the trench and the fifth semiconductor region, and a second portion extending in a second direction orthogonal to the first direction in a plan view and in contact with the fifth semiconductor region,
a plurality of periodic structures each including the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the trench are arranged side by side in the first direction on the upper surface of the semiconductor layer, and
in a plan view, the two first portions and the two second portions form an annular pattern surrounding the second semiconductor region and the third semiconductor region.
2. The silicon carbide semiconductor device according to
in a plan view, the fifth semiconductor region forms an annular pattern surrounding the fourth semiconductor region.
3. The silicon carbide semiconductor device according to
in a plan view, among the periodic structures adjacent to each other, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the trench constituting one of the periodic structures adjacent to each other are not connected to any of the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the trench constituting another periodic structure, and
the fifth semiconductor regions constituting each of the periodic structures adjacent to each other are connected to each other.
4. The silicon carbide semiconductor device according to
the second portion is separated from the trench.
5. The silicon carbide semiconductor device according to
a first electrode formed on the semiconductor layer and electrically connected to the source electrode, wherein
the first electrode and the fifth semiconductor region are connected by a Schottky junction.
6. The silicon carbide semiconductor device according to
the second semiconductor region extends in the first direction and overlaps the plurality of trenches in a plan view, and
both ends in each of the plurality of trenches in the second direction form the periodic structure and are in contact with the two first portions sandwiching the second semiconductor region in a plan view.
7. The silicon carbide semiconductor device according to
the periodic structures adjacent to each other in the lateral direction of the periodic structure are arranged at positions shifted by half a cycle in the longitudinal direction of the periodic structure.
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The present invention relates to a silicon carbide semiconductor device, which is a power semiconductor device, particularly having a trench structure, a power conversion device, a three-phase motor system, an automobile, and a railway vehicle.
In the power metal insulator semiconductor field effect transistor (MISFET), which is one of the power semiconductor devices, in the related art, the power MISFET using a silicon (Si) substrate (hereinafter referred to as Si power MISFET) has been in the mainstream.
However, a power MISFET using a silicon carbide (SiC) substrate (hereinafter referred to as a SiC substrate) (hereinafter referred to as a SiC power MISFET) can have a higher withstand voltage and a lower loss than an Si power MISFET. For this reason, particular attention has been paid to the field of power saving or environment-friendly inverter technology.
The SiC power MISFET can reduce the on-resistance with the same withstand voltage compared with the Si power MISFET. This is because silicon carbide (SiC) has a dielectric breakdown electric field strength of about 7 times as large as that of silicon (Si), and the epitaxial layer serving as a drift layer can be made thinner. However, considering the original characteristics that should be obtained from silicon carbide (SiC), it cannot be said that sufficient characteristics have been obtained yet, and further reduction of on-resistance is desired from the viewpoint of highly efficient use of energy. Further, since the power MISFET using SiC is driven by a larger electric field than the one using Si, the insulating film electric field is also significantly increased and the reliability of the insulating film may be lowered.
In the conventional double diffused metal oxide semiconductor (DMOS) structure, the channel parasitic resistance is relatively high. On the other hand, WO-A-2015/177914 (PTL 1) describes that the (11-20) plane or the (1-100) plane, which is the lateral surface of the trench formed on the upper surface of the substrate of the (0001) plane and has high mobility, is used as a channel to widen the effective channel width. According to this technique, the channel parasitic resistance can be reduced and the on-resistance can be reduced without impairing the reliability of the dielectric breakdown at the bottom of the trench in the OFF state. Hereinafter, this structure is referred to as a trench type DMOS.
Further, WO-A-2016/116998 (PTL 2) discloses that the electric field of the insulating film is significantly reduced and the reliability of the trench type DMOS is increased by forming a shallow impurity region (hereinafter referred to as an electric field relaxation layer) having the same polarity as the body layer on the upper surface of the substrate.
However, the trench type DMOS of PTLs 1 and 2 has a drawback in that the path length of the JFET region existing in the body layer becomes long and the JFET resistance becomes large.
An object of the present invention is to provide a silicon carbide semiconductor device having a significantly improved performance by adopting a unit cell (periodic structure) of a trench type DMOS capable of reducing JFET resistance and by adopting a cell arrangement suitable for an anisotropic unit cell.
The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.
A brief overview of typical embodiments disclosed in the present application is as follows.
The silicon carbide semiconductor device according to one embodiment increases the peripheral length of the JFET region in the unit cell of the trench type DMOS. Specifically, an island-shaped cell structure is formed by surrounding the unit cell with a current diffusion region in a plan view.
Among the inventions disclosed in the present application, the effects obtained by representative ones will be briefly described as follows.
According to the present invention, it is possible to provide a high-performance and highly reliable silicon carbide semiconductor device. As a result, it is possible to realize the high performance of power conversion devices, three-phase motor systems, automobiles, and railway vehicles.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for illustrating the embodiments, the members having the same function are designated by the same reference numerals and the repeated description thereof will be omitted. Further, in the following embodiments, the description of the same or similar portions is not repeated in principle unless it is particularly necessary. Further, in the drawings for illustrating the embodiments, hatching may be added even in a plan view or a perspective view in order to make the configuration easy to understand. Further, in the drawings for illustrating the embodiments, hatching may be omitted in the cross-sectional view in order to make the configuration easy to understand.
Further, in the drawings used in the following description, the electric field relaxation layer described in PTL 2 is omitted, but the structure can be similarly applied to the structure shown in the present embodiment. In that case, an electric field relaxation layer is formed on the JFET region and the current diffusion region adjacent to the substrate surface.
Further, “−” and “+” are codes indicating the relative impurity concentrations of the n-type or p-type conductive type, and, for example, the impurity concentration of the n-type impurity increases in the order of “n−−”, “n−”, “n”, “n+”, and “n++”.
<Details of Room for Improvement>
The details of the room for improvement will be described below with reference to
As shown in
A p-type body layer (well region) 3 having a predetermined depth from the upper surface of the epitaxial layer 2 is formed in the epitaxial layer 2, and the body layer 3 is electrically connected to a source electrode via a p++ type body layer contact region 7 formed in a central portion of the upper surface of the body layer 3. Further, an n++ type source region 5 having a predetermined depth from the surface of the epitaxial layer 2 and containing nitrogen as an impurity is formed in the body layer 3 and is electrically formed with the source electrode. The arrangement relationship between the body layer contact region 7 and the source region 5 is not limited to the line pattern shown in
A JFET region 4a having a predetermined depth from the upper surface of the epitaxial layer 2 is formed in the epitaxial layers 2 at both ends of the unit cell of the SiC power MISFET shown in
In this way, one unit cell is arranged in the order from the end of the unit cell in the X direction toward the central portion of the unit cell in the X direction and includes the JFET region 4a, the current diffusion region 6a, the body layer 3, the source region 5, and the body layer contact region 7, which extend in the Y direction, respectively. Further, one unit cell has a plane layout that is line-symmetrical in the X direction with the body layer contact region 7 as the center in the X direction, and the body layer 3 is formed below each of the current diffusion region 6a, the source region 5, and the body layer contact region 7.
Further, as a component of the unit cell, a plurality of trenches 8 extending from the n++ type source region 5 across the p-type body layer 3 so as to span over the n+ type current diffusion region 6a are formed to be arranged in the Y direction. That is, among the lateral surfaces of the trench 8, the source region 5 is formed on one of the two lateral surfaces facing each other in the X direction, the current diffusion region 6a is formed on the other one, and the body layer 3 is formed on the other lateral surfaces (the two lateral surfaces facing each other in the Y direction). The bottom surface of the trench 8 is in contact with the p-type body layer 3. A gate electrode (not shown) is formed on the trench 8 with a gate insulating film (not shown) therebetween. When the gate electrode is on, the electrons flowing through the SiC power MISFET pass from the n++ type source region 5 through the p-type body layer 3 on the lateral surface of the trench 8, which is the channel region adjacent to the gate electrode, and moves to the n-type JFET region 4a, the n− type epitaxial layer 2, the n+ type SiC substrate that is the drain region, and the drain wiring electrode (not shown) at the bottom of the SiC substrate in the indicated order.
As shown in
As described above, since the trench type DMOS is an element whose characteristics greatly differ depending on the plane orientation of the channel, forming an element having a plane other than the (11-20) plane and the (1-100) plane as the channel causes unexpected operation of the silicon carbide semiconductor device and fluctuations in the timing at which the SiC power MISFET is turned on. Therefore, in order to align the channel directions in the X direction, all the JFET regions 4a and the n+ type current diffusion region 6a extend in the Y direction orthogonal to the X direction, which is the extending direction of the channel forming surface. The layout of the unit cells may be longer in the Y direction than the structure shown in
The length Ptr shown in
The cell area is Ptr×2×(Wstr+Wcon), and one JFET region having a length Ptr and two trenches 8 are present therein. Therefore, the channel density (JFET number density) Djfet and the trench density Dtr are represented by the following Equations 1 and 2, respectively.
Djfet=1/(2×(Wstr+Wcon))[L−1] (Equation 1)
Dtr=1/(Ptr×(Wstr+Wcon))[L−2] (Equation 2)
In Equations 1 and 2, L is the dimension of length. The JFET resistance is inversely proportional to the channel density Djfet. The channel resistance is inversely proportional to the trench density Dtr.
As is clear from the order of the dimensions, when the actual structure width Wstr or the contact width Wcon becomes smaller due to the scaling (reduction) of the cell pitch, the channel resistance, which is inversely proportional to the trench density Dtr whose dimension is to the second power, decreases sharply, but the JFET resistance, which is inversely proportional to the channel density Djfet whose dimension is to the first power, is difficult to decrease. The trench density Dtr can be easily increased by shortening the opening length Ptr in the mask for forming the trench 8. Further, since the channel mobility of the trench type DMOS is several times larger than that of the flat type DMOS having no trench, the channel resistance can be easily reduced in the trench type DMOS, and the channel resistance can be reduced to almost 0. On the other hand, since the channel density Djfet is rate-determined by the actual structure width Wstr determined by the device parameters, the JFET resistance cannot be reduced and remains at high resistance.
That is, the trench type DMOS of the comparative example has a problem that the path length of the JFET region 4a becomes long and the JFET resistance becomes large. Since the JFET region 4a has a higher current density than the drift region, a large JFET resistance becomes a big problem especially in a device driven by a large current. Although the JFET resistance can be reduced by employing a design having a wide JFET width, there is a limit to the increase in the JFET width because the cell pitch in the X direction increases and the withstand voltage decreases.
As described above, reducing the JFET resistance in the silicon carbide semiconductor device provided with the trench type DMOS exists as room for improvement.
Therefore, in the embodiments of the present application, a device is devised to solve the above-mentioned room for improvement. In the following, the technical idea in the embodiments in which the present device is applied will be described.
Hereinafter, a SiC power MISFET having a lateral surface in a trench (groove, recess) as a channel region, that is, a trench type DMOS will be taken as an example and a silicon carbide semiconductor device will be described with reference to the drawings.
<Structure of Silicon Carbide Semiconductor Device>
The structure of the silicon carbide semiconductor device according to Embodiment 1 will be described with reference to
As shown in
A gate electrode of the SiC power MISFET, an n++ type source region, a channel region, and the like are formed on the upper surface side of the active region of the SiC epitaxial substrate, and an n+ type drain region of the SiC power MISFET is formed on the back surface side of the SiC epitaxial substrate. Each of the plurality of floating field limiting rings 102 is composed of a p-type semiconductor region formed at a predetermined depth from the upper surface of the SiC epitaxial substrate. The guard ring 103 is composed of an n-type semiconductor region formed at a predetermined depth from the upper surface of the SiC epitaxial substrate.
By forming a plurality of p-type floating field limiting rings 102 around the active region, the maximum electric field portion sequentially moves to the outer floating field limiting ring 102 when the SiC power MISFET is turned off and yields at the outermost floating field limiting ring 102. Thereby, the withstand voltage of the silicon carbide semiconductor device can be increased.
The plurality of SiC power MISFETs formed in the active region have an island-like pattern in a plan view. That is, the plurality of SiC power MISFETs constitute a plurality of unit cells (periodic structure), and each of the unit cells has an island-shaped planar layout and is arranged so as to be separated from each other. The gate electrode (not shown) of the island-shaped SiC power MISFET is electrically connected to the gate wiring electrode 104 by a lead wiring (gate bus line) existing on the outer peripheral portion of the semiconductor chip 101.
Further, the plurality of SiC power MISFETs are covered with the source wiring electrodes 106, and the source region of each SiC power MISFET and the potential fixing layer of the body layer are connected to the source wiring electrode 106. The source wiring electrode 106 is connected to an external wiring (not shown) through a source opening 107 provided in the insulating film. The gate wiring electrode 104 is formed so as to be separated from the source wiring electrode 106 and is connected to each gate electrode of the plurality of SiC power MISFETs. The gate wiring electrode 104 is connected to an external wiring (not shown) through a gate opening 105. The external wiring referred to here is wiring (for example, a bonding wire) for electrically connecting the semiconductor chip 101 and an external device of the semiconductor chip 101. Further, the n+ type drain region formed on the back surface side of the n-type SiC epitaxial substrate is electrically connected to the drain wiring electrode (not shown) formed so as to cover the entire back surface of the n-type SiC epitaxial substrate.
Next, the structure of the unit cell of the SiC power MISFET, which is the silicon carbide semiconductor device of the present embodiment, will be described with reference to
As shown in
As shown in
In other words, the body layer 3 is formed in the epitaxial layer 2 from the upper surface of the epitaxial layer 2 to the intermediate depth of the epitaxial layer 2, and the source region 5, a current diffusion region 6, and the body layer contact region 7 are respectively formed from the upper surface of the body layer 3 to the intermediate depth of the body layer 3. Further, a JFET region 4 is formed from the upper surface of the epitaxial layer 2 to the intermediate depth of the epitaxial layer 2.
In a plan view, the JFET region 4 is formed in the epitaxial layer 2 around the body layer 3 constituting the unit cell to have a predetermined depth from the upper surface of the epitaxial layer 2. That is, the JFET region 4 is in contact with the epitaxial layer 2. The JFET region 4 is an n-type semiconductor region between the body layers 3 of adjacent unit cells in a plan view. The n-type impurity concentration in the JFET region 4 may be the same as the n-type impurity concentration in the epitaxial layer 2 but may be higher than the n-type impurity concentration in the epitaxial layer 2. The current diffusion region 6, which is an n+ type semiconductor region having a predetermined depth from the upper surface of the epitaxial layer 2, is formed between the body layer 3 and the JFET region 4. The current diffusion region 6 is formed from the upper surface of the body layer 3 to the intermediate depth of the body layer 3, and in a plan view, the current diffusion region 6 is formed in an annular shape to surround the body layer contact region 7, the source region 5, and the body layer 3. Among the ends of the current diffusion region 6, the end opposite to the source region 5 does not overlap with the body layer 3 in a plan view and is formed in the epitaxial layer 2 adjacent to the body layer 3.
Each of the current diffusion region 6 and the JFET region 4 is composed of a rectangular annular pattern including a pattern extending in the Y direction and a pattern extending in the X direction. Further, since the body layer 3 is formed between the source region 5 and the body layer contact region 7, and the current diffusion region 6 on the upper surface of the epitaxial layer 2, the body layer 3 is composed of a rectangular annular pattern including a pattern extending in the Y direction and a pattern extending in the X direction in a plan view.
One unit cell has a plane layout that is line-symmetrical in the X direction with the body layer contact region 7 as the center in the X direction. The body layer contact region 7 and the source region 5 are in contact with each other. Further, the source region 5 and the body layer 3 are in contact with each other, and the current diffusion region 6 and the body layer 3 are in contact with each other. The current diffusion region 6 and the JFET region 4 are in contact with each other.
As described above, one unit cell of the SiC power MISFET includes the body layer contact region 7, the source regions 5 sandwiching the body layer contact region 7 in the X direction, and the current diffusion region 6 and the JFET region 4 which have an annular shape and surround the body layer contact region 7 and the source region 5 in the indicated order, and the body layer 3.
Further, as a component of the unit cell, a plurality of trenches 8 extending from the n++ type source region 5 across the p-type body layer 3 so as to span over the n+ type current diffusion region 6 are formed side by side in the Y direction. That is, among the lateral surfaces of the trench 8, the source region 5 is in contact with one of the two lateral surfaces facing each other in the X direction, the current diffusion region 6 is in contact with the other side, and the body layer 3 between the source region 5 and the current diffusion region 6 is in contact with the other lateral surfaces (the lateral surfaces facing each other in the Y direction). The trench 8 is formed deeper than both the source region 5 and the current diffusion region 6 and is formed shallower than the body layer 3. Therefore, the bottom surface of the trench 8 is in contact with the p-type body layer 3 and does not reach the epitaxial layer 2 below the body layer 3. The source region 5 and the body layer 3 are in contact with each other on the lateral surface extending in the X direction among the lateral surfaces of the trench 8, and the current diffusion region 6 and the body layer 3 are in contact with each other on the lateral surfaces extending in the X direction among the lateral surfaces of the trench 8. The body layer contact region 7 is in contact with the body layer 3 at both ends in the Y direction.
The current diffusion region 6, the body layer contact region 7, and the source region 5 are separated from each other in a plan view. The current diffusion region 6 is composed of a Y-axis line (first portion) which extends in the Y direction and is in contact with the trench 8 and the JFET region 4, and an X-axis line (second portion) which extends in the X direction and is separated from the trench 8 and in contact with the JFET region 4. In one unit cell, the two Y-axis lines and the two X-axis lines of the current diffusion region 6 form an annular pattern.
The trench 8 is formed so as to overlap only the pattern extending in the Y direction (Y-axis line) of the body layer 3 in a plan view and does not overlap the pattern extending in the X direction (X-axis line) in the plan view. In other words, the trench 8 is formed between the source region 5 and the current diffusion region 6 adjacent in the X direction, but the trench 8 is not formed between the source region 5 and the current diffusion region 6 adjacent in the Y direction. This is because, in the trench type DMOS, the trench can not be extended only in a specific direction due to the plane orientation anisotropy of the electronic physical characteristics of SiC. That is, as described above, forming an element having a plane other than the (11-20) plane and the (1-100) plane as a channel causes an unexpected operation of the silicon carbide semiconductor device and fluctuations in the timing at which the SiC power MISFET is turned on. Therefore, in order to align the directions of the channels in the X direction, all the trenches 8 are formed between the source region 5 and the current diffusion region 6 adjacent to each other in the X direction so that the channels are formed on the (11-20) plane or the (1-100) plane, which is the lateral surface along the X direction.
As shown in
The current diffusion region 6 has a role to prevent the current from being concentrated to flow in a part of the region due to the electrons that have passed through the body layer 3 flowing downward in the JFET region 4 and heading toward the SiC substrate 1 side at the shortest distance. That is, since the current diffusion region 6 having a relatively high impurity concentration is formed, the electrons that have passed through the body layer 3 are diffused in the current diffusion region 6 and flows uniformly in the n-type semiconductor region including the current diffusion region 6 and the JFET region 4.
An interlayer insulating film 11 made of, for example, a silicon oxide film is formed on each of the epitaxial layer 2, the gate insulating film 9, and the gate electrode 10. The laminated film composed of the gate insulating film 9 and the interlayer insulating film 11 includes a through hole at a position separated from the gate electrode 10, and the source plug 12, which is a conductive connection portion, is formed in the through hole. The source plug 12 is electrically connected to the body layer contact region 7 and the source region 5. The source plug 12, and the body layer contact region 7, and the source region 5 may be directly connected to each other or may be connected to each other via another metal film or silicide layer. The source plug 12 is electrically connected to the source wiring electrode 106 (see
In the SiC power MISFET having an island structure according to the present embodiment, the laminated structure of each semiconductor region (impurity region) in the Z direction is the same as the striped structure of the comparative example, but the arrangement in the XY plane is different. In the present embodiment, the striped structure is arranged for a certain period at the central portion of the unit cell in the Y direction, and at the end of the unit cell in the Y direction, the impurity regions in the order of the body layer 3 surrounding the body layer contact region 7 and the source region 5, the current diffusion region 6, and the JFET region 4 are terminated. In this structure, the four sides around the unit cell are the JFET region 4. A configuration in which a plurality of island-shaped unit cells are arranged in the element region will be described later in Embodiment 4.
Next,
Next,
Although the gate insulating film 9 (see
The source electrode (source plug 12) is terminated inside the outer end of the annular body layer 3 in a plan view. However, when the electric field relaxation layer described in PTL 2 is formed on the current diffusion region 6, the source electrode may be present as long as the source electrode is on the region where the electric field relaxation layer exists. Even if there is no electric field relaxation layer on the JFET region 4 extending in the X direction, if the JFET structure is properly designed and the contact between the source electrode and the JFET region 4 is a Schottky junction, the source electrode may exist on the JFET region 4.
Here, the source electrode is formed so as to cover the entire body layer contact region 7 and the source region 5 adjacent to the body layer contact region 7 in the X direction, and the end of the source electrode in the Y direction overlaps the body layer 3 extending in the X direction in a plan view. However, the source electrode may be formed separately in the unit cell. Further, regarding the junction between the source electrode and the epitaxial layer 2 (see
When the source electrode is arranged so as to form a Schottky junction between the JFET region 4 and a part of the source electrodes, the source electrode and the JFET region 4 operate as a Schottky barrier diode, and thus, it is possible to reduce the deterioration of energization during bipolar operation of the elements constituting a silicon carbide semiconductor device.
That is, in the SiC power MISFET, when a basal plane dislocation (BPD) is formed in the epitaxial layer on the SiC substrate and electrons and holes recombine in the region where the BPD is formed, the energy released by the recombination causes the crystals in the epitaxial layer to shift. As a result, surface defects called Shockley type stacking faults spread in the epitaxial layer. Since such stacking faults hinder the movement of electrons flowing in the longitudinal direction in the epitaxial layer (drift layer), in the SiC power MISFET in which the stacking faults have spread, the element resistance (substrate resistance) and the forward voltage (on voltage) increase. These stacking faults continue to expand due to the flow of electrons and holes into the SiC epitaxial substrate when the SiC power MISFET is operated, and thus, the resistance between the source and drain and the resistance of the built-in diode increase with the passage of energization time. That is, problems are generated that the characteristics of the SiC power MISFET change due to the deterioration of energization, and the performance and reliability of the silicon carbide semiconductor device deteriorate.
Such a phenomenon particularly occurs when a current flows through the built-in diode (pn diode) formed between the p-type body layer contact region 7 and the body layer 3 shown in
The depth (first depth) from the upper surface of the epitaxial layer 2 of the p-type body layer 3 shown in
Among the patterns of the semiconductor region constituting the unit cell, the number of trenches 8 existing on the body layer 3 extending in the Y direction in a plan view can be arbitrarily set in consideration of the balance between the channel resistance and the JFET resistance as long as the number is at least 1 or more.
The preferable range of the impurity concentration of the n′ type SiC substrate 1 is, for example, 1×1018 to 1×1021 cm−3. The preferable range of the impurity concentration of the n− type epitaxial layer 2 is, for example, 1×1014 to 1×1017 cm−3. The preferable range of the impurity concentration of the p-type body layer 3 is, for example, 1×1016 to 1×1019 cm−3. The preferable range of the maximum impurity concentration of the p-type body layer 3 is, for example, 1×1017 to 1×1019 cm−3. The preferable range of the impurity concentration in the n++ type source region 5 is, for example, 1×1019 to 1×1021 cm−3. The preferable range of the impurity concentration in the n+ type current diffusion region 6 is, for example, 5×1016 to 5×1018 cm−3. The preferable range of the impurity concentration in the n-type JFET region 4 is, for example, 1×1015 to 1×1018 cm−3. The preferable range of the impurity concentration in the p++ type body layer contact region 7 is, for example, the range of 1×1019 to 1×1021 cm−3.
<Effect of the Present Embodiment>
Next, the features and effects of the structure of the SiC power MISFET according to the present embodiment will be described.
In the present embodiment, the unit cells of the SiC power MISFET are not formed in a line shape as in the comparative example shown in
As a result, the entire JFET region 4 is effectively utilized without forming a trench in the body layer 3 extending in the X direction in a plan view, that is, the X-axis line of the body layer 3, and the current paths of the current diffusion region 6 and the JFET region 4 are increased. Therefore, it is possible to reduce the resistance (JFET resistance) of the SiC power MISFET.
Here, the effect of the structure of the SiC power MISFET according to the present embodiment will be described with reference to
A cell area Acell, the JFET density (JFET number density) Djfet, and the channel density (trench density) Dtr can be calculated by the following Equations 3 to 5, respectively. Ntr is the number of trenches arranged in the Y direction per cell, and when the number of left and right trenches sandwiching the body layer contact region is totaled, the number of trenches per cell is 2×Ntr.
Acell=2×(Wstr+Wcon)×(Ntr×Ptr+2×Wstr) (Equation 3)
Djfet=(4×Wstr+2×Wcon+Ntr×Ptr)/(2×(Wstr+Wcon)×(Ntr×Ptr+2×Wstr)) (Equation 4)
Dtr=(2×Ntr×Ptr)/(2×(Wstr+Wcon)×(Ntr×Ptr+2×Wstr)) (Equation 5)
In a high withstand voltage element having a withstand voltage (rated withstand voltage) of 3.3 kV or the like, it is considered that the ratio of the channel resistance to the JFET resistance is 2:8 as described above. Regarding the calculation results of the above graph, the design parameters such as the JFET width or the margin are designed to be the same among the striped structure, the island structure, and the butterfly structure.
Since the magnitude of the decrease in JFET resistance due to the increase in JFET density is larger than the magnitude of the increase in channel resistance due to the decrease in the number of channels due to the decrease in the number of trenches, the total resistance at Ntr=10 becomes the minimum value, and the resistance can be reduced by about 10% in the SiC power MISFET having an island structure as compared with the SiC power MISFET having a striped structure. If the ratio of channel resistance is further reduced by reducing the distance between trenches, the resistance can be expected to be reduced by, for example, 30%.
Here, as shown in
Furthermore, by utilizing the high-dimensional structure, the JFET width can be changed in the X and Y directions, or by adding a Schottky barrier diode (SBD) function, it is possible to give new functionality not found in the striped structure. For example, since there is no trench in the X-axis line, the JFET width can be widened only in the X-axis line where it is not necessary to consider the electric field in the vicinity of the trench 8 to greatly reduce the resistance. Further, by controlling the avalanche breakdown position of the element on the X-axis line where the channel does not exist, it is possible to prevent the induced breakdown of the insulating film. The provision of the SBD will be described later in Modifications 1 and 2 of the present embodiment.
Further, in the island structure in the DMOS having no trench, the insulating film electric field between the island-shaped unit cells (gap of the island structure) becomes large, and the insulating film reliability is low due to the difficulty of predicting the electric field. On the other hand, in the trench type DMOS that can adopt the electric field relaxation layer of PTL 2, the insulating film electric field between the island-shaped unit cells (gap of the island structure) is almost 0 and it is possible to improve the performance without lowering the reliability.
From the above, according to the structure of the present embodiment, it is possible to provide a SiC power MISFET having high reliability and high performance by reducing the JFET resistance while maintaining the advantage of the trench type DMOS that the reliability against the dielectric breakdown of the trench bottom at the time of off is high. That is, the reliability and performance of the silicon carbide semiconductor device can be improved. Further, it is possible to provide a SiC power MISFET in which new functions such as control of an avalanche breakdown position and suppression of the deterioration of energization can be easily implemented.
In the present embodiment, it has been described that the current diffusion region 6 is formed in an annular shape, but since the JFET resistance can be reduced if the current diffusion region 6 extending in the X direction is formed, the X-axis line of the current diffusion region 6 may be interrupted in the middle. The JFET region 4 and the body layer 3 are in contact with each other at a portion where the current diffusion region 6 is interrupted in a plan view.
<Manufacturing Method of Silicon Carbide Semiconductor Device>
The silicon carbide semiconductor device according to the present embodiment can be basically manufactured by a procedure based on the manufacturing methods described in PTLs 1 and 2. Since the only point to be changed is the mask used for photolithography, it is possible to improve the performance of the SiC power MISFET without the need to introduce a special process.
<Modification 1>
Hereinafter, the silicon carbide semiconductor device of Modification 1 of the present embodiment will be described with reference to
As shown in
The plug 14 is formed directly above the JFET regions 4 at both ends in the X direction of the unit cell and extends in the Y direction. For example, the plugs 14 of the unit cells adjacent to each other in the Y direction are connected to each other. Unlike the structure shown in
If the SBD is used as the current path when operating in the reverse direction, the operation mode can be changed from the bipolar of the pn diode to the unipolar of the SBD, and the deterioration of performance and reliability due to the expansion of stacking faults can be prevented.
When manufacturing the silicon carbide semiconductor device having the above-mentioned SBD function, the plug 14 may be formed in a process different from the process of forming the source plug 12. That is, first, a through hole for opening the interlayer insulating film 11 is formed directly above each of the body layer contact region 7 and the source region 5 in the central portion of the island structure. Subsequently, a silicide layer that is ohmically connected to each of the body layer contact region 7 and the source region 5 is formed at the bottom of the through hole. Next, a through hole that opens directly above the JFET region 4 extending in the Y direction is formed, and then a conductor film that embeds the above two types of through holes is formed without forming a silicide layer. As a result, the source electrode made of the conductor film is ohmically connected to each of the body layer contact region 7 and the source region 5 and is connected to the JFET region 4 by a Schottky junction. This makes it possible to manufacture a silicon carbide semiconductor device in which the SBD function is provided only in a desired portion.
<Modification 2>
As shown in
Here, the plug 15 for forming the SBD is formed at a position aligned with the source plug 12 in the Y direction. That is, the plug 15 is formed directly above the JFET regions 4 at both ends in the Y direction of the unit cell. The plug 15 may be in contact with the current diffusion region 6 in addition to the JFET region 4.
In this modification, the same effect as that of Modification 1 of the present embodiment can be obtained. The silicon carbide semiconductor device of the present modification can be formed by the same manufacturing process as that of Modification 1 of the present embodiment.
The horizontal axis of the graph shown in
In a low withstand voltage element having a withstand voltage (rated withstand voltage) of 600 V or the like, the ratio of the channel resistance to the JFET resistance is considered to be 4:6 as described above. Regarding the calculation results of the above graph, the design parameters such as the JFET width or the margin are designed to be the same among the striped structure, the island structure, and the butterfly structure.
From
<Structure of Silicon Carbide Semiconductor Device>
Hereinafter, the SiC power MISFET of the present embodiment will be described with reference to
As shown in
That is, the unit cell of the SiC power MISFET of the present embodiment includes a source region 25 extending in the Y direction in a plan view, a pair of body layer contact regions 17 arranged so as to sandwich the central portion in the Y direction of the source region 25 in the X direction, and a body layer 23 formed so as to surround a portion other than the portion where the body layer contact regions 17 are in contact with the source region 25 in a plan view. That is, the body layer 23 is divided into two by the body layer contact region 17 in a plan view, and each of the two body layer contact regions 17 is in contact with both of the pair of body layers 23 in a plan view. In other words, the source region 25 is completely surrounded by the body layer contact region 17 and the body layer 23. Further, the unit cell includes the annular current diffusion region 6 and the JFET region 4 that sequentially surround the source region 25, the body layer contact region 17, and the body layer 23 in a plan view. Further, the unit cell includes a plurality of trenches 18, which are formed adjacent to the pair of body layer contact regions 17 in the Y direction and over the source region 25 and the body layer 23 sandwiching the source region 25 in the X direction, and have both ends (both lateral surfaces) in the X direction in contact with the current diffusion region 6 in a plan view.
The trench 18 extends uninterrupted above each of the body layer 23 and the source region 25 between the source region 25 and the current diffusion region 6 sandwiching the body layer 23 in the X direction. Unlike Embodiment 1, the source region 25 is formed deeper than the trench 18, and the source region 25 is also formed on the bottom surface of the trench 18 in addition to the body layer 23. The source region 25 is in contact with each of the lateral surfaces of the trench 18 facing each other in the X direction. The source plug 12 is electrically connected to the lateral surface (channel forming surface) of the trench 18 via the source region 25. That is, the electrons supplied from the source plug 12 during the operation of the SiC power MISFET flow through the source region 25 that is formed deeper than the trench 18 with respect to the lateral surface of the trench 18 on which the channel is formed, and extends in the Y direction so as to overlap the plurality of trenches 18 in a plan view. The gate electrode 10 is formed so as to completely cover the trench 18. In
The number of trenches 18 existing on one lateral side of the source plug 12 in the Y direction does not have to be the same as the number of trenches 18 existing on the other lateral side of the source plug 12 in the Y direction. Therefore, the number of trenches 18 possessed by the unit cell may be odd or even, and the degree of freedom in the number of trenches 18 is not impaired. However, since the gate controllability of the trench 18 far from the body layer contact region 17 is lowered, it is desirable that the difference in the number of trenches 18 is small.
According to such a butterfly structure, the width (cell pitch) of the unit cell in the X direction can be reduced by not forming the source plug extending in the Y direction at the center of the unit cell of the island structure. Since the source plug 12 needs to have a wider dimension than the semiconductor region (impurity region) and a thick insulating film needs to be formed between the gate electrode and the source plug, the cell pitch in the X direction can be reduced by 30 to 40% by arranging the source plug 12 as in the present embodiment. Further, in the present embodiment, the three-dimensional corners of the trench 18, that is, the corners of the four corners of the bottom surface of the trench 18 are not formed in the source region 5 having a high impurity concentration. Therefore, the withstand voltage between the gate and the source, which is a problem of the trench structure, can be improved.
Next, the simulation results of the resistance reduction effect in the structure of the SiC power MISFET according to the present embodiment will be described with reference to
According to the butterfly structure of the present embodiment, the channel density and the JFET density can be increased at the same time by reducing the cell pitch, so that the resistance can be significantly reduced. In an element with Rch:Rjfet=2:8 (for example, a high withstand voltage element) as shown in
If Ntr is too large, the distance between the trench and the body layer contact region will increase, and the body potential will separate from the source potential. Therefore, it is desirable that the Ntr is 16 or less as a realistic range that does not affect the operation of the SiC power MISFET. In that case, resistance can be reduced by about 28% even with Rch:Rjfet=4:6.
According to the present embodiment, the same effect as that of Embodiment 1 can be obtained, and further, the withstand voltage between the gate and the source, which is a problem of the element having a trench structure, is improved and the channel resistance can be reduced at the same time together with the larger reduction of the JFET resistance. Furthermore, by reducing the cell pitch, it is possible to reduce the channel-on voltage at the time of a short circuit, improve thermal diffusivity and temperature uniformity, and improve the trade-off between on-resistance and short-circuit tolerance. From the above, with the butterfly structure of the present embodiment, it is possible to provide a highly reliable, high-performance, and highly functional SiC power MISFET that can significantly reduce the resistance and implement the functionality while maintaining the high reliability of the trench type DMOS having the striped structure of the comparative example, and further improve dynamic reliability such as short-circuit tolerance when compared with the reliability of the DMOS having no trench.
<Manufacturing Method of Silicon Carbide Semiconductor Device>
Since the only difference between Embodiment 1 and the present embodiment is the planar layout of the silicon carbide semiconductor device, the silicon carbide semiconductor device according to the present embodiment can be manufactured by the same process as that of Embodiment 1.
In Embodiment 3, reducing the resistance of the SiC power MISFET having a striped structure instead of the island structure will be described with reference to
That is, the plurality of unit cells arranged in the Y direction have a structure in which one source region 35 extending in the Y direction and one body layer 33 extending in the Y direction are shared, and a current diffusion region 36 and a JFET region 34 have a line shape extending in the Y direction instead of an annular shape. That is, one unit cell includes the source region 35 extending in the Y direction, a pair of body layer contact regions 17 adjacent to the source region 35 in the X direction and sandwiching the source region 35, and the body layer 33 adjacent to the lateral surface of the source region 35 in the X direction other than the portion in which the source region 35 and the body layer contact region 17 are in contact with each other and extending in the Y direction. Further, one unit cell includes a current diffusion region 36 which is adjacent to the lateral surface opposite to the source region 35 side among the lateral surfaces of the source region 35 and the lateral surface of the body layer 33 and extends in the Y direction, and a JFET region 34 which sandwiches the source region 35, the body layer contact region 17, the body layer 3, and the current diffusion region 36 in the X direction and extends in the Y direction in contact with the lateral surface of the current diffusion region 36. Further, one unit cell includes the trench 18 which is formed adjacent to the pair of body layer contact regions 17 in the Y direction and over the source region 35 and the body layer 33 sandwiching the source region 35 in the X direction to be in contact with the current diffusion region 6 in a plan view.
In the present embodiment, the increase in JFET density is limited to the decrease in cell pitch as compared with Embodiment 2. That is, as compared with the comparative example shown in
From the above, according to the structure of Embodiment 3, it is possible to provide a highly reliable and high-performance SiC power MISFET that can significantly reduce especially the channel resistance while maintaining the high reliability of the striped trench type DMOS similar to that of the comparative example, and further improve dynamic reliability such as the short-circuit tolerance, and the like.
The silicon carbide semiconductor device of the present embodiment can be manufactured by the same process as that of Embodiment 1.
Hereinafter, the arrangement of a plurality of unit cells of the SiC power MISFET according to Embodiment 4 will be described with reference to
When an island structure is adopted in the SiC power MISFET, the effective JFET width becomes large at a unit cell intersection 40, the electric field non-uniformity becomes strong, the decrease in avalanche withstand voltage or the increase in insulating film electric field occurs, which makes the reliability of the SiC power MISFET deteriorated. Therefore, it is necessary to arrange the unit cells so as to minimize the electric field non-uniformity. The unit cell intersection 40 is a point where the largest number of unit cells are in contact with each other in a plan view, and is, for example, a point farthest from the center of a predetermined unit cell in a plan view.
Since the cell pitch of the trench type DMOS is different between the X direction and the Y direction, the offset can be geometrically provided in either the X direction or the Y direction. However, since the electric field non-uniformity depends on the distance between the unit cell intersections 40, the distance can be set to be larger due to the offset as the cell pitch in the axial direction is longer, which is preferable. That is, as the distance between the unit cell intersections 40 increases, the electric field non-uniformity can be reduced. Further, when the unit cells adjacent to each other in the X direction are offset in the Y direction as in the present embodiment, the electric field non-uniformity can be minimized by setting the offset amount Ly to half the cell pitch in the Y direction. Therefore, it is possible to prevent a decrease in the avalanche withstand voltage or an increase in the insulating film electric field, and thus, the reliability of the silicon carbide semiconductor device can be improved.
A current diffusion region 46 and a JFET region 44 are formed in the indicated order from the terminal portion of the active region in the Y direction toward the central portion of the active region. The current diffusion region 46 is integrated with the current diffusion region 46 of the unit cell for half a cycle formed at the terminal portion of the active region in the Y direction. Further, the JFET region 44 is adjacent to the JFET region 44 of the unit cell in the active region.
Further, the source region 45 and the body layer contact region 47 of the unit cell for half a cycle formed at the terminal portion of the active region in the Y direction, and the body layer 43 below the source region 45 and the body layer contact region 47, respectively, have reached the terminal portion. The JFET width Wjfety of the JFET region 44 at the terminal portion may be different from the JFET width Wjfety of the unit cell, but even if the value is the same as that of the unit cell, the electric field uniformity is higher than that of the unit cell intersection 40 (see
Further, according to such a terminal structure, the current diffusion region 46 is arranged at the terminal portion of the active region, and the current diffusion region 46 is connected to the current diffusion region 46 of the unit cell in the vicinity of the terminal portion. Thereby, the current can be diffused even in the terminal portion and the JFET region can be utilized to the maximum extent to reduce the resistance (JFET resistance) of the SiC power MISFET.
As described above, according to the present embodiment, it is possible to prevent a decrease in reliability due to the application of the island structure and to realize a low-loss and high-performance SiC power MISFET while maintaining high reliability.
The silicon carbide semiconductor device having the SiC power MISFET described in Embodiments 1 to 4 can be used as a power conversion device. A power conversion device according to Embodiment 5 will be described with reference to
As shown in
That is, in the load 301, two SiCMISFETs 304 and two diodes 305 are provided in each single phase, and six SiCMISFETs (switching elements) 304 and six diodes 305 are provided in three phases. A control circuit 303 is connected to the gate electrode of each SiCMISFET 304, and the SiCMISFET 304 is controlled by the control circuit 303. Therefore, the load 301 can be driven by controlling the current flowing through the SiCMISFET 304 constituting the inverter 302 with the control circuit 303. The SiCMISFET 304 and the diode 305, which are connected in antiparallel to each other, are, for example, separate elements and are not mounted in the same semiconductor chip.
The functions of the SiCMISFET 304 constituting the inverter 302 will be described below. In order to control and drive the load 301, for example, the motor, it is necessary to input a sine wave of a desired voltage to the load 301. The control circuit 303 controls the SiCMISFET 304 and performs a pulse width modulation operation that dynamically changes the pulse width of the square wave. The output square wave is smoothed by passing through the inductor to become a pseudo desired sine wave. The SiCMISFET 304 has the function of creating a square wave for performing this pulse width modulation operation.
As described above, according to the present embodiment, the SiCMISFET 304 uses the silicon carbide semiconductor device with low on-resistance and high withstand voltage described in Embodiments 1 to 4. As described above, since the SiCMISFET 304 has high performance, it is possible to improve the performance of a power conversion device such as an inverter. Further, since the SiCMISFET 304 has long-term reliability, the number of years of use of a power conversion device such as an inverter can be extended.
Further, the power conversion device can be used for a three-phase motor system. When the load 301 shown in
The silicon carbide semiconductor device including the SiC power MISFET described in Embodiments 1 to 4 can be used as a power conversion device. The power conversion device according to Embodiment 6 will be described with reference to
As shown in
The functions of the SiCMISFET 404 constituting the inverter 402 will be described below. Also in the present embodiment, as one of the functions of the SiCMISFET, the SiCMISFET has a function of creating a square wave for performing a pulse width modulation operation as in Embodiment 5. Further, in the present embodiment, the SiCMISFET also plays the role of the diode 305 of Embodiment 5. In the inverter 402, for example, when the load 401 includes an inductance like a motor and the SiCMISFET 404 is turned off, the energy stored in the inductance has to be released (recirculation current). In Embodiment 5, the diode 305 plays this role. In this way, the diode 305 is used as a recirculation diode. On the other hand, in the present embodiment, the SiCMISFET 404 plays this role. That is, a synchronous rectification drive is used. Here, the synchronous rectification drive is a method in which the gate of the SiCMISFET 404 is turned on at the time of recirculation to reverse-conduct the SiCMISFET 404.
Therefore, the conduction loss at recirculation is determined not by the characteristics of the diode but by the characteristics of the SiCMISFET 404. Further, when the synchronous rectification drive is performed, a non-operation time is required in which both the upper and lower SiCMISFETs 404 are turned off in order to prevent the upper and lower arms from being short-circuited. During this non-operation time, the built-in PN diode composed of the n-type drift layer and the p-type body layer of the SiCMISFET 404 is driven. However, SiC has a shorter carrier mileage than Si and the loss during non-operation time is small. For example, it is equivalent to the case where the diode 305 of Embodiment 2 is a SiC Schottky barrier diode.
As described above, according to the present embodiment, by using the silicon carbide semiconductor device described in Embodiments 1 to 4 for the SiCMISFET 404, for example, the high performance of the SiCMISFET 404 can also reduce the loss during recirculation. Further, since a diode is not used except for the SiCMISFET 404, the power conversion device such as an inverter can be miniaturized. Further, since the SiCMISFET 404 has long-term reliability, the number of years of use of a power conversion device such as an inverter can be extended.
Further, the power conversion device can be used for a three-phase motor system. When the load 401 shown in
The three-phase motor system described in Embodiment 5 or 6 can be used in an automobile such as a hybrid automobile, an electric vehicle, or a fuel cell vehicle. The automobile using the three-phase motor system according to Embodiment 7 will be described with reference to
As shown in
The three-phase motor 503 is a synchronous generator motor including a rotor in which a permanent magnet is embedded and a stator in which a three-phase coil is wound. As the inverter 504, the inverter described in Embodiment 5 or 6 can be used. The synchronous generator motor receives power supplied from the inverter to drive the drive wheels 501a and 501b.
As shown in
The electronic control unit 510 of
As described above, according to the present embodiment, the power conversion device described in Embodiment 5 or 6 can be used for the inverter 504 and the boost converter 508, which are the power conversion devices. Further, the three-phase motor system described in Embodiment 5 or 6 can be used for the three-phase motor system including the three-phase motor 503 and the inverter 504. As a result, it is possible to achieve energy saving, downsizing, weight reduction, and space saving of the electric vehicle.
Although the electric vehicle has been described in the present embodiment, the three-phase motor system of each of the above-described embodiments is also similarly applied to the hybrid vehicle in which the engine is also used and the fuel cell vehicle in which the battery 505 is a fuel cell stack.
The three-phase motor system described in Embodiment 5 or 6 can be used for a railway vehicle. The railway vehicle using the three-phase motor system according to Embodiment 8 will be described with reference to
As shown in
The element configuration in the converter 607 may be a combination of a SiCMISFET and a diode as in Embodiment 5, or a single SiCMISFET as in Embodiment 6. In this embodiment, for example, a diagram composed of a SiCMISFET 604 as in Embodiment 6 is shown. In
As described above, according to the present embodiment, the power conversion device described in Embodiment 5 or 6 can be used for the converter 607. Further, the three-phase motor system described in Embodiment 5 or 6 can be used for the three-phase motor system including the load 601, the inverter 602, and the control circuit. As a result, it is possible to save energy in railway vehicles and to reduce the size and weight of underfloor parts.
Although the inventions made by the present inventors have been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.
For example, it is needless to say that the material, conductive type, manufacturing conditions, and the like of each unit are not limited to the description of the above-described embodiments and various modifications thereof can be made. Here, for convenience of explanation, the conductive type of the semiconductor substrate and the semiconductor film has been fixed and described, but the present invention is not limited to the conductive type described in the above-described embodiments.
The present invention can be widely used in silicon carbide semiconductor devices, and power conversion devices, three-phase motor systems, automobiles, and railway vehicles equipped with the same.
Watanabe, Naoki, Hisamoto, Digh, Tega, Naoki, Mori, Yuki, Suto, Takeru
| Patent | Priority | Assignee | Title |
| Patent | Priority | Assignee | Title |
| 10290704, | Feb 12 2015 | HITACHI POWER SEMICONDUCTOR DEVICE, LTD | Semiconductor device and method for manufacturing same, power conversion device, three-phase motor system, automobile, and railway carriage |
| 5828101, | Mar 30 1995 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
| 6118149, | Mar 17 1997 | Kabushiki Kaisha Toshiba | Trench gate MOSFET |
| 6452231, | Jul 31 1997 | Kabushiki Kaisha Toshiba | Semiconductor device |
| 6525375, | Oct 19 1999 | Denso Corporation | Semiconductor device having trench filled up with gate electrode |
| 7470960, | Oct 27 1999 | KANSAI ELECTRIC POWER CO , INC | High-voltage power semiconductor device with body regions of alternating conductivity and decreasing thickness |
| 8283721, | Mar 26 2008 | ROHM CO , LTD | Semiconductor device, and method for manufacturing the same |
| 8304329, | Dec 01 2008 | MAXPOWER SEMICONDUCTOR INC | Power device structures and methods |
| 8354715, | Sep 09 2009 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| 8658503, | Sep 09 2009 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| 9117800, | Jun 15 2012 | ROHM CO , LTD | Switching device |
| 9437592, | Jun 15 2012 | Rohm Co., Ltd. | Switching device |
| 9793376, | Aug 07 2012 | Denso Corporation; Toyota Jidosha Kabushiki Kaisha | Silicon carbide semiconductor device and method of manufacturing the same |
| 9818860, | Jun 13 2012 | Denso Corporation; Toyota Jidosha Kabushiki Kaisha | Silicon carbide semiconductor device and method for producing the same |
| 20030001203, | |||
| 20030205758, | |||
| 20040021173, | |||
| 20060226439, | |||
| 20080135925, | |||
| 20090057711, | |||
| 20100327654, | |||
| 20110057202, | |||
| 20110291110, | |||
| 20120012861, | |||
| 20120043606, | |||
| 20120319136, | |||
| 20140103364, | |||
| 20150236127, | |||
| 20160247881, | |||
| 20160344303, | |||
| 20170084735, | |||
| 20170330961, | |||
| 20180331174, | |||
| DE112015004751, | |||
| EP893830, | |||
| JP11103058, | |||
| JP1273821, | |||
| JP2001274398, | |||
| JP2002110983, | |||
| JP2005524975, | |||
| JP2009224811, | |||
| JP2009260253, | |||
| JP2011060930, | |||
| JP2012043955, | |||
| JP2012169386, | |||
| JP2012191056, | |||
| JP2014003051, | |||
| JP8264764, | |||
| JP8330601, | |||
| WO2010110246, | |||
| WO2015177914, | |||
| WO2016116998, | |||
| WO2016129068, |
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| May 21 2021 | HISAMOTO, DIGH | Hitachi, LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 056599 | /0826 | |
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