A semiconductor structure includes a first finfet device disposed over a substrate, a second finfet device disposed over the substrate, and an isolation structure. The first finfet device includes at least a first fin and a first metal gate structure over the first fin. The second finfet device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.
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5. A method for forming a semiconductor structure, comprising:
forming a first finfet device and a second finfet device over a substrate;
forming a metal gate feature coupling the first finfet device and the second finfet device;
cutting the metal gate feature to form a trench interrupting the metal gate feature;
performing a flowable chemical vapor deposition (fcvd) to form a dielectric material to fill the trench;
performing a nitrogen-containing treatment to form a dielectric layer under the dielectric material; and
performing a uv curing to convert the dielectric material into a dielectric feature over the dielectric layer.
16. A method for forming a semiconductor structure, comprising:
forming a first finfet device, a second finfet device and a dielectric structure surrounding the first finfet device and the second finfet device;
forming a metal gate feature coupling the first finfet device and the second finfet device;
removing a portion of the metal gate feature to form a trench to cut the metal gate feature to form a first metal gate structure in the first finfet device and a second metal gate structure in the second finfet device;
performing a nitrogen-containing treatment to form a dielectric layer in the trench;
performing a flowable chemical vapor deposition (fcvd) to form a dielectric material to fill the trench after the nitrogen-containing treatment; and
performing a uv curing to convert the dielectric material into a dielectric feature over the dielectric layer.
1. A method for forming a semiconductor structure, comprising:
forming a first finfet device, a second finfet device and a dielectric structure over a substrate, wherein the dielectric structure surrounds the first finfet device and the second finfet device;
forming a first trench in the first finfet device and the second finfet device;
forming a metal gate feature in the first trench;
removing a portion of the metal gate feature to form a second trench in the metal gate feature; and
forming an isolation structure in the second trench, wherein the forming of the isolation structure further comprises:
performing a flowable chemical vapor deposition (fcvd) to form a dielectric material in the second trench;
performing a nitrogen-containing treatment to form a dielectric layer after the fcvd; and
performing a uv curing to cure the dielectric material to form a dielectric feature after the nitrogen-containing treatment,
wherein the isolation structure comprises the dielectric layer and the dielectric feature over the dielectric layer, and the dielectric layer and the dielectric feature comprise different dielectric materials.
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a first sidewall exposing the metal gate feature; and
a second sidewall exposing the dielectric structure.
13. The method of
14. The method
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18. The method of
19. The method of
a first sidewall exposing the metal gate feature; and
a second sidewall exposing the dielectric structure.
20. The method of
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The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices that are able to support greater numbers of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, low-power integrated circuits (ICs). Thus far, such goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and reducing associated costs. However, such downscaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technology.
As technology nodes achieve progressively smaller scales, in some IC designs, researchers have hoped to replace a typical polysilicon gate with a metal gate to improve device performance by decreasing feature sizes. One approach to forming the metal gate is called a “gate-last” approach, sometimes referred to as a replacement polysilicon gate (RPG) approach. In the RPG approach, the metal gate is fabricated last, which allows for a reduced number of subsequent operations.
Further, as the dimensions of a transistor decrease, the thickness of the transistor's gate dielectric layer may be reduced to maintain performance with a decreased gate length. In order to reduce gate leakage, a high dielectric constant (high-k or HK) gate dielectric layer is used to provide a thickness as effective as that provided by a typical gate oxide used in larger technology nodes. A high-k metal gate (HKMG) approach including a metal gate electrode and the high-k gate dielectric layer is therefore recognized. However, the HKMG approach is a complicated approach, and many issues arise.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the normal deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” or “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” or “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as being from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.
The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.
The present disclosure is generally related to a semiconductor structure and the method for forming the same. Further, the method for forming the semiconductor structure uses a cut metal gate (CMG) process. The term “cut metal gate process” refers to a fabrication process where after a metal gate feature (e.g., a high-k metal gate or HI(MG) replaces a sacrificial gate structure (e.g., a polysilicon gate), the metal gate feature is cut (e.g., by an etching process) to separate the metal gate feature into two or more portions. Each portion functions as a metal gate structure for an individual transistor. An isolation material is subsequently deposited into trenches between the adjacent metal gate structures. These trenches are referred to as cut metal gate trenches, or CMG trenches.
In some comparative approaches, the CMG trenches are filled with high-k dielectric materials. However, devices may suffer from increased capacitance due to the high-k dielectric materials. In some embodiments, a low-k dielectric material may be used to replace the high-k dielectric material in order to reduce the capacitance. In such comparative approaches, the low-k dielectric material may suffer from consumption or damage during subsequently-performed etching in metal-to-device (MD) fabrication. Accordingly, a metal extrusion issue, in which metal is observed in the low-k dielectric material used to fill the CMG trenches, is raised.
As shown in
In some embodiments, the substrate 102 includes a silicon (Si) substrate. In other embodiments, the substrate 102 may include another elementary semiconductor, such as germanium (Ge); a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb); an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium phosphide (AlInP), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GainAs), gallium indium phosphide (GaInP), or gallium indium arsenide phosphide (GaInAsP); or a combination thereof.
The fins 104 are disposed in the fin region 106. In some embodiments, two fins 104 are disposed in each fin region 106, but the disclosure is not limited thereto. The fins 104 include one or more semiconductor materials such as Si, Ge, SiC, GaAs, GaP, InP, InAs, InSb, SiGe, GaAsP, AlInP, AlGaAs, GalnAs, GaInP, and GaInAsP. In some embodiments, the fins 104 may have alternately stacked layers of two different semiconductor materials, such as layers of Si and SiGe alternately stacked. The fins 104 may additionally include dopants for improving the performance of the FinFET device. For example, the fins 104 may include n-type dopant(s) such as phosphorus (P) or arsenic (As), or p-type dopant(s) such as boron (B) or indium (In).
The isolation structure 108 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating materials. The isolation structure 108 may include shallow trench isolation (STI) features. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures are possible. The isolation structure 108 may include a multi-layer structure, for example, a structure with one or more thermal oxide liner layers adjacent to the fins 104.
As mentioned above, the metal gate structures 110 include the high-k gate dielectric layer 112 and the gate conductive layer 114. The high-k gate dielectric layer 112 may include one or more high-k dielectric materials (or one or more layers of high-k dielectric materials), such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO2), alumina (Al2O3), zirconium oxide (ZrO2), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), strontium titanate (SrTiO3), or a combination thereof. The gate conductive layer 114 includes one or more metal layers, such as work function metal layer(s), conductive barrier layer(s), and gap-filling metal layer(s). The work function metal layer may be a p-type or an n-type work function layer depending on the type (PFET or NFET) of the device. The p-type work function layer comprises a metal with a sufficiently large effective work function, selected from but not restricted to the group of titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), and combinations thereof. The n-type work function layer comprises a metal with sufficiently low effective work function, selected from but not restricted to the group of titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), and combinations thereof. The gap-filling metal layer may include Al, W, cobalt (Co), and/or other suitable materials.
The isolation structure 120 includes a dielectric layer 122 and a dielectric feature 124. As shown in
In operation 201, a first FinFET device, a second FinFET device and a dielectric structure are formed over a substrate. Referring to
The isolation structure 108 may be formed by one or more deposition and etching methods. The deposition methods may include thermal oxidation, chemical oxidation, and chemical vapor deposition (CVD) such as flowable CVD (FCVD). The etching methods may include dry etching, wet etching, and chemical mechanical planarization (CMP).
Referring to
In some embodiments, spacers 146 are formed over sidewalls of the sacrificial gate structures 140. The spacers 146 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another dielectric material, or combinations thereof, and may include one or multiple layers of material. The spacers 146 may be formed by depositing a spacer material as a blanket over the isolation structure 108, the fins 104, and the sacrificial gate structures 140. Portions of the spacer material are removed from a top surface of the isolation structure 108, a top surface of the hard mask layer 145, and a top surface of the fins 104, while portions of the spacer material remain on the sidewalls of the sacrificial gate structures 140 and serve as the spacer 146.
Referring to
Still referring to
Accordingly, the first FinFET device 150a (including the sacrificial gate structure 140 and the source/drain structures 148), the second FinFET device 150b (including the sacrificial gate structure 140 and the source/drain structures 148), and the dielectric structure 130 are formed over the substrate 102. In some embodiments, the first FinFET device 150a and the second FinFET device 150b are arranged along the first direction D1. Further, the dielectric structure 130 surrounds the first FinFET device 150a and the second FinFET device 150b. In some embodiments, the sacrificial gate structures 140 of the first FinFET device 150a and the second FinFET device 150b are coupled to each other, as shown in
In operation 202, a first trench is formed in the first FinFET device 150a and the second FinFET device 150b.
Still referring to
Referring to
In operation 203, a metal gate feature is formed in the first trench 151.
Referring to
In some embodiments, the metal gate feature 152 extends in the first direction D1 and couples the first FinFET device 150a to the second FinFET device 150b, as shown in
In operation 204, a portion of the metal gate feature 152 is removed to form a second trench.
Referring to
Still referring to
Referring to
In operation 205, an isolation structure is formed in the second trench 159.
Referring to
Referring to
Referring to
Accordingly, in such embodiments, the dielectric feature 124 may include silicon oxide, and the dielectric layer 122 includes N-containing silicon oxide. In some embodiments, a nitrogen concentration of the dielectric layer 122 is approximately 10% greater than a nitrogen concentration of the dielectric feature 124. In some embodiments, the nitrogen concentration of the dielectric layer 122 is approximately 10% to approximately 20% greater than the nitrogen concentration of the dielectric feature 124.
Referring to
In some embodiments, the N-containing treatment 163 is performed to form a dielectric layer 122 in the second trench 159, as shown in
Referring to
Referring to
Referring to
Referring to
Still referring to
Referring to
Referring to
Referring to
Referring to
It should be noted that in some embodiments, during the forming of the third trench 177, an overlay issue may occur, thus the third trench 177 may be formed not only in the dielectric structure 130, but also in the isolation structure 120 (though not shown). In such case, the low-k material of the dielectric feature 124 may be damaged during the etching. Further, the conductive materials used to form the connecting structure 180 may easily diffuse into the dielectric feature 124. Thus, a metal extrusion issue may arise. However, the dielectric layer 122 of the isolation structure 120 is able to withstand the etching and helps to obstruct the metal diffusion. Therefore, the metal extrusion issue is mitigated.
Accordingly, the isolation structure provided by the present disclosure includes the dielectric feature to comply with the low capacitance requirement, and the dielectric layer to mitigate the etching issue and the metal extrusion issue.
According to one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.
According to one embodiment of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a first metal gate structure, a second metal gate structure, and an isolation structure between the first metal gate structure and the second metal gate structure. The first metal gate structure and the second metal gate structure extend in a first direction, and the isolation structure extends in a second direction different from the first direction. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, and between the dielectric feature and the second metal gate structure. The dielectric feature and the dielectric layer include different materials.
According to one embodiment of the present disclosure, a method for forming a semiconductor structure is provided. The method includes the following operations. A first FinFET device, a second FinFET device and a dielectric structure are formed over a substrate. The dielectric structure surrounds the first FinFET device and the second FinFET device. A first trench is formed in the first FinFET device and the second FinFET device. A metal gate feature is formed in the first trench. A portion of the metal gate feature is removed to form a second trench in the metal gate feature. An isolation structure is formed in the second trench. The isolation structure includes a dielectric layer and a dielectric feature over the dielectric layer. The dielectric layer and the dielectric feature include different materials.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Peng, Chih-Tang, Chen, Yung-Chung, Chu, Chia-Ho
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