A device for measuring sheet resistivity of semiconductor materials and diffused layers uses a linear four-point probe having pneumatically-actuated contact pins coupled to a self-zeroing voltage amplifier and a current source having extremely high output resistance.
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1. Apparatus for measuring sheet resistivity of semiconductor materials and diffused layers comprising:
pneumatically operated probe means for applying current to a material to be tested and for detecting a voltage created in the material to be tested by the current applied thereto, said probe means comprising a probe head having a body structure with a main pressure cavity, having first and second sealed inlets and a plurality of probe orifices and a plurality of probe pins fitted to the plurality of probe orifices and positioned therein for passing therethrough in response to pressure being applied to the main pressure cavity; a current source having high output impedance for producing a selected value of current at a range of voltages; self-zeroing voltage amplification means for amplifying the voltage detected by the probe means and producing an output in response to said voltage; means coupled to the first sealed inlet for connecting the current source and the self-zeroing amplification means to the plurality of probe pins; means coupled to the second sealed inlet for applying pressure to the main pressure cavity; and means for applying the probe head to a material to be tested, comprising a lever having a first and second end and pivoted at a point located between said first and second ends, means for coupling the probe head to the second end, a pneumatic cylinder coupled to the lever between the point and the second end for lowering the second end with reference to the first end in response to a control signal, an adjustable stop positioned to limit the movement of the first end, an interlocking system having a first and second microswitch, the first microswitch positioned to actuate when the first end communicates with the adjustable stop and the second microswitch positioned to actuate in response to a material to be tested being in a sample receiving position, and control means coupled to the first and second microswitches for producing a control signal in response to the probe head being in pin contact range of a material to be tested and the material being in a sample receiving position.
2. Apparatus as in
a reference voltage source; a differential amplifier having a first and a second transistor, a base of the first transistor being connected to the reference voltage source; a third transistor having an emitter coupled to a base of the second transistor; a fourth transistor having a base coupled to a collector of the first transistor, an emitter coupled to a collector of the second transistor and a collector coupled to a base of the third transistor; and an operational amplifier having an output and an input coupled to the collector of the third transistor.
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Conventional devices used for measuring sheet resistivity are limited in their measurement range and accuracy by variances in probe pressure, probe spacing and by the circuits employed as a current source and a voltage amplifier. Means for ensuring uniform pin pressure on a sample is required since data consistency is directly affected by the load or force with which each probe is pressed into a sample. The current source must have very high output resistance in order to maintain a selected current value over a wide range of voltages and a large voltage range is required not only by the varied resistances seen between the outer two probes, but also by the potential necessary to achieve avalanche breakdown of point-contact diodes formed when the probes touch lightly-doped wafers. These diodes have typically made the accurate measurement of high resistivity wafers difficult, if not impossible. For low-resistivity wafers, the voltage signal must usually be highly amplified; for example, gains of 105 are not uncommon. Drift in a d.c. amplifier's input offset voltage due to time and temperature variations can mask the actual data when such low magnitude voltages are of interest. Thus, the amplifier must be very stable, or some means of correcting the drift errors must be provided. For high-resistivity wafers, point-contact diodes are also formed at the probes. Since all practical amplifiers require some input bias current, the voltage drop required across these diodes in order to allow this bias current flow produces errors at the input of the voltage amplifier. Some means must be provided for correcting these errors.
The value of sheet resistivity is typically found by dividing voltage by a current and multiplying the result by a constant. Conventional systems set the current equal to this constant. Such a technique does not necessarily yield the most desirable value of current. Furthermore, if various wafer geometries are to be accepted, the constant and thus the current must be variable. This leads to difficulty in accurately setting the current. A better method would be to set the current at the desired value and make the constant adjustable by actually performing a data multiplication.
A probe head having four contact pins pneumatically actuated is coupled to a very accurate current source having three selectable values and a self-compensating voltage amplifier. The three selectable current values are not externally adjustable and are precisely calibrated. A voltage signal is detected by applying the current source to two outermost-positioned contact pins and feeding a detected voltage from the two innermost-positioned contact pins to an amplifier which has the ability to detect error voltages at its input and correct for their effects. This amplifier is initially connected to a test wafer with the current source disabled. The point-contact diode voltages are thus zeroed out of the data as is any input offset voltage of the amplifier. The amplifier has several gain ranges to allow a full-scale output over a large span of input voltages.
The amplified voltage is converted to a binary format by an analog-to-digital converter. This digital data is multiplied by a constant multiplier which is digitally selectable by setting thumbwell switches. The resulting value of sheet resistivity is converted to BCD format for display.
FIG. 1 shows a top view of a probe head made in accordance with a preferred embodiment of the invention.
FIG. 2 is a sectional view of the embodiment of FIG. 1.
FIG. 3 shows a means for applying the probe head of FIG. 1 to a semiconductor device to be measured.
FIG. 4 shows a pneumatic control system for the means of FIG. 3.
FIG. 5 is a block diagram of a system for applying current to and measuring sheet resistivity of a semiconductor wafer.
FIG. 6 is a detailed schematic diagram of a current source made in accordance with a preferred embodiment of the invention.
FIG. 7 is an equivalent functional diagram of the current source of FIG. 6.
FIG. 8 is a schematic diagram of a self-zeroing voltage amplifier made in accordance with a preferred embodiment.
Referring to FIG. 1, a probe head 1 consists of four precision gauge pins 2, 3, 4, 5 which are cut to a length of three-fourths of an inch, machined spherical on one end and gold-plated on the other and are custom fit to a head structure 6 that is made, for example of Teflon AF or the like.
Referring to FIG. 2, the head 1 consists of a lid 7 and body structure 6. The body 6 has two major cavities, the upper cavity 8 is the main pressure chamber and the lower one is a secondary pressure chamber 9 which reduces the pin-to-head contact area while maintaining precise alignment of each of the pins 2, 3, 4, and 5. The main pressure chamber 8 has two sealed inlets, one for high pressure air 10 and another for the electrical connections 11. Four incoming wires are soldered to gold ribbons (0.001 × 0.040) 12, 13, 14, 15. The ribbon is clamped in place by, for example, a Teflon block 16 or the like, then twists 90° passing by Teflon separating pins 17, 18, 19 and is soldered to the gold-plated end 20 of each pin.
Referring to FIG. 3, the head assembly 1 is attached to an aluminum bar 21 which is pivoted in the middle 22. The bar 21 is lowered by actuating a pneumatic cylinder 23. The extent of the bars travel is determined by an adjustable stop 24 which positions the head 1 within pin contact range of a wafer to be measured which is held in a pedestal 25. To prevent blowing the pins out of the head an interlocking system is provided consisting of two microswitches 26 and 27. These switches 26, 27 detect when the arm 21 is down and the pedestal 25 is in place and only when these two conditions exist will the head 1 be pressurized.
Referring to FIG. 4, pneumatic controls are shown in schematic form. A push-button switch 31 actuates a microswitch 32 which controls a three-way pneumatic valve 33. The pneumatic valve 33 applies pressure by means of a pneumatic pressure regulator 34 and a pressure gauge 35 to flow control means 36. Flow control means 36 applies pressure to two-way pneumatic valve 37 which communicates with the pneumatic cylinder 23 and a two-way pneumatic valve 43. The pneumatic cylinder 23 actuates the arm assembly 21. When arm assembly 21 is in a down position microswitch 26 is actuated and controls two-way pneumatic valve 43. Valve 43 receives pressure via a pressure gauge 42 and pressure regulator 41 from three-way pneumatic valve 33. Valve 43 communicates with the probe head 1 by means of a pressure-activated electric switch 44 controlling the two-way pneumatic valve 37 and pressure-actuated electric switch 45. Electric switch 45 and probe head assembly 1 are electrically connected to electrical logic means 47 which control the three-way pneumatic valve 33.
Referring to FIG. 5, there is shown an overall block diagram of a system for applying current and measuring voltage. Current source 50 applies current to pins 2 and 5 of probe head 1 which is in contact with a wafer to be tested. A voltage amplifier 60 has its input coupled to pins 3 and 4 of the probe head. The voltage amplifier 60 applies an amplified output to an analog-to-digital converter 70 whose output is fed back to voltage amplifier 60 by autorange circuits 80. Converter 70 also applies an output to a binary multiplier 90 which drives a binary-to-BCD converter 100 to provide a display 110. Thumbwheel switches 92 control a BCD-to-binary converter 94 driving the binary multiplier 90.
Referring to FIG. 6, there is shown a detailed schematic diagram of the current source 50. Current Io is supplied to a load Z1 from the collector of a transistor 117. Transistors 116 and 117 are selected to have high current gains so the vast portion of the collector current of transistor 117 flows through resistor 114.
Transistors 115 and 116 form a differential amplifier which drives transistors 117 and 118 in such a manner as to keep the voltages on the bases of transistors 115 and 116 equal. Therefore, the collector current of transistor 117 is approximately given as V112 /R114 where V112 is the voltage of a Zener diode 112 and R114 is the resistance of resistor 114. The biased Zener diode 112 is thereby used as a reference voltage source. 112 is chosen to be temperature stable, and transistors 115 and 116 are a matched transistor pair whose emitter-base voltages have equal changes with temperature. Thus, the constant current supplied at the collector of transistor 117 is not sensitive to temperature changes.
The current from the collector of transistor 117 is divided into IB, which is the input bias current of an operational amplifier 122, and IL, which is the current that flows through a load impedance ZL representing the load of a test wafer. Operational amplifier 122 is chosen so that its input bias current, IB, is very small as compared with the current from the collector of transistor 117. Thus, the load current, IL, is approximately equal to the constant current from the collector of transistor 117; IL = Io.
The function of amplifier 122 is to increase the output resistance of the constant current source 50. This can be seen from FIG. 7 where the current that flows from the collector of transistor 117 is shown as being produced by a constant current source T117 with finite output resistance Ro. Also in FIG. 7 the operational amplifier 122 is assumed to have an input resistance, Ri, and an open-loop voltage gain of G. The voltage between the inputs of the amplifier 122 is given by Vi, and the voltage across the load is VL. From the circuit shown in FIG. 7, ##EQU1## Vs being the voltage of an applied voltage source. The output resistance of the equivalent current source seen by the load is ##EQU2## Therefore, the output resistance is the parallel combination of Ri and Ro multiplied by the open-loop gain of the amplifier 122. This large value of resistance makes the circuit configuration unique and is the means by which the wafer current can be held constant over a wide voltage range.
To achieve the high gain necessary for measuring low resistivity wafers, the voltage amplifier 60 consists of three stages, each having moderate gains. The first stage is configured to achieve high input impedance by using its positive terminal as the input. The final output of the amplifier 60 is detected by an integrator and used to eliminate offset errors. Referring to FIG. 8, there is shown a circuit representing amplifier 60 in the stand-by mode. Switch 200 applies 0 volts to an input of amplifier 60 while switch 203 connects an output of amplifier 60 to an integrator 204 formed by operational amplifier 205, resistor 206 and capacitor 207. If any offset voltage is present in the amplifier 60, Vout will not be zero, and the integrator 204 will produce a voltage of growing magnitude which is introduced through resistor 209 back into the amplifier 60 in a proper polarity to drive Vout towards zero. When Vout reaches zero, the integrator 204 becomes stabilized, and capacitor 207 stores the voltage required to maintain Vout at zero. Since the integrator's output voltage is added into the amplifier independently of Vin, the amplifier will maintain a zero offset condition during the actual measurement if the integrator's voltages do not change. This is accomplished by switching 200 to connect Vin to the amplifier.
This self-zeroing feature can be used to correct for the voltage errors produced by the point-contact diodes at the two inner probes by keeping the integrator 204 connected to Vout while the wafer is connected to the amplifier with no current flowing into the outer probes. In this condition, switch 200 is switched to connect Vin to the amplifier 60 while switch 203 is in the position shown in FIG. 8. The input bias current for amplifier 202 will thus flow through the point-contact diode, and Vin will be slightly different from zero due to the diode voltage drop. However, the integrator 204 will add in the proper voltage to force Vout to zero. Since the bias current will remain essentially constant regardless of the magnitude of Vin, the diodes voltages will be eliminated from the data, thus allowing accurate measurements to be taken. The proper operation sequence is: With the constant current source 50 disabled, switch 200 connecting Vin to the amplifier 60, and switch 203 connecting the integrator 204 to Vout, establish probe 1 contact with the wafer; allow a settling time for the integrator 204 to zero the amplifier 60 and switch 203 to ground the integrator's input and apply current to the wafer.
Clark, George Reed, Winkleblack, Kenneth Charles
| Patent | Priority | Assignee | Title |
| 5698989, | Oct 06 1994 | Applied Materilas, Inc. | Film sheet resistance measurement |
| Patent | Priority | Assignee | Title |
| 2954521, | |||
| 3048776, | |||
| 3312893, | |||
| 3801919, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Oct 09 1974 | Hewlett-Packard Company | (assignment on the face of the patent) | / |
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