Frequency divider for high frequencies

Abstract

A frequency divider for high frequencies including a first and a second bistable circuit, each of which include two cross-coupled transistors, in which the common emitter circuits of the transistors of the two bistable circuits are each connected through a current source to a point of constant potential. The collectors of the transistors of the first circuit are each connected to a respective collector of each of the transistors of the second bistable circuit, and a coupling resistor is included between the collector and the base of each of the auxiliary transistors.

Description

The invention relates to a frequency divider for high frequencies, which comprises a first and a second bistable circuit, which each include two crosscoupled transistors, while the common emitter circuit of the transistors of the first bistable circuit is connected via a first current source to a point of constant potential, the common emitter circuit of the transistors of the second bistable circuit is connected via a second current source to a point of constant potential, the first and the second current source are driven by clock signals of opposite phase, the collectors of the transistors of the first bistable circuit are connected via the collector-base path of an auxiliary transistor to a collector of the transistors of the second bistable circuit, and the emitters of the auxiliary transistors are connected to a point of constant potential via a current-determining element.

Dividers of the above mentioned type are frequently employed in professional measuring equipment. Known dividers of said type often have the drawback that owing to the low efficiency of the very high frequency transistors the price of the dividers is high. Furthermore, the conventional dividers tend to become smaller and smaller, use being made of integrated elements. The object of said reduction in size is to reduce the costs and to increase the operating speed.

It is an object of the invention to provide a frequency divider, which can readily be integrated and which is moreover cheaper than the known dividers. The invention is characterized in that between the collector and the base of each of the auxiliary transistors a coupling resistor is included.

The invention will be described with reference to the drawing.

The frequency divider for high frequency in accordance with the drawing includes a first bistable circuit I and a second bistable circuit II. The circuit I comprises two cross-coupled transistors T₁ and T₂. The circuit II comprises two cross-coupled transistors T₃ and T₄. The common-emitter circuit of the transistors T₁ and T₂ of the first circuit I is connected via a first current source, constituted by the transistor T₇ and the resistor R₅, to a point -E of constant potential. The common emitter circuit of the transistors T₃ and T₄ of the second circuit II is connected via a second current source, constituted by the transistor T₈ and the resistor R₅, to a point -E of constant potential. The collector of the transistor T₁ is connected via the collector base path of the auxiliary transistor T₅ to the collector of the transistor T₄. The collector of the transistor T₂ is connected via the collector-base path of the auxiliary transistor T₆ to the collector of the transistor T₃. The collectors of the transistors T₃ and T₄ are connected via the respective resistors R₃ and R₄ to a point of constant potential. The collectors of the transistors T₁ and T₂ are connected via the respective resistors R₁ and R₂ to a point of constant potential. The emitters of the transistors T₅ and T₆ are connected via the resistor R₆ to a point -E of constant potential. Between the collector and the base of the transistor T₅ the resistor R₇ is included and between the base and collector of the transistor T₆ the resistor R₈ is included. The signal to be divided is applied to the inputs A and A, the signals applied to said two inputs being inverted relative to each other.

The operation of the frequency divider according to the invention is as follows. The divider in fact consists of two current-controlled bistable circuits I and II and two differential amplifiers constituted by the respective transistors (T₅, T₆) and (T₇, T₈). The differential amplifier constituted by the transistors T₅ and T₆ is employed for driving the collector of the first bistable circuit I. The differential amplifier constituted by the transistors T₇ and T₈ is used for driving the emitter of the second bistable circuit II. If the input voltage at the input A is high, the current I₁ flows through the transistor T₇ of the lower differential amplifier and energizes the bistable circuit I. The bistable circuit I consequently assumes the master state M₁. Via the coupling resistors R₇ and R₈ the bistable circuit II is set to the slave state S₁. The differential amplifier constituted by the transistors T₅ and T₆ is driven by the bistable circuit II so as to counteract the master state M₁ of the bistable circuit I (negative feedback). This is effected by the current I₂ which partly compensates for the effect of the current I₁ by a reduction of the difference voltage from the bistable circuit I.

When the input voltage at the input A is changed from high to low, the bistable circuit II gradually changes over from the state S₁ to the state M₁, while the bistable circuit I changes over from the state M₁ to the state S_O. The next transition of the input voltage from low to high gradually changes the state S_O of the bistable circuit I to the state M_O and, simultaneously by means of the coupling resistors R₇ and R₈, the state M₁ of the bistable circuit II changes to the state S_O. This means that upon each transition from high to low of the input signal at A the bistable circuit I changes over and upon each transition from low to high of said input voltage the frequency divider has reached its original state. Consequently, the frequency divider divides by two.

For obtaining very high frequencies it is necessary to partly compensate for the delay caused by the base resistor of the transistors of the differential amplifier which is constituted by the transistors T₅ and T₆. This is effected by shifting the phase of the input voltage of the differential amplifier relative to the phases of the two bistable circuits I and II by tapping the coupling resistors R₇ and R₈, as is indicated by the dotted lines in the Figure. Said frequency divider is then capable of handling frequencies of 1250 MHz.

Claims

1. A frequency divider comprising a first and a second bistable circuit, each comprising two-cross-coupled transistors,

first and second gating transistors connecting said cross-coupled transistors of said first and second bistable circuits respectively to a point of constant potential;

the base of said first gating transistor being connected to a first signal input, and the base of said second gating transistor being connected to a second signal input inverted relative to said first signal input;

said first bistable circuit including a pair of auxiliary transistors, connecting the collector of each of said transistors of said first bistable circuit by means of collector-base path to a respective collector of one of said transistors of said second bistable circuit, the emitters of said auxiliary transistors being connected to a point of constant potential; and

a coupling resistor having a tap, connected between the collector and base of each of the auxiliary transistors, said tap being connected to the base of said auxiliary transistor.