cmos oscillator in which the oscillator circuit comprises a first mos transistor connected by its source to a first terminal of a voltage supply and biased by the current provided by a second mos transistor of opposed type which is a part of the same integrated circuit. At least a third mos transistor (T6, T8, T12) of the same type as the second and which is a part of the same integrated circuit is provided, the sources and gates of the second and third transistors being respectively connected together and respectively to the second terminal of the voltage supply and to a point (P) at a potential such that the mean drain current of the first transistor will be maintained at a value just higher than the value at which oscillation starts.
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1. A cmos oscillator in which the oscillator circuit comprises a first and a second mos transistor of opposed type integrated on the same substrate, the source-drain path of the first transistor being connected in series with the drain-source path of the second transistor between the terminals of a voltage supply and the drain and gate of the first transistor being coupled to each other through a frequency determining network, and at least a third mos transistor (T6, T8, T12) of the same channel type as the second transistor, integrated on the same substrate, the sources of the said second and third transistors being connected together to one terminal of the voltage supply and the gates thereof being connected together to a point (P) at a potential such that the mean drain current of the first transistor is maintained at a value just higher than the value at which oscillation starts.
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The present invention relates to oscillators employing CMOS technology, in which the oscillator circuit comprises a first MOS transistor which is biased by the current provided by a second MOS transistor of opposite type which is part of the same integrated circuit.
It is known how to design oscillators of low power consumption, for example quartz oscillators, in CMOS technology, that is, in the form of integrated circuits with complementary MOS transistors (Electronics Letters, Vol. 9, No. 19, Sept. 20, 1973, pp. 451-453). This known arrangement uses as bias current source of the first transistor of the oscillator circuit a complementary transistor whose gate is connected to the same terminal of the supply as the source of the first transistor and whose source is connected to the other terminal of the supply. In this case, the mean drain current of the first transistor is quite dependent on the threshold voltage of the second transistor as well as on the supply voltage.
Also, if a CMOS inverter is used the input and output of which are connected through the quartz resonator, there results an oscillation of large amplitude and a current consumption very much higher than the minimum necessary to sustain oscillation in a "Pierce" circuit.
It has also been proposed, in published Swiss application No. 15126/68, to control automatically the current consumed by the oscillator by directly detecting the amplitude of the oscillation signal. This known solution also involves a large oscillation amplitude. On the other hand, the corresponding circuit, which is designed for transistors of a single type, presents a number of drawbacks: the output conductance of the transistor of the oscillator circuit is high because of the phenomenon of modulation by the substrate, which increases the needed current; the circuit comprises a capacitative connection which gives rise to certain difficulties in integration; the ground of the circuit is connected to one of the quartz terminals, which results in the parasitic capacitances between the other terminal and ground adding to the undesired capacitance which appears in parallel across the quartz instead of adding to the functional capacitances between drain and source and between gate and source of the transistor of the oscillator circuit; this can make the oscillator very critical when the quality factor of the quartz is low.
Accordingly, it is an object of the present invention to provide an integrated oscillator, and particularly a quartz oscillator having minimum current consumption and operating in a stable and precise manner.
To this end, the oscillator according to the present invention in which the oscillator circuit comprises a first MOS transistor connected by its source to a first terminal of a voltage supply and biased by the current provided by a second MOS transistor of opposed type which is a part of the same integrated circuit, comprises at least a third MOS transistor of the same channel type as the second and which is part of the same integrated circuit, the source and gate electrodes of the second and third transistors being connected together and respectively to the second terminal of the voltage supply and to a point having a potential such that the mean drain current of the first transistor will be maintained at a value only just higher than the value at which oscillation starts.
An embodiment of the oscillator according to the present invention provides for the amplification of the oscillation signal in a manner which is both simple and completely compatible with integrated CMOS circuit technology. This embodiment is characterized in that the oscillator comprises a pair of MOS transistors of opposite channel types which are part of the same integrated circuit and which are so dimensioned that the width-length ratio of the channel of each relative to the corresponding dimensions of the channel of the transistor of the same type among the first and second transistors, will be equal, the gate and source electrodes of the transistors of the said pair being connected respectively to those of the first and second transistors and the common connection point of the drains of the said pair of transistors constituting the output of the oscillator.
Other embodiments of the oscillator according to the invention provide very high precision and stability in the maintenance of the mean drain current of the first transistor. To this end, the mean drain current may be imposed on the first transistor by means of a control loop.
Other objects, features and advantages of the present invention will become apparent from a consideration of the following description, taken in connection with the accompanying drawings, in which:
FIG. 1 is a diagram of a "Pierce" circuit such as may be used in the oscillator of the present invention;
FIG. 2 is a graph showing the variation of the oscillation amplitude in the circuit of FIG. 1 as a function of the supply current;
FIG. 3 is a circuit diagram of a first embodiment of an oscillator with signal amplification;
FIG. 4 is a schematic view of two MOS transistors of opposite types which are part of the same integrated circuit;
FIG. 5 is a circuit diagram of a modification of the oscillator shown in FIG. 3;
FIG. 6 is a circuit diagram of an embodiment of oscillator comprising a control loop and making use of a control transistor;
FIG. 7 is a circuit diagram of a modification of the oscillator of FIG. 6;
FIG. 8 is a circuit diagram of another embodiment of the oscillator according to the invention;
FIG. 9 is a graph showing the variation of the amplitude of oscillation of the oscillator of FIG. 8 as a function of the dimensions of the transistors which are utilized; and
FIG. 10 is a circuit diagram of an embodiment utilizing a phase-shift oscillator circuit.
Referring now to the drawings in greater detail, and first to FIG. 1 thereof, there is shown a known quartz oscillator circuit, known as a "Pierce" circuit, embodying a single MOS transistor T1. Transistor T1 is biased to active state by a resistance R0 connected between drain and gate, so that the mean potential of the gate is equal to that of the drain, the transistor being fed by a current source I which establishes the mean drain current. A quartz resonator Q is connected between drain and gate of the transistor. The diagram also shows two capacitances C1 and C2 disposed respectively between gate and source and between drain and source of transistor T1. These two capacitances, which are necessary to the operation of the oscillator, may be components connected between the illustrated points, or alternatively may be constituted solely by the parasitic capacitances of T1.
The principal advantage of this circuit with a single transistor is the very small influence of the non-linear effects on the oscillation frequency. This advantage is especially desirable at relatively high frequencies for which other circuits can no longer be used because their oscillation frequency becomes too dependent on certain parameters such as temperature and supply voltage.
FIG. 2 shows the variation of oscillation amplitude of the circuit of FIG. 1, represented for example by the amplitude U1 of the voltage across C1, as a function of the biasing current I. The relationship represented quantitatively in this graph shows that no oscillation exists when the biasing current I is lower than the critical value Icrit. When I exceeds Icrit, oscillation rises sharply to an amplitude of the order of about 100 mV. Beyond that amplitude, the nonlinearity of the gate voltage versus drain current characteristic of the transistor begins to have an effect and the amplitude of the oscillation can be increased only at the price of increased current I.
FIG. 3 shows a circuit diagram of a first embodiment of the present oscillator, utilizing means to adjust the current I to a value only slightly greater than Icrit and comprising on the other hand an amplifier circuit so as to impart to the oscillation signal an amplitude permitting control of logic circuits that can be connected to the oscillator.
The oscillator of FIG. 3 comprises the oscillator circuit of FIG. 1, the source of bias current comprising a complementary MOS transistor T2 whose source is connected to a terminal of the voltage supply the other terminal of which is connected to the source of transistor T1. The gate of transistor T2 is connected to the gate of a third transistor T6 of the same channel type as transistor T2, the source of this transistor T6 being connected to the same supply terminal as the transistor T2 and its drain being connected on the one hand to the gates of T2 and T6 (P), and on the other hand, by means of a resistance R1, to the other terminal of the voltage supply.
The diagram of FIG. 3, further comprises a pair of complementary MOS transistors T3 and T4 of the same types, respectively, as the transistors T1 and T2, the gates and sources of these transistors T2 and T4 on the one hand and of the transistors T1 and T3 on the other hand, being directly connected to each other. The common point of connection of the drains of the transistors T3 and T4 constitutes the output of the oscillator.
The dimensioning of the elements of the present oscillator and the operation of the circuit of FIG. 3 are explained on the basis of the definitions given in connection with the schematic showing of FIG. 4.
FIG. 4 is a schematic view of two MOS transistors of opposed type which are embodied in the same integrated circuit (CMOS technology). The different transistors of the same channel type, that is p-channel type of n-channel type, which are part of the same integrated circuit differ only by the width W and the length L of their respective channels shown in FIG. 4.
The drain current iD of the MOS transistor follows a law corresponding to the expression
iD = (W/L) F (vG, vD)
in which vG and vD are respectively the gate-to-source and drain-to-source voltages of the transistor. The function F depends on the mode of operation of the transistor. It can vary considerably from one manufactured lot of transistors to another, but experience shows that it is substantially the same for all the transistors of the same channel type which are part of the same integrated circuit. Moreover, this function becomes independent of vD, as a first approximation, if the transistor operates in the saturation region which is reached when
vD > vG - VT
in which VT is the threshold voltage of the transistor.
Under these circumstances, the drain currents of several transistors T1 of the same channel type and being part of the same integrated circuit are proportional to their respective dimensional ratios ai = Wi /Li. It is on this principle that the concept of the present oscillator is based.
In the diagram of FIG. 3, the n-channel transistors T1 and T3 differ from each other only as to their dimensional ratios a1 and a3, and the p-channel transistors T2, T3 and T6 differ from each other only as to their corresponding ratios a2, a4 and a6. Thus, according to the above-mentioned principle, the bias current I of T1, which is equal to the drain current of transistor T2, is given by the expression
I = I6 . a2 /a6
The drain current of T6, denominated I6, is given by the expression
I6 = (U-VG6 /R1)
in which VG6 is the gate voltage of T6. This gate voltage being close to the threshold voltage of the p-channel transistors which is much lower than the supply voltage U, the current I6 is substantially a function of U and of R1. In other words, the potential of point P applied to the gate of transistor T2 can be determined by these two parameters such that the current I will have a value only just greater than the value Icrit indicated in FIG. 2.
On the other hand, in the diagram of FIG. 3, the transistors T1, T2, T3 and T4 are so dimensioned that
a3 /a1 = a4 /a2
Transistor T1 being biased in the active state by the presence of resistance Ro, transistor T3 is similarly biased in the active state with a quiescent current
I4 = I . a4 /a2
The transistor pair T3, T4 constitutes an amplification stage. The oscillation signal from the gate of T1 is applied directly to the gate of the amplifier transistor T3 which provides at its drain an output signal of great amplitude.
FIG. 5 is a diagram of an embodiment showing different variations, independent from each other, which may be made in the arrangement of FIG. 3. Thus, in FIG. 5, the resistance R1 is replaced by a transistor T5 whose gate-to-source voltage is equal to the supply voltage U. On the other hand, the biasing resistance Ro is replaced by two diodes D1 and D2 connected in series and in opposition. These diodes may be provided for example by lateral junctions in polycrystalline silicon used as the gate electrodes. These two modifications completely eliminate the resistors whose manufacture can give rise to problems in CMOS technology.
Furthermore, in FIG. 5, the gate of transistor T3 is no longer connected to the gate but rather to the drain of T1, whose mean potential is identical to that of the gate of T1.
FIG. 6 shows another preferred embodiment of the present oscillator. The basic oscillator circuit comprising T1 and the mounting of the transistors T2, T3 and T4 as well as the dimensioning of the same are similar to those of FIG. 3.
A third pair of complementary transistors T7 and T8 is connected in the same fashion as the pair T3 and T4, the common connection point of the drains of T7 and T8, constituting the output of this stage, being connected to the gate of a p-channel control transistor T10. The source of transistor T10 is connected to the positive terminal of the power supply and its drain circuit comprises a load resistance R2 shunted by a capacitor C3. The drain of transistor T10 which is the output of this stage constitutes the point P connected directly to the gates of T2, T4 and T8.
The transistor pair T7 and T8 is dimensioned such that
a8 /a2 > a7 /a1
It follows that, in the absence of oscillation, the drain currents of T1 and T2 being equal, the saturation current of T8 is greater than that of T7. The common potential of the drains of T7 and T8 is thus close to the positive supply potential +U, such that the quiescent operating point of T8 departs from the saturation region, which reduces the drain current thereof. Transistor T10 is accordingly turned off and resistance R2 brings the gate potential of transistors T2, T4 and T8 to that of the negative supply terminal. The currents I, I4 and I8 then take a higher value and the oscillation starts.
When the oscillation amplitude has attained a sufficient value, the positive voltage peaks at the gate of T7 lead to an increase of the drain current of T7 until the same overcomes that of T8, despite the initial dissymmetry. Negative pulses appear then on the gate of T10. The mean drain current of this transistor is thus no longer zero and gives rise to a d.c. voltage across R2. The potential at point P rises and currents I, I4 and I8 decrease to the level just adequate to permit a periodic conduction of control transistor T10. The operating current I is thus stabilized by the feed back loop including the transistor T10.
FIG. 7 shows a number of variations which can be embodied in the circuit of FIG. 6 and which are independent of each other. A diode D3 is connected in blocking direction between source and gate of T10. The leakage current of D3 is greater than that of the p-n junction drain/substrate of transistor T7, so that the potential of the gate of T10 will be about +U, even if no current flows through the channel of the transistor. This diode can be formed for example by a lateral p-n junction of polycrystalline silicon. It may also be replaced by a high ohmic resistance.
The output signal of the oscillator is taken directly from the drain of T1 and is applied in parallel to the gate of transistor T7, the mean potential of the gate and of the drain of T1 being of the same magnitude. Resistance R2 in FIG. 6 is replaced by a transistor T9 with long n-channel, whose gate is connected to +U.
The capacitance C4 shown in phantom lines is a parasitic capacitance for the described mode of operation, because it limits the gain of amplifier T7, T8. However, the control means operates even if this capacitance is very great, the mode of operation being then as follows: when the oscillation amplitude at the gate of T1 exceeds several hundred mV, the operating point of T1 leaves the saturation region during the positive half-waves of the gate voltage, which tends to lower the mean value of the drain current of T1. As this value should remain equal to the constant current I supplied by T2, this lowering is compensated by an increase of mean potential at the gate and at the drain of T1, this potential being also that of the gate of T7. The mean drain current of T7 increases therefore and ultimately surpasses that of T8, reducing the mean potential of the gate of T10. Transistor T10 thus becomes conductive causing a reduction in currents I and I8 supplied by T2 and T8 to a level just sufficient to maintain T10 conductive.
FIG. 8 shows another embodiment of the present oscillator, by which the amplitude of oscillation can be limited to a very low value without amplifying the signal. The oscillator circuit comprising transistor T1 is identical to the preceding examples, as well as the operation of transistor T2. A pair of complementary transistors T11 and T12 having a common node at their drains is connected by the sources to the corresponding terminals of the voltage supply. The gate of the p-channel transistor T12 is connected to the drain thereof and to the gate of transistor T2 (point P). The gate of the n-channel of transistor T11 is connected to the gate of transistor T1 by means of resistance R3, a capacitance C5 being connected in parallel between gate and source of the transistor T11. The resistance R3 and capacitance C5 constitute a low pass filter.
The four transistors of the circuit of FIG. 8 are so dimensioned that
a12 /a2 < a11 /a1
In the absence of oscillation and if the four transistors were operating in the saturation region, the current I resulting from a given current iD1 would be equal to kiD1 with
k = a2 /a12 . a11 /a1 > 1
There is accordingly no quiescent operating point corresponding to these conditions. The currents increase until at least one of the transistors T2 and T11 leaves the saturation region such that iD1 = I.
Current I is then largely sufficient to start oscillation. When the amplitude of oscillation U1 at the gate of T1 increases, the mean gate voltage V1 decreases due to the nonlinear characteristic iD1 = f (vG1) to maintain the average of iD1 = I. The gate voltage vG11 of T11 is equal to V1, as the a.c. component does not appear at the output of filter R3, C5, and therefore the current I11 decreases, causing a decrease of the current I. The circuit stabilizes at a value I which is necessary to sustain an oscillation of an amplitude U1 sufficient to compensate the factor k greater than 1, and the four transistors operate about a quiescent operating point located in the saturation region.
The values of a1 and a11 are preferably sufficiently large that the transistors T1 and T11 operate at a low current density. In this case, it will be seen that the stabilized amplitude
U1 /Vc
depends only on the ratio k according to the relationship shown in FIG. 9. Vc is a generally well controlled constant for a given technology. This embodiment of the oscillator therefore permits stabilizing the consumed current by the choice of the dimensional ratios of the four transistors that are used.
A diode D4 may be connected between source and drain of transistor T4 to overcome the drain-to-substrate leakage current of the transistor T1 and to permit the quiescent operating point to establish itself accurately when the supply voltage is switched on. This diode may be of the same type as diode D3 in FIG. 7.
On the other hand, resistances R0 and R3 might be replaced by pairs of diodes connected in series in opposed direction.
The oscillator circuit of the "Pierce" type used in the embodiments described above might be replaced for example by a phase-shift oscillator circuit.
FIG. 10 shows an embodiment which utilizes a resistance-capacitance oscillator circuit and in which the control circuit and the amplifier circuit operate like those of FIG. 6. The number of meshes of the RC network may be greater than shown in FIG. 10 and a distributed network or other form of network can be used without departing from the principle of the present oscillator.
In all the different embodiments of the invention, it is possible to reduce the current consumption of the oscillator to a minimum level, which also limits the amplitude of the oscillation signal at the gate of the first transistor and thus avoids the non-linear effects which would have a great influence on the oscillation frequency.
From a consideration of the foregoing disclosure therefore, it will be evident that the initially recited objects of the present invention have been achieved.
Although the present invention has been described and illustrated in connection with preferred embodiments, it is to be understood that modifications and variations may be resorted to without departing from the spirit of the invention, as those skilled in this art will readily understand. Such modifications and variations are considered to be within the purview and scope of the present invention as defined by the appended claims.
| Patent | Priority | Assignee | Title |
| 4096496, | May 26 1976 | Fuji Photo Optical Co., Ltd. | Exposure control circuit for camera |
| 4122414, | Oct 11 1977 | Harris Corporation | CMOS negative resistance oscillator |
| 4128816, | Jul 16 1976 | Kabushiki Kaisha Daini Seikosha | Electronic circuit |
| 4208639, | Jun 16 1978 | ALLEGRO MICROSYSTEMS, INC , A CORP OF DE | Constant current source stabilized semiconductor oscillator |
| 4994866, | Jan 07 1988 | Fujitsu Limited | Complementary semiconductor device |
| 5184094, | Aug 16 1991 | MYCROSENSOR TECHNOLOGIES, LLC | Low power oscillator circuits |
| 5568093, | May 18 1995 | National Semiconductor Corporation | Efficient, high frequency, class A-B amplifier for translating low voltage clock signal levels to CMOS logic levels |
| 7123113, | Jun 11 2004 | MONTEREY RESEARCH, LLC | Regulated, symmetrical crystal oscillator circuit and method |
| 7859355, | Mar 24 2005 | MONTEREY RESEARCH, LLC | Regulated capacitive loading and gain control of a crystal oscillator during startup and steady state operation |
| 7902933, | Mar 29 2006 | MONTEREY RESEARCH, LLC | Oscillator circuit |
| 8035455, | Dec 21 2005 | MONTEREY RESEARCH, LLC | Oscillator amplitude control network |
| Patent | Priority | Assignee | Title |
| 3887881, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
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