A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si3 N4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si3 N4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO2 there below, while leaving the SiO2 above the trenches covered with polysilicon. The exposed SiO2 is then RIE etched down to the Si3 N4, leaving a plug of SiO2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si3 N4, to provide a planarized upper surface of SiO2 and Si3 N4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.
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12. A process for forming a filled wide trench in the surface of a substrate comprising the steps of:
forming a wide trench in the surface of the substrate; conformally forming a layer of filling material on the surface of the substrate including in said trench the top surface of which filling material extends above the plane of the surface of the substrate; conformally forming a layer of etch-resistant material on said layer of filling material which etch resistant material will mask said filling material from reactive ion etching; selectively removing only those portions of said etch resistant material that extend above the surface of the filling material by physical polishing and not removing any etch resistant material disposed below the surface of said filling material, such that the only remaining portion of the etch resistant material resides within the width of said trench; forming a plug above said trench comprising the remaining etch resistant material overlying filling material by anisotropically etching said layer of filling material which is not masked by said etch resistant material down to the top of said trench; and removing said plug to obtain a filled trench having an upper surface in substantial planarity with the upper surface of said substrate.
1. A process for forming a wide dielectric-filled isolation trench in the surface of a semi-conductor substrate comprising the steps of:
forming a wide trench in the surface of the substrate; conformally forming a layer of dielectric material over the surface of the substrate including in said trench the top surface of which layer of dielectric material extends above the plane of the surface of the substrate; conformally forming a layer of etch resistant material on said layer of dielectric material which etch resistant material will mask said dielectric material from reactive ion etching; selectively removing only those portions of said etch resistant material that extend above the surface of the dielectric material by physical polishing and not removing any etch resistant material disposed below the surface of said dielectric material, such that the only remaining portion of the etch resistant material resides within the width of said trench; forming a dielectric plug above said trench comprising the remaining etch resistant material overlying dielectric material by anisotropically reactive ion etching said layer of dielectric material which is not masked by said etch resistant material down to the top of said trench; and removing said dielectric plug to obtain a dielectric-filled trench having an upper surface in substantial planarity with the upper surface of said substrate.
2. The invention as defined in
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This is a continuation of copending application Ser. No. 07/427,153 filed on Oct. 25, 1989, now abandoned.
This invention relates generally to the manufacture of semi-conductor devices. More particularly, the invention relates to a method of forming planarized wide filled trenches in the surface of a semi-conductor substrate, especially a silicon wafer, particularly filled with dielectric material, although the invention also can be used to form trenches filled with conductive material.
In the art of large-scale integrated chips, a large number of surface conductors are required for distribution of operating voltages and currents and digital signals between devices. Although surface conductors are insulated from the semi-conductor substrate upon which they are formed, a certain amount of capacitive coupling is present between the insulated conductor and the substrate through the insulating material. This capacitive coupling degrades the signal carried by the surface conductors.
While this capacitive coupling can be minimized by increasing the thickness of the dielectric material separating the conductors and the substrate, it is more desirable to recess the dielectric material below the surface of the substrate and maintain the planarity of the substrate rather than add the dielectric material onto the surface of the substrate. This is accomplished by forming shallow trenches in the surface of the substrate, and filling the trenches with dielectric material, normally silicon dioxide. These trenches may be either narrow trenches (i.e., less than about one micron in width, and more typically about 0.5 microns) and wide trenches (i.e., those wider than about one micron).
It is relatively simple to maintain planarity when forming dielectric filled narrow trenches. However, problems of maintaining planarity with the semi-conductor substrate and the dielectric material are presented with wide trenches because of the conformal nature of the deposition of the dielectric and especially silicon dioxide in the wide trenches.
There have been several prior art proposals for solving these problems of forming planarized dielectric filled wide trenches. One such proposal, described in U.S. Pat. No. 4,385,975 assigned to the assignee of this invention, utilizes a step in the process of depositing a photoresist material through a mask over the dielectric material contained in the trenches before planarization. The dielectric material is then reactive ion etched (RIE) with the photoresist masking the underlying material from etching, thus resulting in a relatively planer structure. U.S. Pat. No. 4,671,970 also utilizes a photoresist as a mask for reactive ion etching of dielectric material. These teachings of masking, while somewhat effective, nevertheless have certain drawbacks. They require extra masking and photolithographic steps, which adds two processing steps, and more importantly create significant problems of alignment; i.e., the mask must be perfectly aligned to deposit the photoresist exactly within the conformal or trough portion of the deposited dielectric material to be utilized to mask just that dielectric material desired and to expose the rest.
U.S. Pat. No. 4,278,987 shows a somewhat different technique for filling trenches, not with dielectric material, but with a semi-conductor material having a different characteristic than the base substrate material. This also uses a masking process.
U.S. application Ser. No. 189,863, filed May 3, 1988, owned by the assignee of this invention, discloses another technique for planarizing wide dielectric filled isolation trenches.
One of the principal objects of this invention is to provide an improved method of forming dielectric filled wide trenches in a semi-conductor substrate which is self-aligning and has resultant good planarization.
A method or process for forming a wide, shallow filled trench on the surface of a semi-conductor substrate is provided, and in particular a dielectric filled trench. The process includes forming a wide, shallow trench in the surface of the semi-conductor substrate followed by conformally depositing a layer of dielectric material on the surface of the substrates including in the trench. A layer of etch-resistant material is deposited on the layer of the dielectric material. Portions of the etch resistant material outside the width of the trench are selectively removed, preferably by chemical-mechanical polishing, such that the remaining portions of the etch resistant material reside within the width of the trench. Following this, a dielectric plug is formed above the trench by etching the layer of dielectric material which is not covered by the etch resistant material down to the top of the trench. Finally, the dielectric plug is removed, preferably by polishing, to obtain a dielectric filled trench, having an upper surface in substantial planarity with the upper surface of the substrate. This invention also can be used to fill and planarize trenches with conductive material.
FIGS. 1 through 6 are cross-sectional views, somewhat diagrammatic, showing successive stages of processing of a semi-conductor having wide and narrow shallow trenches formed, filled with dielectric material and planarized according to this invention.
Referring now to the drawings, and for the present, FIG. 1, there is shown a silicon semi-conductor substrate 10 having an etch stop coating of silicon nitride (Si3 N4) 12 deposited thereon. The silicon nitride is typically about 1000 Å thick and can be deposited by conventional means such as by chemical vapor deposition (CVD) from SiH2 Cl2 +NH3 at 400 mTorr, at 770°C The silicon nitride is then patterned by conventional photoresist techniques to reveal underlying openings where both wide and narrow trenches are to be formed. Two such trenches 14 and 16 are shown in FIG. 2 formed in substrate 10 although it is to be understood that normally many such trenches are formed. The trench 14 is a wide trench, typically wider than about one micron, and the trench 16 is a narrow trench, less than one micron wide and typically about 0.5 microns wide. These can be formed by conventional RIE etching in a well-known manner, such as, for example, in a plasma of NF3 +Ar at 10 mTorr and 0.1- 0.2 W/cm2, utilizing the photoresist as a mask material which is a well-known practice in the art. Other processes, also which are well-known, may be used to form the trenches 14 and 16.
As indicated above, the present invention is especially useful for forming dielectric filled wide trenches; however, FIGS. 1 through 6 illustrate how the present invention can be used on substrates which contain narrow trenches as well as wide trenches.
As shown in FIG. 3, a layer of silicon dioxide (SiO2) 18 is formed over the surface of the substrate, including both the wide and narrow trenches 14 and 16. Preferably the SiO2 layer is deposited using well-known CVD processes which typically includes vapor deposition in tetraethylorthosilane (TEOS) at 650 mTorr at 715°C Of course, other processes could be used. The thickness of the CVD SiO2 layer is approximately equal to the total depth of the trench so that the top of the SiO2 layer in the trench 14 is approximately even with the top layer of the silicon substrate. This is typically about 6000 Å in thickness, although this can vary greatly with different substrates, depending upon the utilization of the substrates for forming devices and the type of conductors which are to be formed on the substrate.
On top of the silicon dioxide layer 18 is formed a thin layer of polysilicon 20 which typically is about 1000 Å thick. This polysilicon can be deposited in any conventional manner, a preferred method being CVD in SiH4 +H2 at 400 mTorr at 620°C This resultant structure is shown in FIG. 3. This structure is then subjected to a chemical-mechanical polish to remove just that portion of the polysilicon 20 which is located outside the confines of the trench 14. In the preferred polishing technique the substrate is mounted onto a flat circular holder which maintains the exposed surface of the polysilicon 20 is contact with a rotating polyurethane pad. The pad is wetted with a slurry of an abrasive material in a basic aqueous solution, such as SiO2, plus aluminum oxide (Al2 O3) and tetramethylammonium hydroxide (TMAH). As the polyurethane pad rotates against the surface of the exposed polysilicon, the chemicals react with the very outer-most surface of the polysilicon 20 to loosen it from the polysilicon which underlies it. The mechanical or abrasive action of the SiO2 then removes this loosened surface wherever it contacts it. Such chemical-mechanical polishing is well-known in the art. This is a continuous process in that a continuous reaction occurs at the outer surface with the chemicals for loosening this layer and those loosened portions of the polysilicon are removed by the abrasive action of the SiO2.
The chemical-mechanical polishing continues until all of the polysilicon that lies outside of the boundaries of the trench 14 has been removed as shown in FIG. 4. Coincidentally it can be seen that actually all of the polysilicon has been removed from the surface of the dielectric 18, filling the narrow trench 16. This, however, is not a problem because of the narrowness of the trench 16, and there is very little conformality which is indicated by the small indentation shown thereabove and is not significant.
The material shown in FIG. 4 is then anisotropically etched by reactive ion etching (RIE). Typically this can be done in a CHF3 +CO2 atmosphere at 0.1-0.2 W/CM2 and 40 mTorr. This RIE is reactive with the SiO2 material 18 but is not reactive with the polysilicon material 20. Thus, the SiO2 material not masked by the polysilicon material 20 is removed with the silicon nitride layer 12 acting as an etch stop in a well-known manner. This will result in the structure shown in FIG. 5 in which the underlying silicon nitride 12 has been revealed on both sides of the wide trench 14 and on both sides of the narrow trench 16. Also, it should be noted that with respect to the narrow trench 16, since there was no polysilicon material overlying the silicon dioxide in the trench 16, that the etch was also reacting with the SiO2 overlying the trench 16 to provide a planarized surface of the dielectric material 18 with respect to the silicon nitride 12. However, with respect to the material overlying the wide trench 14, a plug of material is left which comprises the SiO2 material underlying the polysilicon 20. This plug of material extends significantly above the planarized level of the silicon nitride 12, thus providing essentially a planarized surface over all of the substrate, except over any trenches where there are these plugs of material.
The entire wafer shown in FIG. 5 is then again chemically-mechanically polished using a silica slurry in basic aqueous solution and polished against a rotating polyurethane disk. This polishing step will remove the plugs of material which are above the wide trenches 14 resulting in a final structure shown in FIG. 6. The silicon nitride 12 acts as the end point for the polishing so that the entire surface of the wafer which includes both wide and narrow trenches filled with silicon dioxide are essentially planarized and hence ready for further processing such as the formation of the conductor patterns on the surface.
Several modifications can be made to the process. For example, a thin (50 nm) layer of polysilicon can be deposited over the silicon nitride layer 12. This will improve the selectivity of the SiO2 RIE, making complete removal thereof more feasible without impairing the uniformity of the silicon nitride etch stop. Also a thin (50 nm) layer of silicon nitride can be deposited over the SiO2 layer 18 before the deposition of the polysilicon layer 20. This will help prevent reduction of the SiO2 layer during the first chemical-mechanical polishing step for the remaining polysilicon layer 20 overlying the trenches 18.
It is also contemplated that similar process steps can be used to form planarized surfaces wherein trenches are filled with conductive materials rather than dielectric material. In such case, the masking materials and etch reagents and conditions are selected to provide the selectivity required.
While several embodiments of the present invention have been shown and described, various adaptions and modifications can be made without departing from the scope of the invention as defined in the appended claims.
Koburger, III, Charles W., Kerbaugh, Michael L., Machesney, Brian J., Dash, Somanath, Parekh, Nitin B.
| Patent | Priority | Assignee | Title |
| 5346584, | Jul 28 1993 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Planarization process for IC trench isolation using oxidized polysilicon filler |
| 5382541, | Aug 26 1992 | Intersil Corporation | Method for forming recessed oxide isolation containing deep and shallow trenches |
| 5389559, | Dec 02 1993 | International Business Machines Corporation | Method of forming integrated interconnect for very high density DRAMs |
| 5420065, | May 28 1993 | HEWLETT-PACKARD DEVELOPMENT COMPANY, L P | Process for filling an isolation trench |
| 5492858, | Apr 20 1994 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
| 5494857, | Jul 28 1993 | Digital Equipment Corporation | Chemical mechanical planarization of shallow trenches in semiconductor substrates |
| 5504033, | Aug 26 1992 | Intersil Corporation | Method for forming recessed oxide isolation containing deep and shallow trenches |
| 5521422, | Dec 02 1994 | International Business Machines Corporation | Corner protected shallow trench isolation device |
| 5539229, | Dec 28 1994 | International Business Machines Corporation | MOSFET with raised STI isolation self-aligned to the gate stack |
| 5629242, | Jan 07 1994 | Sony Corporation | Process for planarizing surface of a semiconductor device |
| 5643837, | Apr 15 1992 | Renesas Electronics Corporation | Method of flattening the surface of a semiconductor device by polishing |
| 5663107, | Dec 22 1994 | Qimonda AG | Global planarization using self aligned polishing or spacer technique and isotropic etch process |
| 5665202, | Nov 24 1995 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Multi-step planarization process using polishing at two different pad pressures |
| 5688720, | Apr 15 1992 | NEC Corporation | Method of flattening the surface of a semiconductor device by polishing |
| 5721172, | Dec 02 1996 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers |
| 5721173, | Feb 25 1997 | Kabushiki Kaisha Toshiba | Method of forming a shallow trench isolation structure |
| 5795829, | Jun 03 1996 | Advanced Micro Devices, Inc. | Method of high density plasma metal etching |
| 5880006, | May 22 1998 | VLSI Technology, Inc. | Method for fabrication of a semiconductor device |
| 5972570, | Jul 17 1997 | GOOGLE LLC | Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby |
| 6008107, | Jun 14 1990 | National Semiconductor Corporation | Method of planarizing integrated circuits with fully recessed isolation dielectric |
| 6022781, | Dec 28 1994 | International Business Machines Corporation | Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack |
| 6048775, | May 24 1999 | Vanguard International Semiconductor Corporation | Method to make shallow trench isolation structure by HDP-CVD and chemical mechanical polish processes |
| 6048800, | Jan 17 1994 | Sony Corporation | Process for planarizing surface of a semiconductor device |
| 6051496, | Sep 17 1998 | Taiwan Semiconductor Manufacturing Company | Use of stop layer for chemical mechanical polishing of CU damascene |
| 6093656, | Feb 26 1998 | United Microelectronics Corp | Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device |
| 6103455, | May 07 1998 | Taiwan Semiconductor Manufacturing Company | Method to form a recess free deep contact |
| 6103592, | May 01 1997 | Qimonda AG | Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas |
| 6107187, | Jun 17 1999 | Freescale Semiconductor, Inc | Method for forming a semiconductor device |
| 6147394, | Jul 17 1997 | International Business Machines Corporation | Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby |
| 6197691, | Nov 15 1999 | Chartered Semiconductor Manufacturing Ltd. | Shallow trench isolation process |
| 6207533, | Oct 08 1999 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an integrated circuit |
| 6221775, | Sep 24 1998 | International Business Machines Corporation | Combined chemical mechanical polishing and reactive ion etching process |
| 6271138, | Sep 27 1999 | Taiwan Semiconductor Manufacturing Company | Chemical mechanical polish (CMP) planarizing method with enhanced chemical mechanical polish (CMP) planarized layer planarity |
| 6309948, | May 22 1998 | VLSI Technology, Inc. | Method for fabrication of a semiconductor device |
| 6322634, | Jan 27 1997 | Micron Technology, Inc | Shallow trench isolation structure without corner exposure |
| 6323082, | Jul 30 1998 | International Business Machines Corporation | Process for making a DRAM cell with three-sided gate transfer |
| 6369418, | Mar 19 1998 | Invensas Corporation | Formation of a novel DRAM cell |
| 6395620, | Oct 08 1996 | Micron Technology, Inc. | Method for forming a planar surface over low density field areas on a semiconductor wafer |
| 6403484, | Mar 12 2001 | Chartered Semiconductor Manufacturing Ltd. | Method to achieve STI planarization |
| 6426237, | Dec 18 1998 | Eastman Kodak Company | Method for producing optically planar surfaces for micro-electromechanical system devices |
| 6432797, | Jan 25 2001 | Chartered Semiconductor Manufacturing LTD | Simplified method to reduce or eliminate STI oxide divots |
| 6436833, | Mar 15 2001 | Chartered Semiconductor Manufacturing LTD | Method for pre-STI-CMP planarization using poly-si thermal oxidation |
| 6475875, | Jul 09 2001 | Chartered Semiconductor Manufacturing Ltd. | Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer |
| 6531265, | Dec 14 2000 | International Business Machines Corporation | Method to planarize semiconductor surface |
| 6593197, | Oct 20 2000 | GLOBALFOUNDRIES U S INC | Sidewall spacer based fet alignment technology |
| 6664190, | Sep 14 2001 | Chartered Semiconductor Manufacturing Ltd. | Pre STI-CMP planarization scheme |
| 6720233, | Oct 12 1995 | Method of producing trench insulation in a substrate | |
| 6774042, | Feb 26 2002 | Taiwan Semiconductor Manufacturing Company | Planarization method for deep sub micron shallow trench isolation process |
| 6919260, | Nov 21 1995 | Kabushiki Kaisha Toshiba | Method of manufacturing a substrate having shallow trench isolation |
| 7153781, | Jun 19 2000 | Polaris Innovations Limited | Method to etch poly Si gate stacks with raised STI structure |
| 7396737, | Oct 13 2005 | DONGBU ELECTRONICS CO , LTD | Method of forming shallow trench isolation |
| 7446046, | Jan 06 2005 | Intel Corporation | Selective polish for fabricating electronic devices |
| 7892941, | Jan 27 1997 | Micron Technology, Inc. | Technique for forming shallow trench isolation structure without corner exposure |
| 8338264, | Jan 27 1997 | Micron Technology, Inc. | Methods for forming isolation structures for semiconductor devices |
| 8497210, | Oct 04 2010 | GLOBALFOUNDRIES U S INC | Shallow trench isolation chemical mechanical planarization |
| 8507383, | Oct 04 2010 | GLOBALFOUNDRIES U S INC | Fabrication of replacement metal gate devices |
| 8513127, | Oct 04 2010 | GLOBALFOUNDRIES U S INC | Chemical mechanical planarization processes for fabrication of FinFET devices |
| 8524606, | Oct 04 2010 | GLOBALFOUNDRIES U S INC | Chemical mechanical planarization with overburden mask |
| 8637956, | Jan 27 1997 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor devices structures including an isolation structure |
| Patent | Priority | Assignee | Title |
| 4278987, | Oct 17 1977 | Hitachi, Ltd. | Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations |
| 4376672, | Oct 26 1981 | Applied Materials, Inc. | Materials and methods for plasma etching of oxides and nitrides of silicon |
| 4385975, | Dec 30 1981 | International Business Machines Corp. | Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate |
| 4526631, | Jun 25 1984 | International Business Machines Corporation | Method for forming a void free isolation pattern utilizing etch and refill techniques |
| 4671851, | Oct 28 1985 | International Business Machines Corporation | Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique |
| 4671970, | Feb 05 1986 | MagnaChip Semiconductor, Ltd | Trench filling and planarization process |
| 4836885, | May 03 1988 | International Business Machines Corporation | Planarization process for wide trench isolation |
| 4962069, | Nov 07 1988 | Dow Corning Corporation | Highly densified bodies from preceramic polysilazanes filled with silicon carbide powders |
| EP300569, | |||
| EP341898, | |||
| FR2599892, | |||
| JP59117233, | |||
| JP5913342, | |||
| JP59175138, | |||
| JP59177941, | |||
| JP59193044, | |||
| JP60236244, |
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