A method of manufacturing a printed wiring board is disclosed. The method comprises the steps of forming a printed circuit on a substrate, coating an insulating layer on at least a part of the printed circuit, coating a shield layer on at least a part of the insulating layer, and forming the shield layer by a halftone dot.
|
4. A method of producing a printed circuit board, comprising:
forming a circuit on a substrate; covering at least a portion of the circuit with an insulating layer; and applying a shield layer of halftone dots on at least a portion of the insulating layer.
1. A method of manufacturing a printed wiring board which comprises the steps of forming a printed circuit on a substrate, coating an insulating layer on at least a part of the printed circuit, and coating a shield layer on at least a part of the insulating layer by applying a pattern of halftone dots.
2. A method of manufacturing a printed wiring board as claimed in
3. A method of manufacturing a printed wiring board as claimed in
|
|||||||||||||||||||||||||
This is a continuation of application Ser. No. 073,608 filed Jun. 7, 1993 now abandoned which is a continuation of application Ser. No. 982,146 filed Nov. 25, 1992, now abandoned which is a continuation of application Ser. No. 896,729 filed Jun. 9, 1992, now abandoned which is a continuation of application Ser. No. 784,688 filed Oct. 30, 1991, now abandoned which is a continuation of application Ser. No. 379,435 filed Jul. 12, 1989 now abandoned.
The present invention relates to a method of manufacturing a printed wiring board, more particularly, to a printed wiring board in which a printed circuit is formed on a substrate, an insulating layer is coated on at least a part of the printed circuit, a shield layer is coated on at least a part of the insulating layer.
Such a printed wiring or circuit board is well known from, for example, the Japanese Utility Model Application Publication No. 29,276/80. In this case, the shield layer is usually obtained by coating copper paste over desired portions of the insulating layer.
The coating of the above shield layer is performed by coating the copper paste substantially over the whole surface of the insulating layer with a screen process printing, so that the new provision of a mask for printing may be omitted. However, this method must increase the desired amount of the copper paste so that heat dissipation of the printed circuit board becomes decreased and the shield layer is susceptible to cause cracks in the drying process.
It is an object of the present invention to overcome the above described disadvantages.
It is another object of the present invention to provide a method of manufacturing a printed wiring board in which heat dissipation becomes increased and cracks are not caused in the drying process.
According to the present invention, there is provided a method of manufacturing a printed wiring board which comprises the steps of forming a printed circuit on a substrate, coating an insulating layer on at least a part of the printed circuit, coating a shield layer on at least a part of the insulating layer, and forming the shield layer by a halftone dot.
In a preferred embodiment of the method according to the present invention, the halftone dot is fabricated in a shape of a net formed by a continuous fine strip.
In another feasible version of the method according to the present invention, the halftone dot is fabricated in a shape of a desired pattern formed by a number of dots of discontinuity.
According to the above method of the present invention, the shield layer is formed by a halftone dot, so that the desired amount of the copper paste may be considerably decreased and the average thickness of the copper paste coated on the insulating layer may be decreased, thereby holding excellent heat dissipation and preventing the shield layer from cracking in the drying process. The method according to the present invention requires substantially the same printing labor for the shield layer as that of the conventional method, except for an addition of the halftone dot mask.
The invention will be described in detail hereinafter with reference to the drawing.
FIG. 1 is a plan view showing a part of a printed wiring board manufactured by the method according to the present invention; and
FIG. 2 is a cross-sectional view showing a part of the printed wiring board shown in FIG. 1.
Referring now to the drawing, FIG. 1 shows a part of a printed wiring board according to the present invention.
Referring to FIG. 2, a printed wiring circuit 12 is formed by coating a copper foil on one surface or both surface of an insulating substrate 10 with the use of a conventional method. An insulating paste is coated on the circuit conductors 12 throughout the desired range thereof by the screen process printing or the like, thereby forming an insulating layer 14. A copper paste is coated on a part or whole surface of the insulating layer 14 by the screen process printing or the like, thereby forming a shield layer 16. In the conventional method, the shield layer 16 is coated on the whole surface of the insulating layer 14 with the use of a mask for forming the insulating layer, in order to save or omit the preparation of new additional mask. The shield layer 16 is connected to a grounded terminal 18. If necessary, a protection film 20 is coated on the shield layer 16.
The above process is well known and utilized widely. This well known method requirs a great amount of the copper paste so that the effect of heat dissipation becomes decreased. Moreover, the thickness of the copper paste becomes large so that thermal expansion and contraction become large, thereby cracking the coated film, resulting in a lack of dimensional stability.
According to the method of the present invention, the shield layer 16 is formed by halftone dots 22. In the preferred method, the halftone dots are formed by a number of dots of discontinuity. These dots of discontinuity are formed by providing copper paste on the insulating layer 14 by the screen process printing with the use of a mask in the shape of net pattern shown in FIG. 1. The pattern formed on the insulating layer 14 is a shield layer 16 consisting of a continuous fine strip and connected to a grounded terminal 18.
Alternatively, the halftone dot may be formed by a continuous netting wire from the begining, or the halftone dot may be so formed that dot arrangement of discontinuity on the mask may be formed in a pattern other than the net. In this case, the same effect may be obtained in these versions.
As described above, according to the present invention, the shield layer 16 is formed by halftone dots so that the coating film layer provided on the printed wiring circuit 12 becomes substantially decreased. Therefore, as compared with the conventional method, the desired amount of the copper paste becomes substantially decreased so that the heat dissipation effect is not obstructed, resulting in a high dimensional stability. The mask for forming halftone dot may be manufactured simply, so that the method according to the present invention may be advantageously obtained in economy and in practice.
| Patent | Priority | Assignee | Title |
| 10522425, | Dec 12 2013 | Kateeva, Inc. | Fabrication of thin-film encapsulation layer for light emitting device |
| 10586742, | Dec 12 2013 | Kateeva, Inc. | Fabrication of thin-film encapsulation layer for light emitting device |
| 10811324, | Dec 12 2013 | KATEEVA, INC | Fabrication of thin-film encapsulation layer for light emitting device |
| 10950826, | Dec 27 2012 | Kateeva, Inc. | Techniques for print ink droplet measurement and control to deposit fluids within precise tolerances |
| 11088035, | Dec 12 2013 | Kateeva, Inc. | Fabrication of thin-film encapsulation layer for light emitting device |
| 11233226, | Dec 27 2012 | Kateeva, Inc. | Nozzle-droplet combination techniques to deposit fluids in substrate locations within precise tolerances |
| 11456220, | Dec 12 2013 | KATEEVA, INC | Techniques for layer fencing to improve edge linearity |
| 11489146, | Dec 27 2012 | Kateeva, Inc. | Techniques for print ink droplet measurement and control to deposit fluids within precise tolerances |
| 11551982, | Dec 12 2013 | Kateeva, Inc. | Fabrication of thin-film encapsulation layer for light-emitting device |
| 11673155, | Dec 27 2012 | Kateeva, Inc. | Techniques for arrayed printing of a permanent layer with improved speed and accuracy |
| 11678561, | Dec 27 2012 | Kateeva, Inc. | Nozzle-droplet combination techniques to deposit fluids in substrate locations within precise tolerances |
| 6911605, | Nov 13 2001 | Fujikura Ltd | Flexible printed circuit |
| 9806298, | Dec 12 2013 | KATEEVA, INC | Techniques for edge management of printed layers in the fabrication of a light emitting device |
| 9831473, | Dec 12 2013 | Kateeva, Inc. | Encapsulation layer thickness regulation in light emitting device |
| 9960087, | Dec 12 2013 | Kateeva, Inc. | Fabrication of thin-film encapsulation layer for light emitting device |
| Patent | Priority | Assignee | Title |
| 3619899, | |||
| 5195238, | Jul 20 1990 | Nippon CMK Corp. | Method of manufacturing a printed circuit board |
| JP63142889, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Date | Maintenance Fee Events |
| Aug 11 1998 | REM: Maintenance Fee Reminder Mailed. |
| Sep 13 1998 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
| Date | Maintenance Schedule |
| Sep 13 1997 | 4 years fee payment window open |
| Mar 13 1998 | 6 months grace period start (w surcharge) |
| Sep 13 1998 | patent expiry (for year 4) |
| Sep 13 2000 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Sep 13 2001 | 8 years fee payment window open |
| Mar 13 2002 | 6 months grace period start (w surcharge) |
| Sep 13 2002 | patent expiry (for year 8) |
| Sep 13 2004 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Sep 13 2005 | 12 years fee payment window open |
| Mar 13 2006 | 6 months grace period start (w surcharge) |
| Sep 13 2006 | patent expiry (for year 12) |
| Sep 13 2008 | 2 years to revive unintentionally abandoned end. (for year 12) |