A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 Å. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300°C for 10 min. This is due to the formation of aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.
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1. An n-InP Schottky diode intermediate product comprising:
a n-InP substrate having a native inpo4 on its surfaces; an aluminum layer having a thickness of from about 80 Å to about 120 Å being formed on an upper surface of said n-InP substrate; and a platinum layer formed on said aluminum layer.
2. The n-InP Schottky diode intermediate product according to
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This application is a continuation of application Ser. No. 08/255,163, filed Jun. 7, 1994, now abandoned.
1. Field of the Invention
The present invention relates to a Schottky diode structure and a manufacturing method thereof, and more particularly to a Schottky diode structure based on metal/n-InP contact.
1. Description of the Prior Art
Owing to the surface Fermi level pinning arising from the presence of large surface states and other nonstoichiometric defects, the Schottky barrier height greater than 0.5 eV is very difficult to obtain on n-InP. Such a small barrier height causes a large reverse leakage current and hinders the development of InP device applications. A common approach to increase the Schottky barrier height is to form a thin dielectric layer between the metal and the n-InP substrate. Various techniques such as H2 -plasma or PH3 -plasma treatment, growing a thin P3 N5 film, POx Ny Hz film, or an interfacial oxide layer on the InP surface were employed to treat the surface of InP to increase the Schottky barrier height. Schottky diodes fabricated by applying these techniques typically have a barrier height of about 0.7-0.8 eV. Recently, a low temperature (77K) deposition was reported for the metal/n-InP contact to obtained a Schottky barrier height as high as 0.96 eV [Z. Q. Shi, et. al., Appl. Phys. lett. 59, 446 (1991 )]; however, it also has a shortcoming of large reverse leakage current. J. Dunn and G. B. Stringfellow in their article, entitled "Ag/AI Schottky Contacts on n-InP", Journal of Electronic Material 17, 181 (1988), disclose Ag/At/n-InP Schottky diode which has a barrier height of only 0.65 eV. Moreover, the current voltage characteristics of this Ag/AI/n-InP Schottky diode is also not very satisfactory.
Therefore, there is a need in the industry to develop a new structure of Schottky diode having a relatively higher barrier height and a reduced reverse leakage current.
An object of the present invention is to provide a n-InP Schottky diode structure which has a relatively higher barrier height and a reduced reverse leakage current.
Another object of the present invention is to provide a method of manufacturing n-InP Schottky diode structure which has a relatively higher barrier height and a reduced reverse leakage current.
In order to achieve these objects, a n-InP Schottky diode structure constructed in accordance the present invention comprises:
an undoped n-InP substrate having a native InPO4 on its surfaces;
an aluminum layer having a thickness of 80-120 Å being formed on an upper surface of the n-InP substrate; and
a platinum layer formed on the aluminum layer,
in which the aluminum layer is converted to an aluminum oxide interfacial layer between the n-InP substrate and the platinum layer after reacting with the native InPO4 of the InP substrate.
Preferably, an ohmic contact is formed on a bottom surface of the n-InP substrate which is opposite to the upper surface of the n-InP substrate.
A method of manufacturing the n-InP Schottky diode structure of the present invention comprising the following steps:
a) forming an insulating layer on a surface of an undoped n-InP substrate;
b) forming contact patterns on the insulating layer by photolithography with a photoresist composition;
c) etching the patterned insulating layer to form contact windows;
d) depositing an aluminum layer on the surface having contact windows of the resulting n-InP substrate of step c);
e) depositing a platinum layer on the aluminum layer;
f) dissolving the photoresist composition patterns under the aluminum layer with a solvent so that the portions of the aluminum and the platinum deposited on the photoresist composition patterns are removed and the portions of the aluminum and the platinum deposited in the contact windows are remained on the n-InP substrate; and
g) annealing the resulting PtJAI/n-InP contact of step f),
in which the aluminum layer of step d) has a thickness of 80-120 Å and is converted to an aluminum oxide interfacial layer between the n-InP substrate and the platinum layer after reacting with a native InPO4 at the surface of the nInP substrate.
A Pt/Al/n-InP Schottky diode made in accordance with one of the preferred embodiments of the present invention gives a barrier height of 0.74 eV and an ideality factor of 1.11 from its I-V (current density-voltage) characteristics plot, and a barrier height of 0.9 eV from its C-V (capacity-voltage) characteristics plot.
FIG. 1 is a schematic cross-sectional view of a Pt/Al/n-InP Schottky diode made in accordance with one of the preferred embodiments of the present invention.
FIG. 2(a)-(g) are schematic cross-sectional views of a device during key steps of a method of manufacturing the Pt/Al/n-InP Schottky diode shown in FIG. 1.
FIG. 3 is a plot which shows the I-V characteristics of Pt(500 Å)/AI(85 Å)/n-InP Schottky contact after furnace annealing (F.A.) at 300°C for 10 min.
FIG. 4 is a plot which shows the C-V characteristics of Pt(500 Å)/AI(85 Å)/n-InP Schottky contact after furnace annealing (F.A.) at 300°C for 10 min.
FIG. 5 is a plot which shows the Schottky barrier heights dependence on the sandwiched AI thickness for Pt (500 Å)/AI(x Å)/n-InP Schottky diodes fabricated without annealing (--∘--) and with an 10 minutes' time furnace annealing (F.A.) at 400°C (-- --).
FIG. 6 is a plot which shows the Schottky barrier heights and ideality factors dependence on the annealing temperature used in the fabrication of Pt(500 Å)/AI(85 Å)/n-InP Schottky diodes.
FIG. 7 is a plot which shows the SIMS (Secondary Ion Mass Spectrometer) in-depth profile of secondary ion counts in the Pt(500 Å)/AI(85 Å)/n-InP Schottky diode after furnace annealing (F.A.) at 300° C. for 10 min, wherein----represents O element, represents In element, -- -- -- represents AI element, represents Pt element, and - - - - represents P element.
In this invention, a Pt/Al/n-InP Schottky diode structure and a method of making same are disclosed. The Pt/Al/n-InP Schottky diode structure comprises:
an undoped n-InP substrate;
an aluminum layer having a thickness of 80-120 Å being formed on an upper surface of the n-InP substrate; and
a platinum layer formed on the aluminum layer.
It was reported by J. R. Waldrop, et. al. in an article, entitled "Summary Abstract: Fermi-level pinning energy and chemistry at InP(100) interfaces", J. Vac. Sci. Technol. B 1 (3), July-Sept. 1983, that a∼4 Å thick InPO4 native-oxide layer exists on the initial etched surface of InP wafer. Therefore, it is believed that the aluminum layer of the Pt/Al/n-InP Schottky diode structure will be converted to an aluminum oxide interfacial layer between the n-InP substrate and the platinum layer after reacting with the native InPO4 of the InP substrate during a deposition process of forming the AI layer and/or an annealing treatment after a deposition process of forming the Pt layer.
FIG. 1 illustrates a schematic cross-sectional view of a Pt/Al/n-InP Schottky diode made in accordance with one of the preferred embodiments of the present invention, in which a layer of AuGeNi is formed on the bottom surface of the InP substrate as an ohmic contact.
A suitable method of manufacturing the Pt/Al/n-InP Schottky diode shown in FIG. 1 will be described in the following text by referring to FIG. 2(a)-FIG. 2(g). The devices were made on undoped n-type InP substrates having a free carrier concentration of 5-9×1015 cm-3, as illustrated in FIG. 2(a). Ohmic contacts were formed on the backside of the substrate by evaporating AuGeNi and annealing at 400°C for 3 min, as shown in FIG. 2(b). The wafers were then degreased with trichloroethylene (TCE), acetone (ACE), methanol and deionized water in sequence and then soaked in H2 SO4 (98%) for 3 min and etched in NH4 OH:H2 O2 :H2 O=3:1:15 for 3 min to remove the surface damages. A thickness of 2000 Å of SiO2 was then deposited on the wafers by plasma enhanced chemical vapor deposition (PECVD), as shown in FIG. 2(c), and the contact patterns were defined by photolithography technique with a positive photoresist composition (P.R.), as shown in FIG. 2(d). The SiO2 in the contact windows were etched by a buffered oxidant etchant (BOE), and then rinsed in deionized water, as shown in FIG. 2(e). The multilayer metals Pt(500 Å)/AI(85 Å) were deposited sequentially upon the samples by sputtering at a vacuum of 4× 10-6 Torr, as shown in FIG. 2(f), and metal patterns were obtained by using a lift-off process in which the P.R. under the aluminum layer was dissolved in acetone so that the portions of the aluminum and the platinum deposited on the P.R. were removed and the portions of the aluminum and the platinum deposited in the contact windows were remained on the n-InP substrate. The wafers were then annealed in an N2 gas flow in a furnace, as shown in FIG. 2(g). The diode area was equal to 0.000225 cm2.
To evaluate the depth distribution of all elements of the deposition films, a secondary ion mass spectrometer (SIMS) analysis was performed, of which the primary beam was a 133 Cs+ beam at 10 KeV with a current of 16 nA and a rastering area of 225×2.25 μm2.
FIG. 3 shows the current density-voltage (I-V) characteristics of the fabricated Pt(500 Å)/AI(85 Å)/n-InP Schottky diodes after annealing at 300°C for 10 minutes. The effective barrier height, Ob, was calculated from the following equation. Ob =(kT/q)In(A*T2 /J0) where A*=9.6 Acm-2 K-2 is the Richardson constant, and J0 is the saturation current density. The ideality n factor is determined from the forward characteristics using the relations n=q/kT[∂V/∂(InJ)]. The barrier height and ideality factor were 0.74 eV and 1.11 respectively. The ideality n factor exceed unity was due to the existence of the interfacial layer. The corresponding C-V data for the Schottky diode (the concentration of donor ions Nd =3.75×1015 cm-3), taken at 100 KHz over a 0 to -3 V range, were analyzed according to the conventional model that gives Ocb in terms of the intercept Vi (found by a least-square fitting) in the voltage axis of a 1/C2 vs V plot. There were no significant deviations from linearity in the 1/C2 vs V plot, as shown in FIG. 4. The Ocb was equal to 0.9 eV, substantially larger than the value from the I-V characteristics.
For the Pt/Al/n-InP Schottky diode, the thickness of AI should be taken into consideration. FIG. 5 shows the barrier height dependence on the AI thickness of the Pt/Al/n-InP device, where the thickness of Pt was kept constant as 500 Å and the thickness of AI was varied from 0 to 200 Å. The barrier height of the Pt/n-InP contact nearly "ohmic". The barrier height increased from 0.4 eV to 0.72 eV and 0.64 eV for the 400°C, 10 min annealed and the as-deposited devices for the AI thickness was increased to 85 Å respectively. It was reported that an InP wafer, after the final rinse in the deionized water, a thin native oxide, InPO4, exists on the surface. It is speculated that this native oxide would react with the deposited AI during the deposition process to form an Aluminum-oxide, and the oxygen in the chamber was captured during Al deposition which serves as the sandwiched insulator between the InP substrate and Pt layer which was deposited in the following sequence. As the thickness of deposited AI increased, the interfacial layer increased too, as a result of increasing the effective barrier height. But for thicker AI layer (200 Å) of the Pt/Al/InP contact, the AI was thick enough to form interfacial layer and remained some unreacted AI. The structure could modify as Pt/Al/interfacial-layer/InP contact structure. Its electrical characteristic was similar to single metal AI contacted to InP, with very low barrier height and large leakage current. So there existed a Ocb peaks and then decreased with increasing AI thickness as shown in FIG. 5. A furnace annealing would help enhance the reaction of the AI with the oxide. This is manifested by the data in FIG. 5 for the annealed devices, for which the barrier height values are higher.
FIG. 6 is a plot which shows the Schottky barrier heights and ideality factors dependence on the annealing temperatures used in the fabrication of Pt(500 Å)/AI(85 Å)/n-InP Schottky diodes. A suitable annealing temperature will be about 300°-400°C for the fabrication of Pt(500 Å)/AI(85 Å)/n-InP Schottky diode.
FIG. 7 is a plot which shows the SIMS in-depth profile of secondary ion counts in the Pt/Al/n-InP Schottky diodes after annealing at 300° C. for 10 min. There existed a significant amount of oxygen at the interface. This supported the point of view for the formation of Aluminum-oxide in the contact surface.
In conclusion, a new Schottky contact structure, Pt/Al/n-InP, which was prepared in a simple process but could give a good diode performance was disclosed. Different thickness of AI gave different value of barrier height. It is found that as the thickness of AI equal to 80-120 Å could obtain better Ob value. For the diode of Pt(500Å)/AI(85 Å)/n-InP its barrier height equal to 0.74 eV after it was annealed at 300 °C for 10 min. This good performance is to be believed due to the effect of the formation of interfacial oxide layer.
Although the preferred embodiment of the invention has been disclosed above for illustration purpose, those skilled in the art will appreciate that various modifications, additions and substitution are possible without departing from the scope and spirit of the invention as set forth in the accompanying claims.
Huang, Wen C., Lei, Tan F., Lee, Chung L.
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