A uv light-enhanced process for rapidly stripping films of silicon nitride in a dry reaction environment, which may be free of plasma or plasma effluents. This process is carried out in a sealed reactor which allows simultaneous exposure of a substrate wafer to a polyatomic fluorine containing gas which can be photodissociated by uv radiation to produce atomic fluorine and to uv radiation. silicon nitride stripping rates in excess of 500 Å/min are readily obtainable with uv-stimulated fluorine-based processes, while maintaining the bulk wafer temperature below 300°C Selectivities for silicon nitride-to-silicon oxide etching of greater than 30 can be achieved for the stripping of silicon nitride LOCOS mask layers in the presence of field oxide and pad oxide layers when a chlorine or bromine containing gas which can be photodissociated by uv radiation to produce atomic chlorine or bromine is used in mixture with the fluorine containing gas. Selectivity and etch rate are controlled through uv lamp exposure, substrate temperature, and additions of nitrogen diluent, and photodissociable chlorine or bromine containing gases. The process addresses many of the limitations of plasma-downstream etch tools for dry silicon nitride stripping, including complete elimination of charged particles and sputtered contaminants associated with plasma effluents.

Patent
   5534107
Priority
Jun 14 1994
Filed
Aug 18 1994
Issued
Jul 09 1996
Expiry
Jun 14 2014
Assg.orig
Entity
Large
82
38
EXPIRED
1. A method of removing silicon nitride from a substrate, the method comprising
placing the substrate in a gaseous environment comprising at least one first gas and at least one second gas, the first gas being a fluorine-containing gas which can be photodissociated by uv radiation to produce atomic fluorine and the second gas being a chlorine-containing or a bromine containing gas which can be photodissociated by uv radiation to produce atomic chlorine or bromine, and
exposing the substrate to uv irradiation in the presence of the gaseous environment.
22. A method of removing silicon nitride from a substrate, the method comprising:
placing the substrate in a gaseous environment comprising at least one first gas, the first gas being a fluorine-containing gas which can be photodissociated by uv radiation to produce atomic fluorine, and
exposing the substrate to uv irradiation in the presence of the gaseous environment,
wherein the integrated intensity of the uv irradiation at the substrate surface over the range of 180-400 nm is at least 50 mW/cm2, the temperature of the substrate before irradiation is in the range of 20°-400°C, and the partial pressure of said first gas is at least 10 torr.
2. A method as in claim 1 wherein the gaseous environment is substantially free of plasma products.
3. A method as in claim 1 wherein the first gas is selected from the group consisting of fluorine, fluorine interhalogens, fluorides of sulfur and xenon difluoride.
4. A method as in claim 1 wherein the substrate comprises silicon or silicon oxide.
5. A method as in claim 1 wherein the gaseous environment further comprises a third gas, the third gas being an inert gas.
6. A method as in claim 5 wherein the third gas is selected from the group consisting of helium (He), argon (Ar), and nitrogen (N2).
7. A method as in claim 1 wherein the substrate further comprises on at least a portion of the surface thereof a silicon oxide material which is desired to be retained on the substrate.
8. A method as in claim 7 wherein the silicon oxide material comprises a doped oxide film, a CVD oxide film, or a thermal oxide film.
9. A method as in claim 8 wherein the doped oxide is selected from the group consisting of boron and phosphorus doped silica glass, phosphorous doped silica glass, boron doped silica glass, and spin on glass.
10. A method as in claim 7 wherein the silicon oxide material desired to be retained comprises a thermally grown field oxide formed as a result of a LOCOS process.
11. A method as in claim 1 wherein the silicon nitride material to be etched is part of a composite stack of materials which includes at least one material selected from the group consisting of silicon oxynitride, polysilicon, and silicon oxide.
12. A method as in claim 1 wherein the silicon nitride is a mask layer for a LOCOS process on a silicon substrate.
13. A method as in claim 12 wherein a thermally grown pad oxide layer is located between the silicon substrate and the silicon nitride mask layer, the method being conducted under conditions of time, gas flow rates, uv intensity, first and second gas ratios and temperature such that the pad oxide layer is not penetrated.
14. A method as in claim 13 wherein a polysilicon layer is located between the pad oxide layer and the silicon nitride mask layer and the method conducted for sufficient time to remove the polysilicon layer as well as the silicon nitride mask layer.
15. A method as in claim 1 wherein the silicon nitride to be removed has an over layer of silicon oxynitride.
16. A method as in claim 1 wherein the integrated intensity of the uv irradiation at the substrate surface over the range of 180-400 nm is at least 50 mW/cm2, the temperature of the substrate before irradiation is in the range of 20°-400°C, and the partial pressure of said first gas is at least 10 torr.
17. A method as in claim 16, wherein the first gas is F2, ClF3, or BrF3, the second gas is chlorine, the integrated intensity of the uv irradiation at the substrate surface over the range of 180-400 nm is at least 200 mW/cm2, the pressure of the first gas is at least 20 torr and the first and second gases are present at a pressure ratio of 2:1-1:2, and the temperature of the substrate before irradiation is at least 150°C
18. A method as in claim 1 wherein the integrated intensity of the uv irradiation at the substrate surface over the range of 240-400 nm is at least 200 mW/cm2.
19. A method as in claim 1 wherein the substrate is a silicon wafer, the method further comprising the steps of:
(a) prior to said placing step, evacuating a hermetically-sealed processing chamber having a uv transparent window therein to a low base pressure and introducing the silicon wafer substrate into the processing chamber,
(b) conducting said placing step by introducing into said chamber said gaseous environment,
(c) conducting said exposing step by irradiating the gaseous environment and substrate in said chamber to ultraviolet light through said uv transparent window,
(d) evacuating the processing chamber, and
(e) removing the substrate from the processing chamber.
20. A method as in claim 1 wherein the placing step comprises introducing said first and second gases into a chamber containing said substrate and the method further comprises the step of exciting said gases by a plasma generating source prior to introducing said gases into said chamber.
21. A method as in claim 20 wherein said exciting step is accomplished with a microwave or a radio frequency energy source.
23. A method as in claim 22 wherein the gaseous environment is substantially free of plasma products.
24. A method as in claim 22 wherein the placing step comprises introducing said first and second gases into a chamber containing said substrate and the method further comprises the step of exciting said gases by a plasma generating source prior to introducing said gases into said chamber.
25. A method as in claim 24 wherein said exciting step is accomplished with a microwave or a radio frequency energy source.
26. A method as in claim 22 wherein the first gas is selected from the group consisting of chlorine trifluoride, bromine trifluoride, bromine pentafluoride, iodine pentafluoride, xenon difluoride, fluorine and sulfur hexafluoride.
27. A method as in claim 22 wherein the substrate comprises silicon or silicon oxide.
28. A method as in claim 22 wherein the gaseous environment further comprises an inert gas.
29. A method as in claim 22 wherein the integrated intensity of the uv irradiation at the substrate surface over the range of 180-400 nm is at least 200 mW/cm2.
30. A method as in claim 22 wherein the integrated intensity of the uv irradiation at the substrate surface over the range of 240-400 nm is at least 200 mW/cm2.
31. A method as in claim 22 wherein the partial pressure of the first gas is in the range of 10 torr-760 torr.
32. A method as in claim 31 wherein the partial pressure of the first gas is at least 50 torr, the temperature of the substrate before irradiation is 150°-250°C, and the integrated intensity of the uv irradiation at the substrate surface over the range of 180-400 nm is at least 200 mW/cm2.
33. A method as in claim 22 wherein the temperature of the substrate before irradiation is at least 150°C
34. A method as in claim 22 wherein the method produces a silicon nitride removal rate of at least 100 Å/min.
35. A method as in claim 34 wherein said silicon nitride removal rate is at least 500 Å/min.

This application is a continuation-in-part of Ser. No. 08/259,542, filed Jun. 14, 1994, incorporated herein by reference.

Chemical vapor deposited (CVD) and plasma enhanced chemical vapor deposited (PECVD) silicon nitride films have important applications in advanced integrated circuits manufacture. Specific applications include masking layers for local oxidation of silicon (LOCOS), passivation layers and diffusion barriers, and final mechanical protection layers for IC's. A favored method for isolating active regions in advanced CMOS manufacturing is the poly-buffered LOCOS process (PBL), described in Lin, T., N. Tsai and C. Yoo, "Twin-White-Ribbon Effect and Pit Formation Mechanism in PBLOCOS", J. Electrochem. Soc., 138(7), 1991, p 2145, which involves a "stack" of silicon oxide/polysilicon/silicon nitride on a silicon substrate. The silicon oxide "pad" layer is typically 10 nm, while the polysilicon and top silicon nitride layer are typically 50 nm and 250 nm, respectively. After deposition of this composite film over the silicon substrate, active device regions are masked and an anisotropic plasma etching process is typically used to etch the open or "field" regions down to the pad oxide. The wafer is subsequently subjected to a thermal oxidation process for growth of the "field oxide" in the etched areas, which is typically 500 nm in thickness. This process also leaves a thin oxynitride film on top of the silicon nitride. After the field oxide is grown, the stack is removed.

Currently, removal of the PBL stack from the active device regions is done in wet chemical process steps which include an HF acid solution for etching or "deglaze" of the top oxynitride layer, followed by removal of the silicon nitride layer in a hot phosphoric acid solution. The polysilicon layer is subsequently removed in an additional dry etching process, while the "pad" oxide may be stripped using a wet or dry process. There is great impetus for replacing this complicated wet/dry process sequence with a dry method capable of removing the entire PBL stack. This replacement would have benefits not only from the viewpoint of process clusterability, but also from the elimination of hot phosphoric acid from the process sequence. Hot phosphoric acid poses a safety and environmental hazard, is difficult to handle, and is typically one of the most contaminated chemicals in the fabricating laboratory.

In general, a dry LOCOS isolation stack removal process would be required to rapidly etch silicon nitride (and polysilicon), while achieving a selectivity, for silicon nitride over silicon oxide, of greater than 15. The latter requirement limits the removal of field oxide during the nitride stripping process, and prevents thinning or punch through of the pad oxide during an over etch condition.

Dry processes which have been evaluated for nitride LOCOS mask stripping applications include plasma etching, plasma downstream etching, and plasmaless etching of silicon nitride using fluorine interhalogen and other spontaneously reactive gases.

Akiya, Proc. of Dry. Proc. Symp., Oct. 1981, Tokyo, p 19, demonstrated in a plasma beam experiment that F atoms produced in an upstream CF4 --O2 RF discharge spontaneously etch silicon nitride (Si3 N4) at appreciable rates, while thermal SiO2 and PSG (phosphorous doped silica glass) were etched much more slowly.

Sanders et al., J. Electrochem. Soc., 129(11), 1982, p 2559, studied the selective isotropic dry etching of Si3 N4 over SiO2 using CF4 --O2 mixtures in a commercial barrel etcher, and found that additions of CF3 Br increased selectivity for the nitride from 5 to over 20. They further suggested that there was an increasing effect on nitride selectivity as one added other halogens to the base fluorine chemistry, in the order of chlorine, bromine, iodine.

Suto et al. J. Electrochem. Soc. 136(7), 1989, p 2032, studied Si3 N4 to SiO2 selectivity in a downstream microwave plasma process, where additions of Cl2 to a NF3 discharge chemistry were found to greatly enhance nitride selectivity.

Lowenstein, et al., J. Vac. Sci. Technol. A, 7(3), 1989, p 686; J. Electrochem. Soc., 138(5), 1991, p 1389; and Proc. of ECS, 93(21), 1993, p 373, have characterized the etching of LOCOS isolation structures in a microwave-based remote plasma reactor. In these references, the effect of substrate temperature, as well as hydrogen additions on the etching selectivity of silicon nitride to thermal SiO2 and polysilicon, have been detailed and the removal of silicon oxynitride in a similar dry process was also compared to conventional wet hot phosphoric acid process. All of these references, however, pertain to plasma etch systems. Direct plasma etch systems are generally unacceptable due to various types of charge and ballistic damages which are created in the active device regions. Downstream plasma systems for dry stripping of silicon nitride which expose the substrate to plasma effluent, rather than to the plasma glow region, have disadvantages which include the deposition of sputtered contaminants in the plasma tube onto the wafer, the strong effect of transport tube material and geometry on the wafer chemistry, the exposure of the wafer to residual charge flux and long lived high energy metastables, and process sensitivity to reactor conditioning effects. Accordingly there is a need for a dry plasma-free process for stripping silicon nitride from wafer substrates.

Ibbotson et al., Appl. Phys. Lett., 46(10), 1984 p 2939, demonstrated that plasma deposited silicon nitride and LPCVD Si3 N4 could be etched at an appreciable rate in a plasma-free process using only vapors of chlorine trifluoride (ClF3), while thermal SiO2 was not etched at detectable rates.

Saito et al., IEICE Trans. Electron, E75-C(7), July 1992, p834, have further studied the "plasmaless etching" of thermally grown, sputtered, and plasma deposited silicon nitride films with ClF3 vapors. Low intensity UV exposure of thermal silicon nitride during ClF3 etching was found to reduce the induction time before the onset of etching, and to increase ClF3 --Si3 N4 etching rates by about a factor of 2. Under the conditions studied, selectivity of Si3 N4 was reported to be greater than 100, however, the nitride etching rates reported were under 5 Å/min.

In copending application Ser. No. 08/259,542, filed Jun. 14, 1994, it is disclosed that selectivity between various forms of silicon oxide is reduced to a factor of near 1:1 when a substrate containing several types of silicon oxide is exposed to a plasma-free gaseous environment comprising a photodisassociable fluorine containing gas and irradiated with UV.

The current invention is a dry process for removing a film of silicon nitride from a substrate. The process can achieve removal at rates in excess of 100 Å/minute, and in some cases over 500 Å/minute. This result is preferably achieved in the absence of a plasma or plasma effluent which simplifies the process and minimizes damage to the wafer and underlying material. The invention also allows removal of a film of silicon nitride in the presence of silicon oxide while minimizing the removal of the silicon oxide. Specific application of this process may be in the stripping of the silicon nitride mask following a LOCOS or a poly-buffered-LOCOS (PBL) process.

The invention provides several advantages over the use of hot phosphoric acid. First, hot phosphoric acid is a safety hazard due to the presence of large quantities of highly reactive, hot liquid. This invention uses only dry gases as the reactive species. Second, phosphoric acid is one of the dirtiest chemicals in the industry. The invention uses gases that can be readily obtained at very high purity levels. Third, the hot phosphoric process generates and deposits particles on wafers. This invention is, at worst, particle neutral. Fourth, phosphate waste from the hot phosphoric acid process is a major pollutant. The waste generated from the scrubbing of the gaseous exhaust from this invention is only a small fraction of the waste generated from the hot phosphoric process. Thus the invention overcomes the limitations of the current hot phosphoric acid stripping of silicon nitride LOCOS films, while maintaining high selectivity against the underlying pad oxide.

Other applications exist where it is desirable to strip silicon nitride film in the manufacturing of semiconductor devices. The present invention may also be employed to strip silicon nitride in such applications. In particular, the high selectivity for silicon nitride over silicon oxide can be readily exploited in circumstances where different forms of silicon oxide are present and are desirably retained relative to silicon nitride. The different forms of silicon oxide may include CVD oxide, thermal oxide and doped oxides such as boron and phosphorus doped silica glass (BPSG), phosphorous doped silica glass (PSG), boron doped silica glass (BSG), and spin on glass (SOG).

The invention, in one aspect, is a method of removing silicon nitride from a substrate, the method comprising:

placing the substrate in a gaseous environment comprising at least one first gas and at least one second gas, the first gas being a fluorine-containing gas which can be photodissociated by UV radiation to produce atomic fluorine and the second gas being a chlorine-containing or a bromine containing gas which can be photodissociated by UV radiation to produce atomic chlorine or bromine, and

exposing the substrate to UV irradiation in the presence of the gaseous environment. Examples of suitable fluorine containing gases are fluorine, fluorine interhalogens, especially ClF3, fluorides of sulfur and xenon difluoride.

In a further aspect the invention is a method of removing silicon nitride from a substrate, the method comprising:

placing the substrate in a gaseous environment comprising at least one first gas, the first gas being a fluorine-containing gas which can be photodissociated by UV radiation to produce atomic fluorine, and

exposing the substrate to UV irradiation in the presence of the gaseous environment,

wherein the integrated intensity of the UV irradiation at the substrate surface over the range of 180-400 nm is at least 50 mW/cm2, the temperature of the substrate before irradiation is in the range of 20° -400°C, and the partial pressure of said first gas is at least 10 torr.

FIG. 1 is a schematic cross section of a silicon wafer having a PBL stack to be removed.

FIG. 2 is a graph of UV-enhanced ClF3 etching rates for Si3 N4, thermal oxide, and BPSG at low (50°C) initial wafer temperature.

FIG. 3 is a graph of UV-enhanced ClF3 etching rates for Si3 N4, thermal oxide, and BPSG at high (150°C) initial wafer temperature level.

FIG. 4 is a graph showing the effect of Cl2 additions on silicon nitride-to-thermal oxide etching rate selectivity in UV/ClF3 etching at a constant 0.25 ClF3 fraction and 100°C initial wafer temperature.

FIG. 5 is a graph showing the effect of Cl2 additions on silicon nitride-to-thermal oxide etching rate selectivity in UV/ClF3 etching at a constant 500 sccm ClF3 flow and 150°C initial wafer temperature.

FIG. 6 is a graph comparing UV/F2 and UV/F2 +Cl2 etching of Si3 N4, thermal oxide, and BPSG films.

FIG. 7 is a graph showing comparison of UV/ClF3 and UV/ClF3 +Cl2 etching with an ozone generating versus and ozone free medium pressure mercury are lamp.

The process of the invention is achieved by simultaneously exposing the wafer surface to ultraviolet (UV) illumination and a gaseous environment containing a fluorine containing gas which is photolysable by UV, such as chlorine trifiuoride (ClF3) or F2. In a preferred embodiment a second, a chlorine-containing or a bromine-containing gas which can be photodissociated by UV radiation to produce atomic chlorine or bromine, is also employed in the gaseous environment. Typical conditions include a total gas pressure of 100 torr, total flow rate of 1000 sccm, ClF3 fraction of 1% to 90%, Cl2 fraction of 1% to 50% and a starting temperature of 40°C UV irradiation may be provided with a medium pressure mercury vapor discharge lamp.

For purposes of this invention, UV radiation is actinic radiation in the range of 180-400 nm.

In practice of the inventive method, a source of the fluorine-containing gas is connected to a processing chamber containing the substrate material to be etched or cleaned. The processing chamber suitably comprises a vacuum vessel constructed of chemically inert material, which is hermetically sealed from the ambient atmosphere and can be evacuated to better than 20 millitorr base pressure by means of suitable vacuum apparatus. The processing chamber is evacuated to a low base pressure, for example 20 millitorr. The substrate is desirably introduced into the processing chamber through an isolated load-lock chamber which can be pumped down to a similar base pressure. Introduction or removal of the substrate from the process chamber occurs through the load-lock chamber to prevent the introduction of atmospheric contaminants, particularly water vapor, into the process chamber. Alternatively, the substrate may be introduced into the chamber before evacuation.

The process chamber may also share a transfer interface with a vacuum cluster robotic transfer unit which allows sequential transfer of substrate materials to or from other process modules without exposure to ambient atmosphere.

A fluorine-containing gas such as ClF3 is introduced into the process chamber to produce a gaseous environment in which the fluorine containing gas forms a substantial partial pressure over the substrate, suitably in the range of 10-760 torr. Preferably the fluorine containing gas is introduced at a partial pressure of at least 20 torr, more preferably about 50 torr or greater. Suitable fluorine containing gases usable in the invention include, in addition to ClF3, other fluorine interhalogens such as bromine trifluoride, bromine pentafluoride, and iodine pentafluoride, and also fluorine, sulfur hexafluoride and xenon difluoride. Fluorine containing gases which are not readily photodissociated by UV radiation, such as NF3, are not suitable for use as the fluorine containing gas.

In one embodiment a second gas which provides a source of atomic chlorine or bromine by photodissociation, for instance chlorine, bromine, CCl4, chlorofluorocarbons such as CF3 Cl and bromofluorocarbons such as CF3 Br, is also introduced into the process chamber. Preferred second gases are chlorine and bromine, with chlorine most preferred. The second gas can be employed at a partial pressure in the range of 1 mtorr-760 torr. Preferably the ratio of the partial pressures of the fluorine-containing gas and the second gas is from 2:1-1:2. A preferred gas mixture is a mixture of ClF3 and Cl2 at partial pressures of about 50 torr each.

An inert gas or mixture of inert gases may also be introduced into the chamber. The inert gas may be any gas which is inert to the materials to be treated and which will remain in the gaseous phase under the processing conditions present. Suitable inert gases include nitrogen, argon, and helium.

The process preferably is conducted in the substantial absence of a plasma or plasma products, such as a downstream plasma effluent. That is, the gases of the gaseous environment are preferably introduced to the reaction vessel in their atomic ground state. However, the use of a photolyzable fluorine containing gas in the gaseous environment under the conditions described herein also provides advantages in achieving silicon nitride etching when the gaseous environment includes plasma products from an upstream plasma generator. For instance, the fluorine containing gas and/or the chlorine or bromine containing gas may be excited with an upstream plasma generating source such as a radio frequency source or a microwave source in an apparatus as described in U.S. Pat. No. 4,741,800 or U.S. Pat. No. 4,687,544.

For safety reasons, the total gas pressure is desirably maintained at or below atmospheric pressure.

The fluorine containing gas or gas mixture may be introduced into the processing chamber in a manner which creates a uniform radial laminar flow pattern over the substrate, for instance through a gas distribution showerhead. In this manner removal of etching products and contaminants is facilitated through entrainment in the laminar flow stream. However, the present invention may be accomplished using other reactive gas flow patterns or in an approximately stagnant gaseous environment.

Both the fluorine-containing gas phase above the substrate and the substrate surface to be processed are illuminated with UV light, suitably through a UV transparent window in the processing chamber. Broadband UV radiation in the wavelength range of 180-600 nm may be used, as may narrower band sources providing substantial output in the 180-420 nm range. Suitable sources are medium pressure Hg lamps and xenon flash lamps. The UV radiation may be pulsed or continuous. Ozone-free UV sources providing little or no output in the 180-239 nm range may also be suitably employed. A laser and suitable optics may also be used to generate the required UV photon flux. Silicon nitride removal rates may be controlled to a large degree by the intensity of the UV radiation, the UV photon energy, the UV exposure time and/or the UV lamp or laser pulsing rate.

The intensity of the UV irradiation over the range of 180-400 nm is desirably at least 50 mW/cm2, preferably at least 200 mW/cm2. A typical broadband UV source useful in the invention will provide an integrated intensity over the 180-400 nm range of about 250 mW/cm2 with a intensity at 254±5 nm of about 25 mW/cm2. An ozone free source providing at least 50 mW/cm2, preferably at least 200 mW/cm2 in the range of 240-400 nm can be used and provide important safety advantages over ozone generating sources. For purposes of this invention UV irradiation intensities are determined at the substrate surface.

The temperature of the substrate before onset of irradiation is desirably in the range of 20-400°C, more preferably at least 150° C., and no more than 250°C

Following treatment, the processing chamber is evacuated and the substrate is removed.

As noted above one particular application of the process of the invention is in the removal of silicon nitride mask following a LOCOS or a PBL process. Referring to FIG. 1, there is shown a silicon wafer substrate 10 on which a PBL stack has been built. The PBL stack consists of successive layers of "pad" silicon oxide 12, typically 100 Å thick, polysilicon 14, typically 500 Å thick, and a layer of silicon nitride 16, typically 2500 Å thick. After the PBL stack is built it is masked, etched, and then "field oxide" layer 18 built up in the unmasked etched areas. The field oxide build up step produces a thin silicon oxynitride layer 20 at the top of the PBL stack. Following the buildup of layer 18, the PBL stack is removed down to the pad oxide layer. That is, layers 20, 16 and 14 are removed. The process of the present accomplishes that removal efficiently.

The invention is illustrated by the following non-limiting examples.

Examples

The reactor used in these studies was a prototype single wafer vacuum cluster module capable of conducting UV-enhanced processing of 100, 150, or 200 mm wafers, and interfaced to a vacuum cluster robotic handler. The reactor module was constructed of 6061 aluminum, which has undergone a hard coating process rendering it impervious to attack by HF and HCl vapors, as well as halogen radicals. For the purpose of these studies a dry rough pump was used to pump the vacuum reactor to base pressure below 10 mtorr. High purity sapphire windows were used to allow UV (and/or IR) light exposure of the wafer front side, the sapphire material also being impervious to attack by process chemistries. Gases were introduced over the wafer in a radial laminar flow pattern, enhancing the transport of etching products and particulates away from the wafer surface. High intensity (10-50 mw/cm2 at 254 nm), broad band UV radiation was generated for the purpose of these studies using commercially available medium pressure mercury discharge ozone producing and ozone-free lamps. The high energy cutoff for the ozone-free lamp is at about 245 nm, while the cut off for the ozone producing lamp is at about 180 nm. Unless otherwise noted, data presented in this study was taken using the ozone-producing lamp.

The wafer pre-process temperature was controlled using a proximity heater, typically in the range of 50° to 150°C During the period of UV exposure, typically 30 to 60 seconds, the wafer temperatures were transient due to IR output from the UV lamps. However, the wafer temperature typically did not exceed 300°C during processing.

Gases used in this study included Air Products C. P. Grade (99.0%) ClF3 and Scientific Gas Products VLSI grade Cl2 (99.998%). Dry nitrogen used in these studies was from an LN2 vapor delivery system, and typically had below 10 ppm H2 O impurity. 2000 Å LPCVD silicon nitride (Si3 N4) films were prepared over a 200 Å pad of thermal oxide for nitride etching studies. 5000 Å BPSG (3% B/3% P) films and 4000 Å steam growth thermal oxide were used for oxide etching selectivity studies. All work presented herein was conducted on 150 mm p-Si<100> substrate wafers. Film thicknesses preceding and following etching process were measured optically.

The rate of etching Si3 N4 is compared to that for thermal silicon oxide and densified BPSG at high ClF3 flow fractions and two different levels of temperature in FIGS. 2 and 3. Total flow in these studies was held at 1000 sccm using dry nitrogen as a diluent, while total reactor pressure was held at 100 torr. Computational and experimental studies have shown that these conditions lead to uniform gas distribution over a 150 mm wafer in the present reactor configuration. Preceding the dry strip processes, all wafers were subjected to a standardized cleaning procedure to establish a consistent pre-etch state for the substrate surfaces. The wafer carrier was then inserted into a vacuum cluster robot elevator which was evacuated to below 10 mtorr. Wafers were inserted into the process module by the handler under vacuum. The flow of gaseous reactants to the module was started about 30 seconds prior to starting UV exposure to allow the reactor pressure to stabilize at 100 torr. Wafers were exposed to UV light for 1-5 minutes, depending on the film being etched and experimental conditions, after which the UV exposure was stopped and the reaction chamber was pumped to base pressure and purged with dry nitrogen.

Silicon nitride and silicon oxide UV/ClF3 etching rates are compared for ClF3 flow fractions of 0.5, 0.75, and 0.9 in FIG. 2, where the initial substrate temperature was 50°C Silicon nitride etching rates were found to increase with flow fraction from 160 to 200 Å/min in these low temperature studies, while etching of the doped and undoped oxides was typically under 10 Å/min. Etching selectivity exceeded 20 for the highest ClF3 flow fraction. However, under these conditions the nitride etching rates were impractically low.

Increasing the substrate starting temperature to 150°C (FIG. 3) increased both the Si3 N4 and silicon oxide etching rates substantially, indicating a positive activation energy in both cases. However, the results of FIG. 3 indicate that temperature has a disproportionate effect in increasing silicon oxide etching rates so that UV/ClF3 SiO2 etching is more strongly thermally activated. Consequently, while Si3 N4 etching rates reach 800 Å/min at this temperature, nitride-to-oxide selectivity falls to about 8-to-1.

The results of Example 1 indicate that it is possible to greatly enhance Si3 N4 etching rates by increasing substrate temperature, UV intensity, and/or ClF3 concentration, but typically at the expense of etching selectivity to thermal oxide. This example demonstrates the UV-enhanced process chemistry of the invention which achieves both high Si3 N4 etching rates and high selectivity.

Wafers were processed as in the previous example except that ClF3 flow rate was 250 sccm, the initial temperature was 100°C, pressure was 100 torr and chlorine gas was introduced at rates as shown in FIG. 4. Under these conditions improvements in selectivity from 4:1 with no Cl2, to 10:1 with a Cl2 /ClF3 ratio of 2 were obtained. Neither Si3 N4 or SiO2 were measured at substantial rates with UV/Cl2 only.

The effect of Cl2 additions at ClF3 flow rate of 500 sccm and initial wafer temperature of 150°C is presented in FIG. 5. The total flow rate was held at 1000 sccm with the remainder of the flow being made up by N2, with the exception of the run at the 1.5:1 Cl2 to ClF3 ratio in which a total flow of 1250 sccm was used. For the chlorine only process 500 sccm chlorine was flowed with 500 sccm nitrogen. Additions of 25% chlorine were found to increase nitride-to-oxide etching selectivity to over 20, and silicon oxide etching was nearly completely suppressed. This allows extensive over-etching of the nitride films without breakthrough of the pad oxide layer. Under conditions in which no nitrogen diluent was present (500 sccm ClF3, 500 sccm Cl2), an etching selectivity ratio of 90:1 was measured.

The data presented in FIGS. 4 and 5 suggest that the mechanism for Cl2 suppression depends on the photolytic production efficiency for Cl atoms and consequently it is believed that bromine additions will have a qualitatively similar effect.

Similar etching results to those obtained in Example 2 may be achieved using F2, which is efficiently photo dissociated by 200-400 nm light or other fluorine-bearing gases which are efficiently photo dissociated in the UV. FIG. 6 shows results of UV/F2 and UV/F2 +Cl2 etching of Si3 N4 as well as undoped silicon oxide. Conditions were 100 torr pressure, 100°C initial wafer temperature, 500 sccm F2, 500 sccm N2 for UV/F2 and 500 sccm F2, 500 sccm Cl2 for UV/F2 +Cl2. UV/F2 was found to etch all films at rates greater than UV/ClF3 at similar temperatures and flow rates. The addition of Cl2, however, was again found to nearly completely suppress the etching of silicon oxide, resulting in a highly selective etching process for Si3 N4.

Shown in FIG. 7 is the effect of using an ozone producing (180-400 nm) versus an ozone free (240-400 nm) UV lamp on the UV/ClF3 etching of Si3 N4. Conditions were 100 torr pressure, 150°C initial wafer temperature. The first gas mixture was 500 sccm ClF3, 500 sccm N2 and the second gas mixture was 500 sccm ClF3, 750 sccm Cl2. No significant reduction in etching rate was noted in the silicon nitride etch rate when using the ozone free lamp. Consequently, for purposes of this invention, ozone-free UV sources, which provide an integrated intensity at the substrate surface over the range of 240-400 nm of at least 50 mW/cm2, more preferably at least 200 mW/cm2, are considered suitable. This has particular advantage in commercial processes where worker safety and health are important.

Gray, David C., Butterbaugh, Jeffery W.

Patent Priority Assignee Title
11049729, Mar 28 2017 Central Glass Company, Limited Dry etching method, semiconductor device manufacturing method, and chamber cleaning method
5726480, Jan 27 1995 CALIFORNIA, UNIVERSITY OF THE REGENTS, THE Etchants for use in micromachining of CMOS Microaccelerometers and microelectromechanical devices and method of making the same
5786242, Nov 25 1994 SEMICONDUCTOR ENERGY LABORATORY CO , LTD Method of manufacturing SOI semiconductor integrated circuit
5814156, Sep 08 1993 Novellus Systems, Inc Photoreactive surface cleaning
5912186, Nov 21 1995 AIR WATER, INC Method for processing semiconductor material
5922219, Oct 31 1996 FSI International, Inc. UV/halogen treatment for dry oxide etching
6083413, Oct 19 1995 Massachusetts Institute of Technology Metals removal process
6120697, Dec 31 1997 AlliedSignal Inc Method of etching using hydrofluorocarbon compounds
6207553, Jan 26 1999 GLOBALFOUNDRIES Inc Method of forming multiple levels of patterned metallization
6284006, Nov 15 1999 FSI International, Inc Processing apparatus for microelectronic devices in which polymeric bellows are used to help accomplish substrate transport inside of the apparatus
6290864, Oct 26 1999 Texas Instruments Incorporated Fluoride gas etching of silicon with improved selectivity
6402957, Oct 15 1999 SEH America, Inc. Bromine biocide removal
6428716, Dec 31 1997 AlliedSignal Inc. Method of etching using hydrofluorocarbon compounds
6429083, Sep 24 1999 Advanced Micro Devices, Inc. Removable spacer technology using ion implantation to augment etch rate differences of spacer materials
6451713, Apr 17 2000 MATTSON TECHNOLOGY, INC UV pretreatment process for ultra-thin oxynitride formation
6500356, Mar 27 2000 Applied Materials, Inc. Selectively etching silicon using fluorine without plasma
6569775, Mar 30 1999 Applied Materials, Inc Method for enhancing plasma processing performance
6576151, Sep 10 1999 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM IMEC Etching of silicon nitride by anhydrous halogen gas
6586324, Oct 26 2001 Nanya Technology Corporation Method of forming interconnects
6635185, Dec 31 1997 AlliedSignal Inc Method of etching and cleaning using fluorinated carbonyl compounds
6649065, Oct 15 1999 SEH America, Inc. Bromine biocide removal
6707591, Apr 10 2001 Silicon Light Machines Corporation Angled illumination for a single order light modulator based projection system
6712480, Sep 27 2002 Silicon Light Machines Corporation Controlled curvature of stressed micro-structures
6714337, Jun 28 2002 Silicon Light Machines Corporation Method and device for modulating a light beam and having an improved gamma response
6728023, May 28 2002 Silicon Light Machines Corporation Optical device arrays with optimized image resolution
6747781, Jun 25 2001 Silicon Light Machines Corporation Method, apparatus, and diffuser for reducing laser speckle
6764875, Jul 29 1998 Silicon Light Machines Corporation Method of and apparatus for sealing an hermetic lid to a semiconductor die
6767751, May 28 2002 Silicon Light Machines Corporation Integrated driver process flow
6773683, Jan 08 2001 UVTECH SYSTEMS, INC Photocatalytic reactor system for treating flue effluents
6782205, Jun 25 2001 Silicon Light Machines Corporation Method and apparatus for dynamic equalization in wavelength division multiplexing
6800238, Jan 15 2002 Silicon Light Machines Corporation Method for domain patterning in low coercive field ferroelectrics
6801354, Aug 20 2002 Silicon Light Machines Corporation 2-D diffraction grating for substantially eliminating polarization dependent losses
6806997, Feb 28 2003 Silicon Light Machines Corporation Patterned diffractive light modulator ribbon for PDL reduction
6813059, Jun 28 2002 Silicon Light Machines Corporation Reduced formation of asperities in contact micro-structures
6822797, May 31 2002 Silicon Light Machines Corporation Light modulator structure for producing high-contrast operation using zero-order light
6829077, Feb 28 2003 Silicon Light Machines Corporation Diffractive light modulator with dynamically rotatable diffraction plane
6829092, Aug 15 2001 Silicon Light Machines Corporation Blazed grating light valve
6829258, Jun 26 2002 Silicon Light Machines Corporation Rapidly tunable external cavity laser
6835616, Jan 29 2002 MONTEREY RESEARCH, LLC Method of forming a floating metal structure in an integrated circuit
6843258, Dec 19 2000 Applied Materials, Inc. On-site cleaning gas generation for process chamber cleaning
6865346, Jun 05 2001 Silicon Light Machines Corporation Fiber optic transceiver
6872984, Jul 29 1998 Silicon Light Machines Corporation Method of sealing a hermetic lid to a semiconductor die at an angle
6880561, Mar 27 2000 Applied Materials, Inc. Fluorine process for cleaning semiconductor process chamber
6908201, Jun 28 2002 Silicon Light Machines Corporation Micro-support structures
6922272, Feb 14 2003 Silicon Light Machines Corporation Method and apparatus for leveling thermal stress variations in multi-layer MEMS devices
6922273, Feb 28 2003 Silicon Light Machines Corporation PDL mitigation structure for diffractive MEMS and gratings
6927891, Dec 23 2002 Silicon Light Machines Corporation Tilt-able grating plane for improved crosstalk in 1×N blaze switches
6928207, Dec 12 2002 Silicon Light Machines Corporation Apparatus for selectively blocking WDM channels
6930364, Sep 13 2001 Silicon Light Machines Corporation Microelectronic mechanical system and methods
6934070, Dec 18 2002 Silicon Light Machines Corporation Chirped optical MEM device
6947613, Feb 11 2003 Silicon Light Machines Corporation Wavelength selective switch and equalizer
6949202, Oct 26 1999 Texas Instruments Incorporated Apparatus and method for flow of process gas in an ultra-clean environment
6956878, Feb 07 2000 Silicon Light Machines Corporation Method and apparatus for reducing laser speckle using polarization averaging
6956995, Nov 09 2001 Silicon Light Machines Corporation Optical communication arrangement
6965468, Jul 03 2003 Texas Instruments Incorporated Micromirror array having reduced gap between adjacent micromirrors of the micromirror array
6970281, Jul 03 2003 Texas Instruments Incorporated Micromirror array having reduced gap between adjacent micromirrors of the micromirror array
6981508, Dec 19 2000 Applied Materials, Inc. On-site cleaning gas generation for process chamber cleaning
6985277, Jul 03 2003 Texas Instruments Incorporated Micromirror array having reduced gap between adjacent micromirrors of the micromirror array
6987600, Dec 17 2002 Silicon Light Machines Corporation Arbitrary phase profile for better equalization in dynamic gain equalizer
7026235, Feb 07 2002 Infineon Technologies LLC Dual-damascene process and associated floating metal structures
7027202, Feb 28 2003 Silicon Light Machines Corporation Silicon substrate as a light modulator sacrificial layer
7041224, Oct 26 1999 Texas Instruments Incorporated Method for vapor phase etching of silicon
7042611, Mar 03 2003 Silicon Light Machines Corporation Pre-deflected bias ribbons
7049164, Sep 13 2001 Silicon Light Machines Corporation Microelectronic mechanical system and methods
7054515, May 30 2002 Silicon Light Machines Corporation Diffractive light modulator-based dynamic equalizer with integrated spectral monitor
7057795, Aug 20 2002 Silicon Light Machines Corporation Micro-structures with individually addressable ribbon pairs
7057819, Dec 17 2002 Silicon Light Machines Corporation High contrast tilting ribbon blazed grating
7068372, Jan 28 2003 Silicon Light Machines Corporation MEMS interferometer-based reconfigurable optical add-and-drop multiplexor
7153443, Mar 28 2003 Texas Instruments Incorporated Microelectromechanical structure and a method for making the same
7177081, Mar 08 2001 Silicon Light Machines Corporation High contrast grating light valve type device
7189332, Sep 17 2001 Texas Instruments Incorporated Apparatus and method for detecting an endpoint in a vapor phase etch
7227212, Jan 29 2002 MONTEREY RESEARCH, LLC Method of forming a floating metal structure in an integrated circuit
7270724, Dec 13 2000 Novellus Systems, Inc Scanning plasma reactor
7286764, Feb 03 2003 Silicon Light Machines Corporation Reconfigurable modulator-based optical add-and-drop multiplexer
7391973, Feb 28 2003 Silicon Light Machines Corporation Two-stage gain equalizer
7645704, Sep 17 2003 Texas Instruments Incorporated Methods and apparatus of etch process control in fabrications of microstructures
8492736, Jun 09 2010 Lam Research Corporation Ozone plenum as UV shutter or tunable UV filter for cleaning semiconductor substrates
8536061, Aug 05 2010 Kioxia Corporation Semiconductor device manufacturing method
8584612, Dec 17 2009 Lam Research Corporation UV lamp assembly of degas chamber having rotary shutters
8603292, Oct 28 2009 Lam Research Corporation Quartz window for a degas chamber
8624210, Jun 09 2010 Lam Research Corporation Ozone plenum as UV shutter or tunable UV filter for cleaning semiconductor substrates
9997325, Jul 17 2008 VERITY INSTRUMENTS, INC Electron beam exciter for use in chemical analysis in processing systems
Patent Priority Assignee Title
2841477,
3122463,
3669774,
4065369, Jul 18 1975 Tokyo Shibaura Electric Co., Ltd. Activated gas reaction apparatus & method
4160690, Mar 31 1977 Tokyo Shibaura Electric Co., Ltd. Gas etching method and apparatus
4175235, Aug 31 1976 Tokyo Shibaura Electric Co., Ltd. Apparatus for the plasma treatment of semiconductors
4183306, Oct 08 1976 Kureha Kagaku Kogyo Kabushiki Kaisha Hot gas recirculation type burning furnace
4183780, Aug 21 1978 International Business Machines Corporation Photon enhanced reactive ion etching
4314875, May 13 1980 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching
4498953, Jul 27 1983 AT&T Bell Laboratories Etching techniques
4522674, Jan 24 1983 Hitachi, Ltd. Surface treatment apparatus
4540466, May 11 1983 Semiconductor Research Foundation Method of fabricating semiconductor device by dry process utilizing photochemical reaction, and apparatus therefor
4643799, Dec 26 1984 Hitachi, Ltd. Method of dry etching
4678536, Nov 21 1984 Hitachi, Ltd. Method of photochemical surface treatment
4687544, May 17 1985 NIHON SHINKU GIJUTSU, K K Method and apparatus for dry processing of substrates
4741800, Jan 28 1985 SEMICONDUCTOR ENERGY LABORATORY CO , LTD , A CORP OF JAPAN Etching method for the manufacture of a semiconductor integrated circuit
4749440, Aug 28 1985 FSI International, Inc Gaseous process and apparatus for removing films from substrates
4857140, Jul 16 1987 Texas Instruments Incorporated Method for etching silicon nitride
4871416, Nov 19 1987 Oki Electric Industry Co., Ltd. Method and device for cleaning substrates
4938815, Oct 15 1986 AIXTRON, INC Semiconductor substrate heater and reactor process and apparatus
5022961, Jul 26 1989 DAINIPPON SCREEN MANUFACTURING CO , LTD Method for removing a film on a silicon layer surface
5028560, Jun 21 1988 Mitsubishi Denki Kabushiki Kaisha Method for forming a thin layer on a semiconductor substrate
5030319, Dec 27 1988 Kabushiki Kaisha Toshiba Method of oxide etching with condensed plasma reaction product
5068040, Apr 03 1989 Raytheon Company Dense phase gas photochemical process for substrate treatment
5178682, Mar 01 1989 Mitsubishi Denki Kabushiki Kaisha Method for forming a thin layer on a semiconductor substrate and apparatus therefor
5183531, Aug 11 1989 Sanyo Electric Co., Ltd. Dry etching method
5201994, Nov 18 1988 Kabushiki Kaisha Shibaura Seisakusho Dry etching method
5221423, May 20 1986 Fujitsu Limited Process for cleaning surface of semiconductor substrate
5228206, Jan 15 1992 PRIMAXX, INC Cluster tool dry cleaning system
5234540, Apr 30 1992 Akrion Systems LLC Process for etching oxide films in a sealed photochemical reactor
5236602, Apr 03 1989 Raytheon Company Dense fluid photochemical process for liquid substrate treatment
5254176, Feb 03 1992 Tokyo Electron Limited; Iwatani International Corporation Method of cleaning a process tube
5431772, May 09 1991 International Business Machines Corporation Selective silicon nitride plasma etching process
5437765, Apr 29 1994 Texas Instruments Incorporated Semiconductor processing
EP63273,
GB1180187,
JP57200569,
WO9103075,
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Aug 17 1994GRAY, DAVID C FSI InternationalASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0071400868 pdf
Aug 17 1994BUTTERBAUGH, JEFFREY W FSI InternationalASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0071400868 pdf
Aug 18 1994FSI International(assignment on the face of the patent)
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