A dc-offset canceler circuit is provided, which cancels a dc offset more effectively. This circuit includes a first differential pair of emitter-coupled first and second bipolar transistors driven by a first constant current source/sink, and a second differential pair of emitter-coupled third and fourth bipolar transistors driven by a second constant current source/sink. The first and second differential pairs are coupled by a coupling capacitor. An emitter of a fifth bipolar transistor is connected to the emitters of the first and second transistors. An emitter of a sixth bipolar transistor is connected to the emitters of the third and fourth transistors. bases of the first and fifth transistors are connected to a first input terminal. A base of the second transistor is connected to the first input terminal through a first resistor. bases of the fourth and sixth transistors are connected to a second input terminal. A base of the third transistor is connected to the second input terminal through a second resistor. Collectors of the first, third, and sixth transistors are connected to a first output terminal, and those of the second, fourth, and fifth transistors are connected to a second output terminal.
|
1. A dc-offset canceler circuit comprising:
(a) a first differential pair of first and second bipolar transistors whose emitters are coupled together; (b) a first constant current source/sink supplying/sinking a first constant current to/from said first differential pair; (c) a second differential pair of third and fourth bipolar transistors whose emitters are coupled together; (d) a second constant current source/sink supplying/sinking a second constant current to/from said second differential pair; (e) a fifth bipolar transistor having an emitter connected to said emitters of said first and second transistors; (f) a sixth bipolar transistor having an emitter connected to said emitters of said third and fourth transistors; and (g) an ac-coupling element for ac-coupling said first and second differential pairs together; wherein bases of said first and fifth transistors are connected to a first input terminal, and a base of said second transistor is connected to a first end of said coupling element; and wherein bases of said fourth and sixth transistors are connected to a second input terminal, and a base of said third transistor is connected to a second end of said coupling element; and wherein collectors of said first, third, and sixth transistors are connected to a first output terminal, and collectors of said second, fourth, and fifth transistors are connected to a second output terminal; and wherein a dc offset generated at said first and second input terminals is canceled at said first and second output terminals.
4. A differential amplifier circuit comprising:
(a) a differential amplifier subcircuit for amplifying a differential input signal to differentially generate first and second outputs; and (b) a dc-offset canceler subcircuit for canceling a dc offset generated in said first and second outputs of said differential amplifier subcircuit; wherein said dc-offset canceler subcircuit includes; (c-1) a first differential pair of first and second bipolar transistors whose emitters are coupled together; (c-2) a first constant current source/sink supplying/sinking a first constant current to/from said first differential pair; (c-3) a second differential pair of third and fourth bipolar transistors whose emitters are coupled together; (c-4) a second constant current source/sink supplying/sinking a second constant current to/from said second differential pair; (c-5) a fifth bipolar transistor having an emitter connected to said emitters of said first and second transistors; (c-6) a sixth bipolar transistor having an emitter connected to said emitters of said third and fourth transistors; and (c-7) an ac-coupling element for ac-coupling said first and second differential pairs together; (c-8) bases of said first and fifth transistors being connected to a first input terminal, and a base of said second transistor being connected to a first end of said coupling element; (c-9) bases of said fourth and sixth transistors being connected to a second input terminal, and a base of said third transistor being connected to a second end of said coupling element; (c-10) collectors of said first, third, and sixth transistors being connected to a first output terminal, and collectors of said second, fourth, and fifth transistors being connected to a second output terminal; (c-11) a dc offset generated at said first and second input terminals being canceled at said first and second output terminals. 2. A circuit as claimed in
wherein one end of said first emitter resistor is connected to said bases of said first and fifth transistors and the other end thereof is connected to said base of said second transistor; and wherein one end of said second emitter resistor is connected to said bases of said fourth and sixth transistors and the other end thereof is connected to said base of said third transistor.
3. A circuit as claimed in
|
|||||||||||||||||||||||||||||||
1. Field of the Invention
The present invention relates to a dc-offset canceler circuit and a differential amplifier circuit and more particularly, to a dc-offset canceler circuit which is preferably used for an amplifier circuit amplifying a signal in a low-frequency region such as 1 kHz to 10 kHz (e.g., the baseband frequency region) in a portable telecommunication system such as a pager system, and a differential amplifier circuit equipped with the dc-offset canceler circuit.
2. Description of the Prior Art
In recent years, a direct conversion receiver has been popularly used as a portable radio receiver such as a pager instead of a conventional superheterodyne receiver.
A limiting amplifier circuit designed for a direct conversion receiver of a pager amplifies a signal in the baseband frequency region (typically, 1 kHz to 10 kHz). This limiting amplifier circuit has a configuration that a plurality of differential amplifier subcircuits are cascade-connected at a plurality of stages, in which the differential amplifier subcircuits located at two adjoining ones of the stages are directly coupled without coupling capacitors. This is due to the following reason.
The coupling capacitor needs to have a large capacitance for the signal in the baseband frequency region and as a result, this capacitor occupies a large area on an Integrated Circuit (IC) chip. Accordingly, the coupling configuration with the coupling capacitor having such the large capacitance is not suitable to ICs. On the other hand, the directly coupling configuration requires no coupling capacitor and therefore, no problem relating to the chip area will occur.
With the limiting amplifier circuit having the direct-coupling configuration, the "dc offset" generated in the differential amplifier subcircuits at the respective stages tends to cause some known problems. To solve the problems, various techniques have been studied and developed for a long time, an example of which is shown in FIG. 1.
FIG. 1 shows a conventional dc blocking amplifier circuit having a dc-offset canceling function, which is disclosed in the Japanese Non-Examined Patent Publication No. 2-305205 published in 1990.
As shown in FIG. 1, the conventional dc blocking amplifier circuit S300 includes a first differential amplifier subcircuit S100 and a second differential amplifier subcircuit S200, which are coupled together by an ac-coupling capacitor 113.
The first differential amplifier subcircuit S100 is comprised of an emitter-coupled pair of npn-type bipolar transistors 101 and 102. The coupled emitters of the transistors 101 and 102 are connected to one end of a constant current sink 111 sinking a constant current I101. The other end of the constant current sink 111 is connected to the ground.
A resistor 109 is connected to the bases of the transistors 101 and 102. The base of the transistor 101 is further connected to a first input terminal 114. The base of the transistor 102 is further connected to one end of the coupling capacitor 113.
The second differential amplifier subcircuit S200 is comprised of an emitter-coupled pair of npn-type bipolar transistors 103 and 104. The coupled emitters of the transistors 103 and 104 are connected to one end of a constant current sink 112 sinking a constant current I102. The other end of the constant current sink 112 is connected to the ground.
A resistor 110 is connected to the bases of the transistors 103 and 104. The base of the transistor 103 is further connected to the other end of the coupling capacitor 113. The base of the transistor 104 is further connected to a second input terminal 115.
First and second input voltages are differentially applied across the first and second input terminals 114 and 115, respectively.
Collectors of the transistors 101 and 103 are coupled together to be connected to an end of a load resistor 107. The other end of the load resistor 107 is applied with a power supply voltage VCC. The coupled collectors of the transistors 101 and 103 are further connected to a first output terminal 116.
Collectors of the transistors 102 and 104 are coupled together to be connected to one end of another load resistor 108. The other end of the load resistor 108 is applied with the power supply voltage VCC. The coupled collectors of the transistors 102 and 104 are further connected to a second output terminal 117.
First and second output voltages are differentially derived from the first and second output terminals 116 and 117, respectively.
The transistors 101, 102, 103, and 104 have a same emitter area.
Next, the operation of the conventional dc blocking amplifier circuit S300 in FIG. 1 is explained below.
First, base voltages of the transistors 101, 102, 103, and 104 with respect to a specific reference point (e.g. the ground) are defined as VB101, VB102, VB103, and VB104, respectively. Collector currents of the transistors 101, 102, 103, and 104 are defined as IC101, IC102, IC103, and IC104, respectively. First and second output currents flowing through the load resistor 107 and 108 are defined as IC113 and IC124, respectively.
Then, the following equations (1) and (2) are established.
IC113 =IC101 +IC103 ( 1)
IC124 =IC102 +IC104 ( 2)
The collector currents IC101, IC102, IC103, and IC104 of the transistors 101, 102, 103, and 104 are expressed as the following equations (3), (4), (5), and (6), respectively. ##EQU1##
In the equations (3), (4), (5), and (6), α is the dc common-base current gain factor of each transistor, k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron. Typically, the gain factor a is approximately equal to 1.
When the constant current I102 of the constant current sink 112 is equal to the constant current I101 of the constant current sink 111 (i.e., I101 =I102), and the difference between the base voltages VB104 and VB103 of the transistors 104 and 103 are equal to the difference between the base voltages VB101 and VB102 of the transistors 101 and 102 (i.e., VB101 -VB102 =VB104 -VB103), the first and second output currents IC113 and IC124 become equal to each other. If the load resistors 107 and 108 have a same resistance, the first and second output voltages will have a same dc level at the first and second output terminals 116 and 117.
If the dc voltage level of the first input voltage at the first input terminal 114 is higher than that of the second input voltage at the second input terminal 115 due to a dc offset, the base voltages VB101, VB102, VB104, and VB103 satisfy the relationships of
VB101 >VB102 and
VB104 <VB103.
In this case, the collector current IC101 increases by an increment and the collector current IC102 decreases by the same increment in the first differential amplifier subcircuit S100. At the same time, the collector current IC103 increases by an increment and the collector current IC104 decreases by the same increment in the second differential amplifier subcircuit S200. Therefore, the first output current IC113 is increased and the second output current IC124 is decreased.
Thus, the dc voltage level at the first output terminal 116 is lowered and that at the second output terminal 117 is raised, thereby canceling the dc-voltage level difference (i.e., the dc offset) at the first and second input terminals 114 and 115. This means that no dc offset is generated between the first and second output terminals 116 and 117 even if the dc offset exists between the first and second input terminals 114 and 115.
The dc voltage levels at the first and second output terminals 116 and 117 are determined by a specific dc bias voltage applied to the conventional dc blocking amplifier circuit S300.
The same explanation as above is applied to the case where the dc voltage level at the first input terminal 114 is lower than that at the second input terminal 115.
However, the conventional dc blocking amplifier S300 in FIG. 1 has the following problem.
If any difference is generated between the constant currents I101 and I102 of the constant current sinks 111 and 112 (i.e., I101 ≠I102) due to the dc-voltage level difference greater than a specific value at the first and second input terminals 114 and 115, there arises a problem that a dc offset tends to occur between the first and second output terminals 116 and 117. It was found by the inventor that this problem is caused by the fact that the transistors forming one of the constant current sinks 111 and 112 operate in the saturation region while those forming another one of the constant current sinks 111 and 112 operate in the active region, resulting in some difference between the constant currents I102 and I102.
The dc bias offset thus generated at the first and second output terminals 116 and 117 is amplified by a differential amplifier located at a next stage. Therefore, there arises a disadvantage that the gain of the amplifier at the next stage needs to be set as sufficiently low.
Because of this problem, the conventional dc blocking amplifier S300 in FIG. 1 is not suitable to a dc-offset canceler for the limiting amplifier of the above sort.
Additionally, the difference between the constant currents I101 and I102 of the constant current sinks 111 and 112 may occur due to any other cause such as the unbalance in device layout of the current sinks 111 and 112.
Accordingly, an object of the present invention is to provide a dc-offset canceler circuit that cancels a dc offset more effectively.
Another object of the present invention is to provide a dc-offset canceler circuit that suppresses a dc offset due to the current difference of constant current sources/sinks with a simple configuration.
Still another object of the present invention is to provide a dc-offset canceler circuit that is suitable to a limiting amplifier circuit including cascade-connected differential amplifier subcircuits.
A further object of the present invention is to provide a differential amplifier circuit that is preferably used as a limiting amplifier circuit including cascade-connected differential amplifier subcircuits.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a dc-offset canceler circuit is provided. This circuit is comprised of (a) a first differential pair of first and second bipolar transistors whose emitters are coupled together, (b) a first constant current source/sink supplying/sinking a first constant current to/from the first differential pair, (c) a second differential pair of third and fourth bipolar transistors whose emitters are coupled together, (d) a second constant current source/sink supplying/sinking a second constant current to/from the second differential pair, (e) a fifth bipolar transistor whose emitter is connected to the emitters of the first and second transistors, (f) a sixth bipolar transistor whose emitter is connected to the emitters of the third and fourth transistors, and (g) an ac-coupling element for ac-coupling the first and second differential pairs together.
Bases of the first and fifth transistors are connected to in common a first input terminal. A base of the second transistor is connected to a first end of the coupling element.
Bases of the fourth and sixth transistors are connected in common to a second input terminal. A base of the third transistor is connected to a second end of the coupling element.
Collectors of the first, third, and sixth transistors are connected to a first output terminal. Collectors of the second, fourth, and fifth transistors are connected to a second output terminal.
With the dc-offset canceler circuit according to the first aspect of the present invention, the fifth and sixth bipolar transistors are additionally provided to the first and second differential pairs, respectively.
For example, if the base voltage of the fifth transistor in the first differential pair becomes higher than that of the sixth transistor in the second differential pair due to a dc offset at the first and second input terminals, base voltages of the first and fifth transistors are higher than that of the second transistor, and a base voltage of the third transistor is higher than those of the fourth and sixth transistors. Therefore, collector currents of the first and fifth transistors will increase and that of the second transistor will decrease. At the same time, a collector current of the third transistor will increase and those of the fourth and sixth transistors will decrease.
In this case, the collector current increase of the first, third, and fifth transistors and the collector current decrease of the second, fourth, and sixth transistors serve to cancel the dc offset at the first and second input terminals, because of the collector connection of the first to sixth transistors.
Thus, the dc offset generated at the first and second input terminals is canceled at the first and second output terminals.
Further, for example, if the first constant current of the first constant current source/sink for the first differential pair increases from its specific current value due to a dc offset at the first and second input terminals, the collector currents of the first, second, and fifth transistors will increase according to this current deviation. In this case, the increment of the collector current of the first transistor is supplied to the first output terminal and at the same time, the increments of the collector currents of the second and fifth transistors are supplied to the second output terminal.
As a result, the increments of the collector currents of the first, second, and fifth transistors will be partially canceled with each other. Thus, the resultant current difference between the first and second output terminals will be less than the increase of the first constant current of the first constant current source/sink.
This means that the dc offset due to the current deviation of the first and second constant current sources/sinks is suppressed with a simple configuration. In other words, the canceling of the dc offset current is effectively performed.
Because the dc-offset is effectively canceled, the dc-offset canceler circuit according to the first aspect is suitable to a limiting amplifier circuit including cascade-connected differential amplifier subcircuits.
In a preferred embodiment of the dc-offset canceler circuit according to the first aspect, first and second emitter resistors are further provided. One end of the first emitter resistor is connected to the bases of the first and fifth transistors and the other end thereof is connected to the base of the second transistor. One end of the second emitter resistor is connected to the bases of the fourth and sixth transistors and the other end thereof is connected to the base of the third transistor.
According to a second aspect of the present invention, a differential amplifier circuit is provided. This circuit is comprised of (a) a dc-offset canceler subcircuit having the same configuration as that according to the first aspect of the present invention and (b) a differential amplifier subcircuit for amplifying a differential input signal to differentially generate first and second outputs. The first and second outputs are inputted into the first and second input terminals of the dc-offset canceler subcircuit.
With the differential amplifier circuit according to the second aspect of the present invention, because the dc-offset is effectively canceled by the dc-offset canceler subcircuit, this differential amplifier circuit can be used as a limiting amplifier circuit including cascade-connected differential amplifier subcircuits.
In a preferred embodiment of the differential amplifier circuit according to the second aspect, the dc-offset canceler subcircuit has a gain of 0 dB .
In order that the present invention may be readily carried into effect, it will now be described with reference to the accompanying drawings.
FIG. 1 is a circuit diagram of a conventional dc blocking amplifier circuit with a dc-offset canceling function.
FIG. 2 is a circuit diagram of a dc-offset canceler circuit according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram of a single-stage differential amplifier circuit according to a second embodiment of the present invention, which includes the dc-offset canceler circuit according to the first embodiment in FIG. 2.
FIG. 4 is a circuit diagram of a four-stage limiting amplifier circuit according to a third embodiment of the present invention, in which a plurality of the single-stage differential amplifier circuits according to the second embodiment in FIG. 2 are cascade-connected.
Preferred embodiments of the present invention will be described below with reference to FIGS. 2 to 4.
A dc-offset canceler circuit S3 according to a first embodiment of the present invention has a configuration as shown in FIG. 2.
In FIG. 2, this dc-offset canceler circuit S3 includes a first differential amplifier subcircuit S1 and a second differential amplifier subcircuit S2, which are coupled together by an ac-coupling capacitor 13.
The first differential amplifier. subcircuit S1 is comprised of a first differential pair of npn-type bipolar transistors 1 and 2 whose emitters are coupled together, and a first constant current sink 11 sinking a first constant current I01 from the first differential pair. The coupled emitters of the transistors 1 and 2 are connected to one end of the first constant current sink 11. The other end of the first constant current sink 11 is connected to the ground.
An npn-type bipolar transistor 5 is additionally provided to the first differential pair. An emitter of the transistor 5 is connected to the emitters of the transistors 1 and 2.
Bases of the transistors 1 and 5 are connected to a first input terminal 14. A base of the transistor 2 is connected to the first input terminal 14 through a first resistor 9. The base of the transistor 2 is further connected to one end of the coupling capacitor 13.
The second differential amplifier subcircuit S2 is comprised of a second differential pair of npn-type bipolar transistors 3 and 4 whose emitters are coupled together, and a second constant current sink 12 sinking a second constant current 102 from the second differential pair. The coupled emitters of the transistors 3 and 4 are connected to one end of the second constant current sink 12. The other end of the second constant current sink 12 is connected to the ground.
An npn-type bipolar transistor 6 is additionally provided to the second differential pair. An emitter of the transistor 6 is connected to the emitters of the transistors 3 and 4.
Bases of the transistors 4 and 6 are connected to a second input terminal 15. A base of the transistor 3 is connected to the second input terminal 15 through a second resistor 10. The base of the transistor 3 is further connected to the other end of the coupling capacitor 13.
Collectors of the transistors 1, 3, and 6 are coupled together to be connected to one end of a first load resistor 7. The other end of the first load resistor 7 is applied with a power supply voltage Vcc. The coupled collectors of the transistors 1, 3, and 6 are further connected to a first output terminal 16.
Collectors of the transistors 2, 4, and 5 are coupled together to be connected to one end of a second load resistor 8. The other end of the second load resistor 8 is applied with the power supply voltage Vcc. The coupled collectors of the transistors 2, 4, and 5 are further connected to a second output terminal 17.
The transistors 1, 2, and 5 are driven by the constant current sink 11. The transistors 3, 4, and 6 are driven by the constant current sink 12.
The six transistors 1, 2, 3, 4, 5, and 6 have a same emitter area.
Next, the operation of the dc-offset canceler circuit S3 according to the first embodiment in FIG. 2 is explained below.
First, base voltages of the transistors 1, 2, 3, and 4 with respect to the reference point (e,g. the ground) are defined as VB1, VB2, VB3, and VB4, respectively. Collector currents of the transistors 1, 2, 3, 4, 5, and 6 are defined as IC1, IC2, IC3, IC4, IC5, and IC6, respectively. First and second output currents flowing through the first and second load resistors 7 and 8 are defined as IC13 and IC24, respectively.
Then, the following equations (7) and (8) are established.
IC13 =IC1 +IC3 +IC6 (7)
IC24 =IC2 +IC4 +IC5 (8)
The collector currents IC1, IC2, IC3, IC4, IC5, and IC6, of the transistors 1, 2, 3, 4, 5, and 6 are expressed by the following equations (9), (10), (11), and (12). ##EQU2##
Therefore, an. output offset current ΔI1, which is defined as ΔI1 =(IC13 -IC24), is expressed as the following equation (13), because IC1 is canceled by IC5 and IC4 is canceled by IC6.
ΔI1 =IC13 -IC24 =IC3 -IC2 (13)
The equation (13) means that the output offset current ΔI is equal to the difference between the collector currents IC2 and IC3 of the transistors 2 and 3.
On the other hand, with the conventional dc blocking amplifier circuit S300 in FIG. 1, the output offset current is ΔI2 is expressed as ΔI2 =(IC113 -IC124), which is greater than ΔI1. This means that the output offset current of the circuit S3 according to the first embodiment is less than that of the conventional dc blocking amplifier circuit S300.
With the dc-offset canceler circuit S3 according to the first embodiment in FIG. 2, for example, if the base voltage VB1 of the transistor 5 in the first differential pair becomes higher than the base voltage VB4 of the transistor 6 in the second differential pair due to a dc offset at the first and second input terminals 14 and 15, the base voltages VB1 of the transistors 1 and 5 are higher than the base voltage VB2 of the transistor 2, and the base voltage VB3 of the transistor 3 is higher than the base voltages VB4 of the transistors 4 and 6. Therefore, the collector currents IC1 and IC5 of the transistors 1 and 5 will increase and the collector current IC2 of the transistor 2 will decrease. At the same time, the collector current IC3 of the transistor 3 will increase and the collector currents IC4, IC6 of the transistors 4 and 6 will decrease.
In this case, the collector current increase of the transistors 1, 3, and 5 and the collector current decrease of the transistors 2, 4, and 6 serve to cancel the dc offset at the first and second input terminals 14 and 15, because of the collector connection of the transistors 1 to 6.
Thus, the dc offset generated at the first and second input terminals 14 and 15 is canceled at the first and second output terminals 16 and 17.
Further, for example, if the first constant current I01 of the first constant current sink 11 for the first differential pair increases from its specific current value due to a dc offset at the first and second input terminals 14 and 15, the collector currents IC1, IC2, and IC5 of the transistors 1, 2, and 5 will increase according to this current deviation. In this case, the increment of the collector current IC1 of the transistor 1 is supplied to the first output terminal 16 and at the same time, the increments of the collector currents IC2 and IC5 of the transistors 2 and 5 are supplied to the second output terminal 17.
As a result, the increments of the collector currents IC1, IC2, and IC5 of the transistors 1, 2, and 5 will be partially canceled with each other. Thus, the resultant current difference (i.e., the output offset current ΔI1) between the first and second output terminals 16 and 17 will be less than the increase of the first constant current I01 of the first constant current sink.
This means that the dc offset due to the current deviation of the first and second constant current sinks 11 and 12 is suppressed with a simple configuration. In other words, the canceling of the dc offset current is effectively performed.
The inventor performed some tests to confirm the advantage of the present invention in the following way.
The resistors 9 and 10 had a same resistance and the voltage drops (VB1 -VB2) and (VB4 -VB3) generated by the resistors 9 and 10 were set as 50 mV. The constant currents I01, and I02 of the constant current sinks 11 and 12 were set as I01 =9 μA and I02 =10 μA. In this case, the collector currents IC1, IC2, IC3, IC4, IC5, and IC6 were expressed as IC1 =IC5 =3.926 μA, IC2 =1.147 μA, IC3 =1.275 μA, and IC4 =IC6 =4.3625 μA. As a result, the output offset current ΔI1 was obtained as ΔI1 =0.28 μA.
On the other hand, with the above-explained conventional current blocking circuit S300 in FIG. 1, the collector currents IC1, IC2, IC3, and IC4 were expressed as IC1 =7.852 μA, IC2 =1.147 μA, IC3 =1.275 μA, and I4 =8.725 μA under the same conditions as above. As a result, the output offset current ΔI2 was obtained as ΔI2 =0.745 μA.
Accordingly, the output offset current ΔI1 of the dc-offset canceler circuit 33 according to the first embodiment in FIG. 2 is reduced to approximately 0.38 times as much as the output offset current ΔI2 of the conventional current blocking circuit S300 in FIG. 1, because (0.28/0.745)≈0.38.
FIG. 3 shows a single-stage differential amplifier circuit S5 according to a second embodiment of the present invention.
The differential amplifier circuit S5 includes a differential amplifier subcircuit S4 and the dc-offset canceler subcircuit S3 according to the first embodiment in FIG. 2. Therefore, the explanation about the dc-offset canceler subcircuit S3 is omitted here for the sake of simplification.
The differential amplifier circuit S4 includes a differential pair of npn-type bipolar transistors 23 and 24 whose emitters are coupled together. The coupled emitters of the transistors 23 and 24 are connected to one end of a constant current sink 22. The other end of the constant current sink 22 is connected to the ground. The transistors 23 and 24 are driven by the constant current sink 22.
Bases of the transistors 23 and 24 are connected to first and second input terminals 20 and 21, respectively.
Collectors of the transistors 23 and 24 are connected to ends of first and second load resistors 25 and 26, respectively. The other ends of the resistors 25 and 26 are applied with the power supply voltage Vcc. The collectors of the transistors 23 and 24 are further connected to the first and second input terminals 14 and 15 of the dc-offset canceler subcircuit S3.
The first and second input terminals 20 and 21 serve as input terminals of the single-stage differential amplifier circuit S5 according to the second embodiment, and the first and second output terminals 16 and 17 serve as output terminals thereof.
An initial differential input voltage is applied across the first and second input terminals 20 and 21. First and second differential output voltages of the differential amplifier subcircuit S4 are generated at the collectors of the transistors 23 and 24, respectively. The first and second differential output voltages are applied to the input terminals 14 and 15 of the dc-offset canceler subcircuit S3.
A dc offset generated at the terminals 14 and 15 is effectively canceled by the dc-offset canceler subcircuit S3.
If the dc-offset canceler subcircuit S3 has a gain of 0 dB (i.e., unity gain), this subcircuit S3 serves as a dc blocking circuit. In this case, there is an advantage that only the ac signal in the initial input voltage is selectively transferred to a subsequent circuit (not shown) located at a next stage, because the overall gain of the differential amplifier circuit S5 according to the second embodiment in FIG. 3 is equal to the gain of the differential amplifier subcircuit S4.
FIG. 4 shows a four-stage differential amplifier circuit according to a third embodiment of the present invention, in which the four single-stage differential amplifier circuits S5 according to the second embodiment in FIG. 2 are cascade-connected. In other words, the amplifier circuit S5 is used as a basic cell.
The circuit according to the third embodiment serves as a limiting amplifier for a direct conversion receiver of a pager, in which a signal in the baseband frequency region (typically, 1 kHz to 10 kHz) is amplified.
In each basic cell S5, the dc-offset canceler subcircuit S3 has a gain of 0 dB (i.e., unity gain) and serves as a dc blocking circuit. The differential amplifier circuit S5 has a gain of G1 dB, where G1 is greater than unity. Therefore, the gain of the basic cell S5 is equal to G1. Since the basic cells S5 are cascade-connected at the four stages, the overall gain of the limiting amplifier circuit in FIG. 4 is equal to 4G1 dB.
The limiting amplifier circuit in FIG. 4 has an advantage that the gain setting and gain adjustment are readily performed, because the overall gain is determined by only the differential amplifier subcircuit S4 in each basic cell.
The reference numeral S6 indicates a full-wave rectifier circuit. The full-wave rectifier circuit S6 is provided for each of the first to fourth stages.
Each of the full-wave rectifier circuits S6 has three npn bipolar transistors 30, 31, and 32, two constant current sinks 33 and 34, and a resistor 35. The differential output signal voltages generated at the first and second output terminals 14 and 15 are inputted into bases of the transistors 30 and 31, respectively The rectified signal currents are outputted from the collectors of the transistors 30 and 31, respectively.
The rectified signal currents outputted from the four differential amplifier circuits S4 are added by a current mirror circuit formed by pnp-type bipolar transistors 36 and 37 in an output circuit S7, resulting in an output signal current. This output signal current is then integrated by an integrator circuit formed by a resistor 38 and a capacitor 39, generating a dc output voltage at an output terminal 40 of the limiting amplifier. The dc output voltage thus generated is used for detecting the electric-field intensity in the received signal by an antenna of the pager. A characteristic about the dc output voltage and the input signal level is obtained.
The full-wave rectifier circuits S6 are provided for the respective differential amplifier circuits S5 in order to increase the detection range of the electric-field intensity.
The power supply voltage Vcc is typically set as low as 1 V, which is readily provided by a battery. In this case, the limiting amplifier circuit according to the third embodiment in FIG. 4 has a suitable characteristic to low-voltage operation.
Specifically, the dc-offset canceler subcircuit S3 according to the first embodiment in FIG. 2 has a transconductance gm1 given by the following expression (14) ##EQU3## where I0 is a current value of the first and second constant current sinks 11 and 12 (i.e., I0 =I01 =I02) and VT is the thermal voltage defined as kT/q.
The transconductance gml in the expression (14) is equal to (1/3) of the transconductance of the differential amplifier circuit S4 in FIG. 3.
When the load resistors 7 and 8 have a same resistance RL of 30 kΩ, the constant currents I01 and I02 are set as I01 =I02 =5 μA, and the power supply voltage VCC is set as VCC =1 V, the voltage gain Gv is expressed as follows. ##EQU4##
This means that the voltage gain Gv can be set as unity (i.e., 0 dB) if the resistance RL of the load resistors 7 and 8 is set as 30 kΩ.
On the other hand, the conventional dc blocking amplifier circuit S300 in FIG. 1 has a transconductance gm2 given by the following expression (15). ##EQU5##
The transconductance gm2 in the expression (15) is equal to (1/2) of the transconductance of the differential amplifier circuit S4 in FIG. 3, which is greater than that of the dc-offset canceler circuit S3 according to the first embodiment in FIG. 2.
Therefore, to set the gain Gv as unity (i.e., 0 dB) in the conventional circuit S300 in FIG. 1, the load resistance RL needs to be lower. The lowered resistance RL raises the dc voltage levels (i.e., dc bias voltage) at the first and second output terminals 116 and 117, because the output voltages at the output terminals 116 and 117 are given by (IC113 ×RL) and (IC124 ×RL). This leads to a disadvantage that the obtainable dynamic range of this circuit S300 becomes narrow.
As explained above, the limiting amplifier circuit according to the third embodiment in FIG. 4 is more suitable to the low-voltage operation as low as 1 V than the conventional circuit S300 in FIG. 1.
In the above-explained first embodiment in FIG. 2, the first and second differential pairs are formed by adding the resistors 9 and 10 between the bases of the transistors 2 and 5 and the bases of the transistors 3 and 6, respectively. However, the first and second differential pairs may be formed by making the emitter areas of the transistors different without using the resistors 9 and 10.
While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.
| Patent | Priority | Assignee | Title |
| 6114909, | May 31 1996 | DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT | Differential amplifier for correcting offsets at inputs using low capacitance capacitor |
| 6184723, | Mar 03 1999 | Texas Instruments Incorporated | Direct voltage to PTAT current converter for multiple gain control slope for wide dynamic range VGA |
| 6667842, | Mar 01 2001 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Negative feedback impedance matched preamplifier |
| 6856790, | Mar 27 2000 | CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Receiver with dual D.C. noise cancellation circuits |
| 7012464, | Aug 03 2000 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Method and circuit for a dual supply amplifier |
| 7095279, | Aug 28 2003 | STMICROELECTRONICS S R L | AC differential amplifier with reduced low corner frequency |
| 7257375, | Mar 27 2000 | Marvell International Ltd. | Receiver with dual D.C. noise cancellation circuits |
| 7362530, | Mar 02 2004 | Texas Instruments Incorporated | Amplifier apparatus for use with a sensor |
| 7813702, | Mar 27 2000 | CAVIUM INTERNATIONAL; MARVELL ASIA PTE, LTD | Receiver with dual D.C. noise cancellation circuits |
| Patent | Priority | Assignee | Title |
| 4933642, | Feb 17 1989 | Analog Devices International Unlimited Company | CMOS chopper-stabilized operational amplifier using two differential amplifier pairs as input stages |
| 5506537, | Jul 14 1993 | NEC Corporation | Logarithmic amplifying circuit based on the bias-offset technique |
| 5557239, | Aug 12 1994 | SAMSUNG ELECTRONICS CO , LTD | Direct current offset compensating circuit of an audio system |
| EP397250A2, | |||
| JP1255306, | |||
| JP1268303, | |||
| JP2246604, | |||
| JP3227137, | |||
| JP4240905, | |||
| JP440108, | |||
| JP484509, | |||
| JP58111415, | |||
| JP6152012, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Nov 14 1997 | KUDOU, HIROSHI | NEC Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 008904 | /0422 | |
| Nov 20 1997 | NEC Corporation | (assignment on the face of the patent) | / |
| Date | Maintenance Fee Events |
| Jul 11 2002 | M183: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Jul 07 2006 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Jul 01 2010 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| Feb 02 2002 | 4 years fee payment window open |
| Aug 02 2002 | 6 months grace period start (w surcharge) |
| Feb 02 2003 | patent expiry (for year 4) |
| Feb 02 2005 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Feb 02 2006 | 8 years fee payment window open |
| Aug 02 2006 | 6 months grace period start (w surcharge) |
| Feb 02 2007 | patent expiry (for year 8) |
| Feb 02 2009 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Feb 02 2010 | 12 years fee payment window open |
| Aug 02 2010 | 6 months grace period start (w surcharge) |
| Feb 02 2011 | patent expiry (for year 12) |
| Feb 02 2013 | 2 years to revive unintentionally abandoned end. (for year 12) |