The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.
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8. A method for storing data, comprising:
storing a respective first plurality of data bits in each of multiple elementary data storage cells; defining a second plurality of sets that each include one of said data bits from each of said data storage cells; and associating a respective correction word with each one of said sets.
20. A multi-level storage device, comprising:
a) at least a first plurality of cells, each adapted for storing a respective identical first number of binary data, said first number being greater than one; and b) at least a corresponding second plurality of cells adapted for storing a second number of error check and correcting words equal to said first number, said correcting words being respectively associated with sets of binary data, each set including a respective binary data of each cell in said first plurality.
13. A method for checking and correcting errors in a multi-level storage device of the type which comprises at least one plurality of elementary cells each adapted for storing a respective identical first number of binary data, said first number being greater than one, characterized in that, for each plurality of cells, at least a respective second number of error check and correcting words is provided which is equal to said first number, and that said correcting words are respectively associated with respective sets of binary data, each set comprising a respective one binary data of each cell in said plurality of cells.
1. A memory device, comprising:
an address decoder; a data storage matrix that is coupled to said address decoder and that includes multiple elementary data storage cells that are each operable to store a respective first plurality of data bits; and a correction storage matrix that is coupled to said address decoder and that is operable to store a second plurality of correction words that are each associated with a respective one of a third plurality of sets of said data bits, said third plurality of sets each including a respective one of said data bits from each of said data storage cells, said second plurality being equal to said third plurality.
2. The memory device of
said correction words each include a respective fourth plurality of correction bits; and said correction storage matrix comprises a fifth plurality of correction storage cells that are each operable to store a respective one of said correction bits form each of said correction words.
3. The memory device of
4. The memory device of
5. The memory device of
6. The memory device of
7. The memory device of
9. The method of
including in each of said correction words a third plurality of correction bits; and storing one of said correction bits from each of said correction words in each of a fourth plurality of correction storage cells.
11. The method of
12. The method of
14. A method according to
15. A method according to
16. A method according to
17. A method according to
18. A method according to
19. A method according to
21. A device according to
a) first decoder means operative to select and read the first plurality of an addressed section in said plurality of sections; b) second decoder means operative to select and read the second plurality of said addressed section; c) error check and correcting means connected to the outputs of said first and second decoder means, operative to check and correct any errors appearing in the contents of the cells in the addressed first plurality by the use of the contents of the cells in the addressed second plurality, and to generate corrected information; and d) third decoder means operative to select, based on an address, some of said corrected information and to supply it on the device output.
22. A device according to
23. A device according to
24. A device according to
25. A method for reading corrected information in a multi-level storage device as claimed in
a) entering a read address to said device, b) based on said address, selecting and reading a first plurality of cells; c) based on said address, selecting and reading a second plurality of cell; d) checking and correcting any errors appearing in the contents of the cells in said first plurality by using the contents of the cells in said second plurality; e) generating corrected information; and f) based on said address, selecting some of said corrected information for supply on the device output.
26. A method for writing correctable information from information to be stored into a multi-level storage device as claimed in
a) entering the information to be stored to said device; b) entering a write address to said device; c) storing said information into a first plurality of cells identified by said address at a specified location by said address; d) computing error check and correcting words from the contents of the cells in said identified plurality; and e) storing said computed words into a second plurality of cells as identified by said address.
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This invention relates to a method for checking and correcting errors in a multi-level memory, a memory device implementing the method, and related read/write methods.
The problem of error correction in memories of conventional design has been already addressed heretofore.
U.S. Pat. No. 4,958,352, for example, discloses a semiconductor memory provided with an ECC (Error Check and Correcting) circuit. The memory comprises a first cell matrix for the principal information, and a second cell matrix for the ECC information. Associated with each information word, an 8-bit word in the example, is an error check and correcting word, a 4-bit word in the example, which only allows a single error to be located and corrected (this being generally found adequate). Each bit of binary data is stored in a different one of the memory cells.
Understandably, by providing memory cells which can store, for example, four bits of data, it becomes possible to store, in the instance of the above example, each information word into two cells of the first array and the corresponding error check and correcting word into a cell of the second array.
Using Hamming codes, as the codes which provide single-error check and correcting words of shortest length, the relation 2M =N+1+M applies, where N is the bit length of the information word, and M is the bit length of the ECC word. There are, of course, other code types which allow a larger number of errors to be checked and/or corrected, but they require longer error check and correcting words. The subject is exhaustively dealt with in Jiri Adamek, "Foundations of Coding", John Wiley & Sons, 1991.
Multi-level memories are currently the subject of intensive research work because of the growing demand for semiconductor storage devices of large capacity, in particular non-volatile ones. In memories of this kind, write and/or read errors are much more likely to occur, and steps must be taken to prevent or at least reduce them.
In investigating the operation of multi-level memories, in particular of the EEPROM and Flash EPROM types, it has been found that when a cell is programmed improperly, more than one data bit in that cell are incorrect.
Of course, it would be possible to use a code which allows a large number of errors to be checked and corrected, but this results in the error corrective array attaining impractical dimensions, well in excess of those of the informational matrix.
It is an object of this invention to provide a method which enables errors in a multi-level storage device to be checked and corrected, fits the error modeling for such memories, and affords good error allowance without expanding the dimensions of the device as compared to prior devices having error correction, where the device is integrated into a chip; another object being the provision of a storage device architecture which can implement the above method.
In a multi-level storage device comprising at least one plurality of cells, each adapted to store an identical first number of binary data, which first number is greater than one, if for each plurality, at least a second number of error check and correcting words is provided which is equal to said first number, and if said words are respectively associated with sets of binary data, each comprised of one binary data for each cell in the plurality, then many of the known error correction algorithms can be applied directly to obtain comparable results to those provided by binary memories.
Furthermore, if multi-level cells are used to store the error check and correcting words, their effect on size is also comparable.
The invention will be further explained in the following description, to be read in conjunction with the accompanying drawings, in which:
FIG. 1 shows a plurality of multi-level cells and a corresponding number of ECC words, in accordance with the invention; and
FIG. 2 shows a block diagram for a storage device according to this invention.
The method of this invention will now be discussed with reference to FIG. 1. It provides error checking and correcting capabilities in a multi-level storage device of the type which comprises at least one plurality CP of cells C0 . . . C(N-1), each adapted to store an identical first number (eight in FIG. 1) of data bits, e.g., B0 . . . B7. Herein, the term "CP" represents the plurality of cells C0, C1 . . . C(N-1) taken together as a whole (as shown in FIG. 1).
This method consists of providing, for each plurality CP of cells, at least a second number (eight in FIG. 1) of error check and correcting words, e.g., W0 . . . W7. This second number is equal to said first number, and the words W-0 . . . W-7 are respectively associated with sets of data bits, each set including one data bit B0-B7 from each cell CP.
It will be appreciated that there exist several possibilities for selection of the binary information contained in the sets. Lacking any special reasons for doing otherwise, such sets would be discrete sets. Of course, the sets might include several data bits of one or more cells.
The simplest choice would be that of including in the set "0" the binary data B0 of the cells C0 . . . C(N-1) in the plurality CP; in the set "1", the binary data B1 . . . ; and in the set "7", the binary data B7.
The error check and correcting words W-0 . . . W-7 are computed from the associated set by employing an algorithm which permits error checking and correcting in said set. As previously mentioned, there are several codes which can do this. Provided that the number N of the cells CP in a plurality has been suitably selected, the probability of a single error is a reasonable one; in this case the most suitable code (the one requiring the shortest ECC word) is the Hamming code: when N is selected equal to 120, the length of the words W-0 . . . W-7 is 7 bits.
The error check and correcting words can be stored into another plurality WP of cells of a suitable type to store the first number (eight) of data bits; in this case, any additional occupation of the chip area due to the error correction is drastically reduced from conventional devices, in FIG. 1 by a factor of eight. Herein, the term "WP" represents the seven correction cells, taken together as a whole (as shown in FIG. 1), where the first correction cell stores the E0 bit information of the words W-0 . . . W-7, the second correction cell stores the E1 bit information of the words W-0 . . . W-7, etc.
The error check and correcting words W-0 . . . W-7 each include a third number (seven in FIG. 1) of binary data bits E0 . . . E6; the other plurality WP of cells may consist of a fourth number (seven in FIG. 1) of cells equal to said third number. In that case, it is convenient if each binary data bit of each word W-0-W-7 is stored into a different cell of the other plurality WP. The straightest choice consists, as shown in FIG. 1, of storing into a first cell of the other plurality WP all of the binary data bits E0 of the words W-0 . . . W-7; into a second cell, the binary data bits E1 . . . ; and into a seventh and last cell, the binary data bits E6. Understandably, there exist other viable options.
The words W-0 . . . W-7 could also be stored respectively into eight different multi-level memory cells. In the instance of FIG. 1, such cells would be somewhat underutilized in that information would be stored therein which corresponds to seven binary data bits, whilst their capacity is of eight binary data bits; the eighth binary data bit could be advantageously used for storing the parity of the corresponding error check and correcting word.
In FIG. 1, the cells in the two pluralities CP and WP are depicted as if they belonged to a word line WL of a memory array; each cell C0 . . . C(N-1) is associated with a bit line BL-0 . . . BL-N; and the words W-0 . . . W-7 are associated with an error bus EB formed, in this example, of 7 lines, equal to the length of the words and the number of cells provided for storing them.
With reference now to FIG. 2, where the storage device comprises at least a first array IA of cells arranged in rows and columns, for each row (as in FIG. 2) or column, at least said second number of error check and correcting words are provided, and each row (as in FIG. 2) or column forms a different plurality.
These error check and correcting words may then be stored into a second array EA of cells having the same number of rows (as in FIG. 2) or columns as the first array IA.
A storage device according to this invention will now be described with reference to FIG. 2.
This device basically includes:
a) at least a first plurality CP of cells, each adapted for storing an identical first number of binary data bits, which number is greater than one, and
b) at least a corresponding second plurality WP of cells adapted for storing a second number of error check and correcting words equal to the first number, such words being respectively associated with sets of binary data bits, each set comprised of a binary data bit from each cell in the first plurality CP.
The same considerations made in connection with the method description apply here to the sets.
The device of FIG. 2 comprises plural (here, four) storage sections divided into information storage sections DS0, DS1, DS2, DS3, and error storage sections ES0, ES1, ES2, ES3. Each informational section consists of 32 first pluralities CP of cells and each error section consists of 32 corresponding second pluralities WP of cells, and further includes:
a) a line decoder LD being input a line address LA and outputting 32 line signals L-0 . . . L-31;
b) an information section decoder DSD being input 4 groups of 120 bit lines from the information sections DS0, DS1, DS2, DS3 and a section address SA, and outputting one of the four groups of bit lines;
c) an error section decoder ESD being input 4 groups of 7 bit lines from the error sections ES0, ES1, ES2, ES3 and a section address SA, and outputting one of the four groups of bit lines;
d) an ECC circuit connected to the outputs of the decoders DSD and ESD, operative to check and correct any errors appearing in the contents of the cells in a first addressed plurality by the use of the contents of cells in a second addressed plurality, and to generate corrected information; and
e) a column decoder RD being input said corrected information and a column address RA, and being adapted to select, based on this address, some of the corrected information for supplying to the device output U. Herein, the term "RA" represents the column address (as shown in FIG. 2) which is coupled to the column decoder RD.
The cells of the information sections DS0, DS1, DS2, DS3 jointly form an information array IA, while the cells of the error sections ES0, ES1, ES2, ES3 form an error array EA.
Advantageously, all the cells of the arrays IA and EA are adapted for storing the same number of binary data bits, eight in the example of FIGS. 1 and 2.
In the circuit of FIG. 2, each information section DS represents a sub-array of the array IA; each row constitutes a different first plurality CP; each error section ES represents a sub-array of the array EA; each row constitutes a different second plurality WP; for each row in the sub-arrays DS, that is for each first plurality CP, there is a corresponding second plurality WP, this biunivocal relationship being exemplified in FIG. 2 for two particular pluralities by a double-headed arcuate arrow joining two blocks of the arrays IA and EA.
Understandably, in order to read and write a storage device of this type, special methods are required which would depend on its construction.
The method of this invention for reading corrected information in such a multi-level storage device basically includes:
a) entering a read address to said device consisting, in FIG. 2, of a line address LA, a section address SA, and a column address RA;
b) selecting and reading a first plurality CP of cells by coupling the line address LA into the line decoder LD and the section address SA into the information section decoder DSD;
c) selecting and reading a second plurality WP of cells by coupling the line address LA into the line decoder LD and the section address SA into the error section decoder ESD;
d) checking and correcting any errors appearing in the contents of the cells in the first plurality CP by using the contents of the cells in the second plurality WP;
e) generating corrected information; and
f) selecting some of the corrected information for supply on the device output U by coupling the column address RA into the column decoder RD.
The method of this invention for writing correctable information from information to be stored into one such multi-level storage device, basically includes:
a) entering the information to be stored to said device;
b) entering, to said device, a write address consisting, in FIG. 2, of a line address LA, a section address SA, and a column address RA;
c) storing such information into a first plurality CP of cells identified by the write address, specifically in FIG. 2, by the line address LA in combination with the section address SA, at a location specified by the write address, specifically in FIG. 2, by the column address RA;
d) computing error check and correcting words from the contents of the cells in the identified plurality CP; and
e) storing said computed words into a second plurality WP of cells identified by the write address, specifically in FIG. 2, by the line address LA in combination with the section address SA.
To revert to the storage device, it should be understood that there are several architectures to implement a traditional storage device, and consequently, there will be many different options for positioning, dimensioning, arranging and addressing the plurality of error check and correcting cells, all of which allow the method according to this invention to be implemented, and each technician will be able to pick up the most suitable option for the basic storage architecture.
It will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. For example, the multilevel storage device may be formed with N=128 and M=8. This would allow the information sections DS0, DS1, DS2, and DS3 to include 128 bit lines that carry 16 8-bit bytes of data. An additional storage cell would be needed to store the error check and correcting words W-0-W-7, which would now each include 8 bits E0-E7. Accordingly, the invention is not limited except as by the appended claims.
| Patent | Priority | Assignee | Title |
| 10135465, | Nov 08 2012 | Micron Technology, Inc. | Error correction methods and apparatuses using first and second decoders |
| 11556416, | May 05 2021 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
| 11847342, | Jul 28 2021 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
| 6839875, | Oct 18 1996 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for performing error correction on data read from a multistate memory |
| 6990623, | May 16 2001 | MONTEREY RESEARCH, LLC | Method for error detection/correction of multilevel cell memory and multilevel cell memory having error detection/correction function |
| 7181645, | Dec 27 2001 | Denso Corporation | Method and apparatus for storing main data with two checkup data |
| 7333364, | Jan 06 2000 | Super Talent Electronics, Inc | Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory |
| 7593263, | Dec 17 2006 | Apple Inc | Memory device with reduced reading latency |
| 7660941, | Sep 10 2003 | Super Talent Electronics, Inc | Two-level RAM lookup table for block and page allocation and wear-leveling in limited-write flash-memories |
| 7697326, | May 12 2006 | Apple Inc | Reducing programming error in memory devices |
| 7751240, | Jan 24 2007 | Apple Inc | Memory device with negative thresholds |
| 7773413, | Oct 08 2007 | Apple Inc | Reliable data storage in analog memory cells in the presence of temperature variations |
| 7821826, | Oct 30 2006 | Apple Inc | Memory cell readout using successive approximation |
| 7864573, | Feb 24 2008 | Apple Inc | Programming analog memory cells for reduced variance after retention |
| 7881107, | Jan 24 2007 | Apple Inc | Memory device with negative thresholds |
| 7900102, | Dec 17 2006 | Apple Inc | High-speed programming of memory devices |
| 7924587, | Feb 21 2008 | Apple Inc | Programming of analog memory cells using a single programming pulse per state transition |
| 7924613, | Aug 05 2008 | Apple Inc | Data storage in analog memory cells with protection against programming interruption |
| 7924648, | Nov 28 2006 | Apple Inc | Memory power and performance management |
| 7925936, | Jul 13 2007 | Apple Inc | Memory device with non-uniform programming levels |
| 7975192, | Oct 30 2006 | Apple Inc | Reading memory cells using multiple thresholds |
| 7995388, | Aug 05 2008 | Apple Inc | Data storage using modified voltages |
| 8000135, | Sep 14 2008 | Apple Inc | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| 8000141, | Oct 19 2007 | Apple Inc | Compensation for voltage drifts in analog memory cells |
| 8001320, | Apr 22 2007 | Apple Inc | Command interface for memory devices |
| 8046542, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Fault-tolerant non-volatile integrated circuit memory |
| 8050086, | May 12 2006 | Apple Inc | Distortion estimation and cancellation in memory devices |
| 8051358, | Jul 06 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Error recovery storage along a nand-flash string |
| 8059457, | Mar 18 2008 | Apple Inc | Memory device with multiple-accuracy read commands |
| 8060806, | Aug 27 2006 | Apple Inc | Estimation of non-linear distortion in memory devices |
| 8065583, | Jul 06 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Data storage with an outer block code and a stream-based inner code |
| 8068360, | Oct 19 2007 | Apple Inc | Reading analog memory cells using built-in multi-threshold commands |
| 8085586, | Dec 27 2007 | Apple Inc | Wear level estimation in analog memory cells |
| 8145984, | Oct 30 2006 | Apple Inc | Reading memory cells using multiple thresholds |
| 8151163, | Dec 03 2006 | Apple Inc | Automatic defect management in memory devices |
| 8151166, | Jan 24 2007 | Apple Inc | Reduction of back pattern dependency effects in memory devices |
| 8156398, | Feb 05 2008 | Apple Inc | Parameter estimation based on error correction code parity check equations |
| 8156403, | May 12 2006 | Apple Inc | Combined distortion estimation and error correction coding for memory devices |
| 8169825, | Sep 02 2008 | Apple Inc | Reliable data storage in analog memory cells subjected to long retention periods |
| 8174857, | Dec 31 2008 | Apple Inc | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
| 8174905, | Sep 19 2007 | Apple Inc | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
| 8208304, | Nov 16 2008 | Apple Inc | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
| 8209588, | Dec 12 2007 | Apple Inc | Efficient interference cancellation in analog memory cell arrays |
| 8225181, | Nov 30 2007 | Apple Inc | Efficient re-read operations from memory devices |
| 8228701, | Mar 01 2009 | Apple Inc | Selective activation of programming schemes in analog memory cell arrays |
| 8230300, | Mar 07 2008 | Apple Inc | Efficient readout from analog memory cells using data compression |
| 8234439, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Fault-tolerant non-volatile integrated circuit memory |
| 8234545, | May 12 2007 | Apple Inc | Data storage with incremental redundancy |
| 8238157, | Apr 12 2009 | Apple Inc | Selective re-programming of analog memory cells |
| 8239725, | Jul 06 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Data storage with an outer block code and a stream-based inner code |
| 8239734, | Oct 15 2008 | Apple Inc | Efficient data storage in storage device arrays |
| 8239735, | May 12 2006 | Apple Inc | Memory Device with adaptive capacity |
| 8245100, | Jul 06 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Error recovery storage along a nand-flash string |
| 8248831, | Dec 31 2008 | Apple Inc | Rejuvenation of analog memory cells |
| 8259497, | Aug 06 2007 | Apple Inc | Programming schemes for multi-level analog memory cells |
| 8259506, | Mar 25 2009 | Apple Inc | Database of memory read thresholds |
| 8261159, | Oct 30 2008 | Apple Inc | Data scrambling schemes for memory devices |
| 8270246, | Nov 13 2007 | Apple Inc | Optimized selection of memory chips in multi-chips memory devices |
| 8327245, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Memory controller supporting rate-compatible punctured codes |
| 8369141, | Mar 12 2007 | Apple Inc | Adaptive estimation of memory cell read thresholds |
| 8386895, | May 19 2010 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Enhanced multilevel memory |
| 8397131, | Dec 31 2008 | Apple Inc | Efficient readout schemes for analog memory cell devices |
| 8400858, | Mar 18 2008 | Apple Inc | Memory device with reduced sense time readout |
| 8429493, | May 12 2007 | Apple Inc | Memory device with internal signap processing unit |
| 8456905, | Dec 16 2007 | Apple Inc | Efficient data storage in multi-plane memory devices |
| 8479080, | Jul 12 2009 | Apple Inc | Adaptive over-provisioning in memory systems |
| 8482978, | Sep 14 2008 | Apple Inc | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| 8495465, | Oct 15 2009 | Apple Inc | Error correction coding over multiple memory pages |
| 8498151, | Aug 05 2008 | Apple Inc | Data storage in analog memory cells using modified pass voltages |
| 8499229, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for reading data from flash memory |
| 8527819, | Oct 19 2007 | Apple Inc | Data storage in analog memory cell arrays having erase failures |
| 8570804, | May 12 2006 | Apple Inc | Distortion estimation and cancellation in memory devices |
| 8572311, | Jan 11 2010 | Apple Inc | Redundant data storage in multi-die memory systems |
| 8572423, | Jun 22 2010 | Apple Inc | Reducing peak current in memory systems |
| 8595591, | Jul 11 2010 | Apple Inc | Interference-aware assignment of programming levels in analog memory cells |
| 8599611, | May 12 2006 | Apple Inc | Distortion estimation and cancellation in memory devices |
| 8645794, | Jul 31 2010 | Apple Inc | Data storage in analog memory cells using a non-integer number of bits per cell |
| 8677054, | Dec 16 2009 | Apple Inc | Memory management schemes for non-volatile memory devices |
| 8677203, | Jan 11 2010 | Apple Inc | Redundant data storage schemes for multi-die memory systems |
| 8694814, | Jan 10 2010 | Apple Inc | Reuse of host hibernation storage space by memory controller |
| 8694853, | May 04 2010 | Apple Inc | Read commands for reading interfering memory cells |
| 8694854, | Aug 17 2010 | Apple Inc | Read threshold setting based on soft readout statistics |
| 8700978, | May 19 2010 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Enhanced multilevel memory |
| 8713401, | Jul 06 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Error recovery storage along a memory string |
| 8719680, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for reading data from non-volatile memory |
| 8725937, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Fault-tolerant non-volatile integrated circuit memory |
| 8767459, | Jul 31 2010 | Apple Inc | Data storage in analog memory cells across word lines using a non-integer number of bits per cell |
| 8788910, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for low latency, high reliability error correction in a flash drive |
| 8793556, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for reclaiming flash blocks of a flash drive |
| 8832354, | Mar 25 2009 | Apple Inc | Use of host system resources by memory controller |
| 8856475, | Aug 01 2010 | Apple Inc | Efficient selection of memory blocks for compaction |
| 8924661, | Jan 18 2009 | Apple Inc | Memory system including a controller and processors associated with memory devices |
| 8949684, | Sep 02 2008 | Apple Inc | Segmented data storage |
| 8966352, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Memory controller supporting rate-compatible punctured codes and supporting block codes |
| 8972824, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for transparently varying error correction code strength in a flash drive |
| 8996957, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes |
| 9009565, | Mar 15 2013 | IP GEM GROUP, LLC | Systems and methods for mapping for solid-state memory |
| 9021181, | Sep 27 2010 | Apple Inc | Memory management for unifying memory cell conditions by using maximum time intervals |
| 9021333, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for recovering data from failed portions of a flash drive |
| 9021336, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages |
| 9021337, | May 22 2012 | POLARIS POWERLED TECHNOLOGIES, LLC | Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive |
| 9026867, | Mar 15 2013 | IP GEM GROUP, LLC | Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory |
| 9047214, | May 22 2012 | IP GEM GROUP, LLC | System and method for tolerating a failed page in a flash device |
| 9053012, | Mar 15 2013 | IP GEM GROUP, LLC | Systems and methods for storing data for solid-state memory |
| 9063875, | Jul 06 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Error recovery storage along a memory string |
| 9081701, | Mar 15 2013 | IP GEM GROUP, LLC | Systems and methods for decoding data for solid-state memory |
| 9104580, | Jul 27 2010 | Apple Inc | Cache memory for hybrid disk drives |
| 9152546, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Fault-tolerant non-volatile integrated circuit memory |
| 9176812, | May 22 2012 | IP GEM GROUP, LLC | Systems and methods for storing data in page stripes of a flash drive |
| 9183085, | May 22 2012 | POLARIS POWERLED TECHNOLOGIES, LLC | Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency |
| 9197251, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for reading data from non-volatile memory |
| 9208018, | Mar 15 2013 | IP GEM GROUP, LLC | Systems and methods for reclaiming memory for solid-state memory |
| 9442796, | Nov 21 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Memory controller supporting rate-compatible punctured codes |
| 9577673, | Nov 08 2012 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Error correction methods and apparatuses using first and second decoders |
| RE46346, | Oct 30 2006 | Apple Inc. | Reading memory cells using multiple thresholds |
| Patent | Priority | Assignee | Title |
| 3644898, | |||
| 4335459, | May 20 1980 | Single chip random access memory with increased yield and reliability | |
| 4691318, | Mar 04 1983 | RADYNE CORPORATION | Data transmission system with error correcting data encoding |
| 4958352, | Oct 05 1987 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with error check and correcting function |
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