A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.
|
7. A method capable of issuing two program instructions substantially concurrently to two multifunctional digital logic processing units, each of said multifunctional digital logic processing units being capable of performing the same set of logical functions on at least one operand, said multifunctional digital logic processing units being disposed on a single semiconductor integrated circuit, said method comprising:
receiving a first program instruction and a second program instruction substantially concurrently in an instruction issue control unit which is coupled to said two multifunctional digital logic processing units; issuing said first program instruction and said second program instruction to said two multifunctional digital logic processing units without first decoding said first and said second program instructions in order to determine the logical function required to be performed in response to said first and said second program instructions.
1. A superscalar microprocessor capable of processing at least two program instructions at the same time and disposed an a single semiconductor integrated circuit, said superscalar microprocessor comprising:
a plurality of registers storing a plurality of operands; an instruction issue control; a first set of independent processing logic circuits capable of performing a first set of functions, said first set of independent processing logic circuits being coupled to said instruction issue control to receive a first program instruction and being coupled to said plurality of registers to receive at least a first operand; and a second set of independent processing logic circuits providing a second set of functions, wherein said first set of functions and said second set of functions are identical, said second set of independent processing logic circuits being coupled to said instruction issue control to receive a second program instruction and being coupled to said plurality of registers to receive at least a second operand wherein said instruction issue control issues said first program instruction and said second program instruction without first decoding said first and said second program instructions in order to determine the functions specified by said first and said second program instructions in instructions.
12. A microprocessor capable of processing at least two program instructions at the same time and disposed on a single integrated circuit, said microprocessor comprising:
a plurality of registers storing a plurality of operands; an instruction issue logic; a first digital processing logic having at least a first processing unit for performing a first mathematical or logical function with at least one operand and a second processing unit for performing a second mathematical or logical function with at least one operand, said first digital processing logic being coupled to said instruction issue logic to receive at least one program instruction and being coupled to said plurality of registers to receive operands; a second digital processing logic having at least a third processing unit for performing said first mathematical or logical function and a fourth processing unit for performing said second mathematical or logical function, said second digital processing logic being coupled to said instruction issue logic to receive at least one program instruction and being coupled to said plurality of registers to receive operands wherein said instruction issue logic issues substantially concurrently a first program instruction to said first digital processing logic and a second program instruction to said second digital processing logic without first decoding said first and said second program instructions in order to determine the processing function required by either said first program instruction or said second program instruction.
2. A superscalar microprocessor as in
3. A superscalar microprocessor as in
4. A superscalar microprocessor as in
5. A superscalar microprocessor as in
6. A superscalar microprocessor as in
8. A method as in
9. A method as in
10. A method as in
11. A method as in
13. A microprocessor as in
14. A microprocessor as in
a first multiplexer coupled to said plurality of registers and having a first input for receiving operands from said plurality of registers, said first multiplexer having an output coupled to an input of said first digital processing logic, wherein said first multiplexer has only one input for receiving a result of an executed program instruction which has been executed by said first digital processing logic; a second multiplexer coupled to said plurality of registers and having a second input for receiving operands from said plurality of registers, said second multiplexer having an output coupled to an input of said second digital processing logic, wherein said second multiplexer has only one input for receiving a result of an executed program instruction which has been executed by said second digital processing logic.
15. A microprocessor as in
16. A microprocessor as in
17. A microprocessor as in
|
|||||||||||||||||||||||||
The present invention relates generally to the field of microprocessors which are capable of processing at least two program instructions at the same time.
Modern microprocessors, including superscalar microprocessors, have improved performance due to the capability of processing at least two program instructions at the same time. This capability arises from having a first group of execution units which can receive a program instruction for execution, and a second group of execution units which can receive a second program instruction for execution.
FIG. 1 shows a typical microprocessor of the prior art which uses a dual issue mechanism wherein two program instructions may be issued to two groups of execution units. The register file 30 and the issue control and bypass control unit 12 support the issuance of two instructions, one instruction going to the execution units 14, 16, and 18 (issue left) and another instruction going to the execution units 20, 22, and 24 (issue right). Within each group of execution units, there are three specialized functional units. In particular, the execution units on the issue left side include a floating point division execution unit 14, a floating point multiplier execution unit 16, and an ALU execution unit 18. In the group of execution units on the issue right side, there is a floating point adder execution unit 20, an ALU execution unit 22, and an integer multiplier unit 24. Each of these execution units is coupled to the issue control and bypass control unit 12 by a bi-directional link which provides instructions from the issue control unit 12 to the particular execution unit and which provides a signal indicating the execution unit is busy to the issue control and bypass control unit 12. In this manner, the issue control and bypass control unit 12 can determine the status of each execution unit (e.g. is the particular execution unit busy executing an instruction previously provided?) and can provide instructions for execution if the particular execution unit is not busy. These links are shown as 31A-31F in FIG. 1. The issue control and bypass unit 12 is coupled to an instruction cache 10 through a bus 11. It will be appreciated that the issue control unit 12 provides read commands to the instruction cache 10 to cause the instruction cache 10 to deliver one or two instructions at a time to the issue control unit 12.
Each execution unit within a group of execution units is coupled to an output of a multiplexer in order to receive operands which are processed according to the instruction being executed in the particular execution unit. These operands are received from either the register file 30 or from a bypass pathway in which an output from a prior executed instruction is used as an operand for a current instruction. The multiplexer 26 receives an output 30b from the register file and also receives an output from each of the six execution units and provides a selected output to the three execution units 14, 16, and 18 in the issue left group of execution units. The multiplexer 28 receives an output 30a from the register file 30 and also receives outputs from each of the six execution units, and provides an output which is selected by the control select line 15. This output is provided to the three execution units 20, 22, and 24 in the issue right execution group. The six outputs 32a, 32b, 32c, 32d, 32e, and 32f from the six execution units 14, 16, 18, 20, 22, and 24 are provided to both multiplexers 26 and 28 and also provided to the register file 30 as inputs to the register file 30. It will be appreciated that the register file 30 may be configured to provide dual port reads such that operand outputs 30a and 30b can be provided based upon the addresses provided over address bus 17 from the control unit 12. Moreover, the register file 30 may support multiple writes, such as six multiple write ports from the six outputs. It will also be appreciated that in typical operation of the microprocessor shown in FIG. 1, only two of the write ports will be active at once since normally only one result of a computation is provided from the issue left side and only one execution result is provided from the issue right side.
The operation of the microprocessor shown in FIG. 1 will now be described. The issue control unit 12 receives two instructions from the instruction cache 10. The issue control unit 12 then decodes each instruction to determine the resources or functions to be performed as required by the particular instruction. For example, if an instruction requires floating point division or floating point multiplication, then this instruction must be steered into the issue left group of execution units. Similarly, if a decoded instruction reveals that a floating point addition or integer multiplication is required by the instruction, then it must be issued to the issue right group of execution units. Thus, decoding in the issue control and bypass control unit 12 is required in order to determine whether an instruction goes to issue left or to issue right.
The issue control and bypass control unit 12 must also perform the resolution of execution unit conflicts before issuing an instruction. The following table shows an example of the stall logic in the issue control unit 12 in order to resolve execution unit conflicts. If there is an execution unit conflict indicated by a "X", then the issue control will stall the issue of the instruction.
| TABLE A |
| ______________________________________ |
| Issue |
| Instruction Instruction in Unit: |
| Type FP Div FP Mult FP Add |
| ALU 0 ALU 1 Int Mult |
| ______________________________________ |
| FP Div X |
| FP Mult X |
| FP Add X |
| ALU 1 X X |
| Int Mult X |
| ______________________________________ |
For example, if the issue instruction is of the type "FP Div" (i.e., the instruction is for a floating point division), the instruction will stall if there is an instruction in the floating point division unit 14 which is currently being executed by the floating point execution unit 14.
The issue control and bypass unit 12 also stalls the issuance of instructions in order to resolve register conflicts.
| TABLE B |
| ______________________________________ |
| Issue |
| Instruction Instruction in Unit: |
| Registers |
| FP Div FP Mult FP Add |
| ALU 0 ALU 1 Int Mult |
| ______________________________________ |
| Operand 1 |
| X X X X X X |
| Operand 2 X X X X X X |
| Destination X X X X X X |
| ______________________________________ |
If there is a register match between any of the registers indicated by "X", then the issue control unit 12 will stall the issue on the instruction. For example, if for a particular instruction which is yet to be issued, if the first operand for the instruction is to be stored in the same register as the destination register for a floating point division operation which is currently being executed, then the yet to be issued instruction will be stalled.
The issue control unit 12 also resolves resource conflicts at the register file 30 which arise because different instructions have different processor cycle times. This is shown by way of example in Table C below.
| TABLE C |
| ______________________________________ |
| Cycle ALU 0 ALU 1 FP Mult FP Add |
| ______________________________________ |
| 1 -- -- Issue -- |
| 2 -- -- Execute Issue |
| 3 -- -- Execute Execute |
| 4 Issue Issue Execute Execute |
| 5 Write Result Write Result Write Result Write Result |
| ______________________________________ |
As can be seen from Table C, in Cycle 5 there are four results that are produced. Unless there are four write ports into the register file which contains a plurality of registers, the issue of instructions for the ALU0 and ALU1 in Cycle 4 may need to be stalled.
As can be seen from the foregoing description, the issue control unit must perform a variety of control operations in order to resolve various conflicts and yet attempt to issue two program instructions substantially concurrently if possible. It will be appreciated that such control, such as the decoding of program instructions in order to steer the instruction into the appropriate group of execution units, requires considerable circuitry and also requires considerable time in designing such a control unit for this type of microprocessor.
In many circumstances, it will be desirable to provide a microprocessor which requires less complicated issue control.
A microprocessor which is capable of processing at least two program instructions at the same time and which is capable of issuing the two program instructions to two symmetrical multifunctional program execution units is described.
In a typical embodiment, the microprocessor is a superscalar microprocessor which includes a plurality of registers which store a plurality of operands and further includes an instruction issue control unit which controls the issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions, such as a first and second program instruction, without decoding the instructions in order to determine the processing functions required to be performed in response to the two program instructions.
The symmetrical multifunctional program execution units each consist of a set of independent processing logic circuits which are capable of performing a first set of functions. Typically, the independent processing logic circuits in each of the symmetrical multifunctional program execution units are identical to the extent of the functionality required in response to execution of program instructions issued by the issue control logic.
An example of a method according to the present invention issues two program instructions substantially concurrently to two multifunctional digital logic processing units. It will be appreciated that this method is capable of issuing these two program instructions substantially concurrently although it need not do so in every instance depending on stalls asserted in response to resource conflicts. The issue control logic is capable of substantially concurrently issuing two program instructions to the two multifunctional digital logic processing units and it can do so without first decoding a first and a second program instruction in order to determine the logical function required to be performed in response to the first and second program instructions.
FIG. 1 shows a prior art implementation for a microprocessor which supports dual issue of program instructions to two groups of execution units.
FIG. 2 illustrates an example of one embodiment of a microprocessor according to the present invention.
FIG. 3 represents another embodiment of a microprocessor according to the present invention.
FIG. 4 illustrates register dependency comparisons performed in one implementation of a microprocessor according to the present invention.
FIG. 5 shows a flowchart representing one method for performing stall and bypass logic processing for a high priority instruction according to one embodiment of the present invention.
FIG. 6 shows a flowchart illustrating a method according to one embodiment of the present invention for determining whether to issue an instruction for execution.
The present invention relates to a microprocessor, which is typically implemented on a single semiconductor integrated circuit and which is capable of supporting concurrent processing of at least two program instructions through at least two "pipelines." The present invention will be described by using various examples which are shown in the accompanying figures and described below. It will be appreciated that various alternative implementations may be utilized in accordance with the present invention.
FIG. 2 shows an example of a microprocessor which executes program instructions and which supports concurrent processing of at least two program instructions. Typically, the microprocessor shown in FIG. 2 will be formed in a monocrystalline silicon semiconductor integrated circuit, although other implementations will be appreciated by those skilled in the art. The microprocessor will include, at least in certain embodiments, numerous well-known supporting circuitry, such as clock generating circuitry, input and output buffer circuitry, data and address buses, and other well-known supporting components. FIG. 2 illustrates the core of a microprocessor according to the present invention. This includes an instruction cache 101 which is coupled by a bus to an issue control and bypass control unit 102. In turn, the issue control and bypass control 102 unit is coupled to two symmetrical multifunctional units 103 and 104. It will be appreciated that the symmetric multifunctional unit 103 may support a plurality of different processing functions, such as addition, division, logical operations, and multiplications. The particular group of functions supported will depend on the particular implementation. The multifunctional execution unit 104 also represents a group of execution units providing a plurality of processing functions. The processing functions provided by the unit 104 will match the processing functions provided by the unit 103 such that each unit 103 and 104 is capable of performing instructions issued by the issue control and bypass control unit 102. Operand inputs for the multifunctional processing unit 103 is provided by the multiplexer 105, and operands for the multifunctional processing unit 104 is provided by the multiplexer 106. These operands are received from either the register file 107 or from the output of a prior executed instruction from either unit 103 or unit 104.
The register file 107 includes a plurality of registers each having a specific address or number identifying the register. Data may be stored into the registers from the outputs 114a and 114a from the two groups of multifunctional execution units 103 and 104. Moreover, data may be stored into the various registers of the register file 107 through a data and address bus (not shown) which is coupled to the register file 107 to provide data to and from the register file 107. As shown in FIG. 2, the register file 107 includes two write ports and two read ports such that it is fully dual ported. Alternatively, the register file 107 may include an additional read and write port for providing data to and from a data bus on the microprocessor. The read ports 115a and 115b provide operand data to the multiplexers 105 and 106 respectively. Normally, if a bypass is not required, the operands from the read ports 115a and 115b are selected under control of selection line 111 to be outputted at the output of the multiplexers 105 and 106. These outputs are provided as operand inputs to the multifunctional execution units 103 and 104 respectively. The addresses for retrieving the various operands are provided over the address and control bus 112 from the issue control and bypass control unit 102. Each part 115a and 115b may each provide a plurality of operands to each execution unit. It will be appreciated that operands may also be obtained from other sources (e.g. a data cache or a bus).
The issue control and bypass control 102 receives signals over interconnections 110a and 110b which indicate the status of the multifunctional execution units 103 and 104 respectively. In particular, the issue control and bypass control unit 102 determines whether each of the multifunctional execution units 103 and 104 is busy executing a prior instruction. This is typically performed during each processor cycle under control of a processor clock. If a particular unit is not busy, then the issue control and bypass control unit will issue the next in order program instruction to the multifunctional execution unit which is not busy over the interconnection 110a or 110b as appropriate. Using the program instruction provided by the issue control and bypass control 102, and using the operands provided through the particular multiplexer, the multifunctional execution unit will perform the operation required by the program instruction and will provide an output which is then provided to an input of both multiplexers 105 and 106 and also to the register file 107.
In this discussion, it is assumed that the processor executes program instructions in order rather than out of order. In order means that the program instructions are executed in the order of receipt which is typically determined by the order in which the compiler generates and stores executable program instructions. In an alternative embodiment according to the present invention, a microprocessor may implement out of order issuing of program instructions by utilizing reservation stations which are well known in the art.
FIG. 3 shows another embodiment of a microprocessor according to the present invention. This embodiment is similar to the microprocessor shown in FIG. 2 except that a data cache 209 is shared between the two multifunctional processing logic units 203 and 204. An issue control unit 202 controls the issue of program instructions as well as controlling the bypass operation and also controls the operation of the data cache 209. The issue control 202 receives instructions, usually two at a time, from the instruction cache 201. The issue control unit 202 is coupled to the two groups of multifunctional processing logic units 203 and 204 by the interconnects 210a and 210b respectively. These interconnects 210a and 210b provide instructions to the units 203 and 204 and receive status indicators from these units, such as a busy status. Input operands for units 203 and 204 are received from the outputs of multiplexers 205 and 206 respectively, and the results of the executed instructions are provided at the outputs 214a and 214b respectively of the multifunctional processing logic units 203 and 304. These outputs are routed back as inputs to each of the multiplexers 205 and 206 and also as inputs to the register file 207. Read ports 215a and 215b provide operand inputs from the register file 207 which are selected when bypassing is disabled. Address and control bus 212 from the issue control unit 202 provides address and control signals to the register file 207 to retrieve operands and to store execution results in the register file 207. Select line 211 controls the bypass or no bypass status of the multiplexers 205 and 206, and this status is controlled by the bypass control unit which is part of the issue control unit 202.
As with the example shown in FIG. 2, the microprocessor of FIG. 3 includes two symmetrical multifunctional processing logic units each of which provide the same set of processing operations or functions which are capable of performing various operations or functions as required by the various program instructions issued by the issue control unit 202. For example, if multifunctional processing logic unit 203 includes a floating point adder and a floating point divider and an ALU, then the multifunctional processing logic unit 204 will include logic which provides the same processing functions. Thus the issue control unit 202 will not need to decode program instructions in order to determine the function specified by the program instructions which are to be executed in either group of execution units.
It will be appreciated that the data cache 209 represents one example of a shared resource which may be used in a microprocessor in accordance with the present invention. Other types of shared resources will also be understood to be available to be used by those of ordinary skill in the art. Inputs, such as address and/or data inputs to the data cache are multiplexed by the multiplexer 208 which is controlled by the cache control 202 through the select line 216. The inputs 208a and 208b may be addresses and/or data The output from data cache 209 is provided simultaneously over buses 209a and 209b to units 203 and 204 respectively. In the case of a read of data cache 209, an address is provided by the execution unit which is controlling the data cache 209 over either input bus 208a or 208b and this address causes the data cache 209 to retrieve data which is provided over both output buses 209a and 209b. The particular execution unit which is controlling the operation of the data cache 209 will receive and utilize the data retrieved from the data cache 209 and the other execution unit will merely ignore the data. When the issue control unit 202 receives two instructions which are to be issued, it determines whether a shared resource will be required by both instructions. If both instructions require the shared resource, then the issue control 202 will only issue the high priority instruction and will stall the low priority instruction. It will be appreciated that the high priority instruction in the case of an in order microprocessor is the first program instruction in the order of the executed program. The data cache 209 may be coupled to a data and address bus (and input/output buffers) in order to exchange data between the cache 209 and systems (e.g. system RAM) which are separate from the microprocessor.
FIGS. 4, 5, and 6 illustrate the various control operations which are performed by the issue control unit in one example of the present invention. In the following discussion, it will be assumed that the particular example of the issue control unit is the issue control and the bypass control unit 102 of the example shown in FIG. 2.
In the example shown in FIG. 4, there are fifteen comparisons which are performed to determine whether there are any matches between the addresses for various registers which are to be used for the low priority and the high priority instructions that are yet to be issued and the destination registers for instructions that are currently in the left and right groups of execution units. In particular, there are fifteen comparison operations 321-335, and the results of these comparison operations determine register dependency stalls and bypass operations. For example, the address or identification of the destination register 304 for the high priority instruction is compared in comparison 322 to the address or identification of the destination register 301 for the low priority instruction (yet to be issued). Similarly, the address or identification of the destination register 304 for the high priority instruction which is yet to be issued is compared against the address or identification of the first and second operands 302 and 303 for the low priority instruction yet to be issued in comparisons 321 and 323. The remainder of the comparisons shown in FIG. 4 determine whether the address or identification of either destination register for both instructions currently in both execution unit pipelines matches the address or identification for the registers 301-306 of both instructions which are yet to be issued.
FIG. 5 shows the control processing operations performed by an issue control unit of the present invention. This flowchart shows the control processes for the high priority instruction; it will be appreciated that a similar set of control processing operations is performed for the low priority instruction. The flowchart of FIG. 5 may be interpreted to show a sequence in time of these control processes; however, it will be appreciated that these control processes may be performed in parallel. For example, steps 401, 405, 409, and 413 may be performed in parallel such that the processes are performed substantially concurrently (at the same time). Other methods for performing the processes in parallel will be appreciated by those skilled in the art. In steps 401, 405, 409, and 413, the issue control logic determines whether the address for the register for either operand for the high priority instruction matches the address of the destination registers being used (or to be used) by the currently executed instructions in the left and right pipelines. It will be appreciated that the term "pipeline" refers to one group of execution units such that the microprocessor shown in FIG. 2 has two pipelines represented by the multifunctional units 103 and 104 respectively. Steps 401, 405, 409, and 413 represent the comparisons 330, 333, 332, and 335 respectively of FIG. 4. If all four of these comparisons reveal that there are no matches, then in step 417, the high priority instruction is issued to a non-busy group of execution units. If any one of the comparisons results in a match then further processing is performed to determine whether to stall the issuance of the high priority instruction or to bypass the result contained in a destination register for use as the operand input for the high priority instruction to be issued. These additional control processing steps are shown as steps 402-404, 406-408, 410-412, and 414-416. For example, if the comparison in step 401 indicates that there is a match between the first operand for the high priority instruction and the destination register for the left pipeline, then step 402 determines whether the data is available in that destination register (e.g. due to the fact that the execution of the prior instruction has been completed and the result of that execution has been stored in the destination register for the left pipeline). If this register is not available because it does not contain the result of the prior execution then in step 404 the issue control logic stalls the issuance of the high priority instruction. If the data is available then processing proceeds to step 403 in which the result from the prior executed instruction is used as the operand 1 input for the yet to be issued high priority instruction. This is typically implemented by causing the output from the left pipeline to be provided to the multiplexer which is used to route operand inputs to the particular group of execution units. After determining that a bypass is required in step 403, processing proceeds to step 405 (in the embodiment where steps 401 and 405 are not performed in parallel).
FIG. 6 shows one example of the control operations performed by the particular example of an issue control logic according to the present invention. The issue control logic normally receives the first and second program instructions which are kept in order; this is shown in step 450. Then in step 452, the issue control unit determines whether both groups of execution units are busy by monitoring the status lines from each group of execution units. It should be noted that the present invention may be used where there are more than two groups of execution units; for example, three groups of symmetrical multifunctional execution units may be used with the present invention. In step 454, the various register dependent stalls and bypasses are checked for the high priority instruction. These register dependent stalls and bypass checks may be similar to those described and shown in FIGS. 4 and 5. In step 456, if a group of execution units is not busy and if there are no stalls asserted for the high priority instruction, then the high priority instruction will issue to a group of execution units. Concurrently, this group of execution units will receive operands from its operand input port and will perform the instruction on the operands and provide an instruction result at the result output port of the group of execution units. Step 458 shows that the next program instruction is received from the instruction cache and the previously low priority instruction will now become the high priority instruction and processing recycles back to step 452. It will be appreciated that, as an alternative to steps 454 and 456 shown in FIG. 6, the issue control logic may concurrently check register dependent stalls and bypasses for both the high and low priority instructions and then issue concurrently both the high and low priority instructions and then receive the next two program instructions and then recycle back to step 452.
The present invention has been described in the context of several examples which have assumed certain specific architectures. It will be appreciated that the present invention may be employed in other architectures. For example, more than two groups of execution units each being symmetrical and multifunctional may be employed with the present invention. Moreover, the groups of execution units may share a shared resource such as a data cache. The present invention will allow simpler control logic to be used to control the issuance of instructions to the groups of execution units. There will be no need to decode program instructions for the purpose of determining the functions or processing required by each program instruction. Thus, instruction steering is eliminated as a requirement since each group of execution units provides identical functionality such that program instructions may be directed to any of the groups for execution. This design also simplifies other control operations as described above. While the foregoing invention has been described with respect to the above examples, it will be appreciated that the scope of the invention is limited only by the scope of the following claims.
Choquette, Jack, Yeung, Norman K.
| Patent | Priority | Assignee | Title |
| 6594753, | Jun 27 1997 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units |
| 7730284, | Mar 19 2003 | NETWORK SYSTEM TECHNOLOGIES LLC | Pipelined instruction processor with data bypassing and disabling circuit |
| 7769984, | Sep 11 2008 | International Business Machines Corporation | Dual-issuance of microprocessor instructions using dual dependency matrices |
| 7840783, | Sep 10 2007 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths |
| Patent | Priority | Assignee | Title |
| 4442484, | Oct 14 1980 | INTEL CORPORATION SANTA CLARA, CA A CORP OF CA | Microprocessor memory management and protection mechanism |
| 5450607, | May 17 1993 | ARM Finance Overseas Limited | Unified floating point and integer datapath for a RISC processor |
| 5467476, | Apr 30 1991 | Kabushiki Kaisha Toshiba | Superscalar processor having bypass circuit for directly transferring result of instruction execution between pipelines without being written to register file |
| 5546597, | Feb 28 1994 | Intel Corporation | Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution |
| 5559976, | Mar 31 1994 | International Business Machines Corporation | System for instruction completion independent of result write-back responsive to both exception free completion of execution and completion of all logically prior instructions |
| 5564056, | Mar 01 1994 | Intel Corporation | Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming |
| 5574928, | Oct 29 1993 | GLOBALFOUNDRIES Inc | Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments |
| 5574942, | Feb 28 1994 | Intel Corporation | Hybrid execution unit for complex microprocessor |
| 5628021, | Dec 31 1992 | SAMSUNG ELECTRONICS CO , LTD | System and method for assigning tags to control instruction processing in a superscalar processor |
| 5664136, | Jul 10 1995 | GLOBALFOUNDRIES Inc | High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations |
| 5689720, | Jul 08 1991 | Seiko Epson Corporation | High-performance superscalar-based computer system with out-of-order instruction execution |
| 5790827, | Jun 20 1997 | Sun Microsystems, Inc. | Method for dependency checking using a scoreboard for a pair of register sets having different precisions |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jun 25 1997 | YEUNG, NORMAN K | SANDCRAFT, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 008665 | /0215 | |
| Jun 25 1997 | CHOQUETTE, JACK | SANDCRAFT, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 008665 | /0215 | |
| Jun 27 1997 | SandCraft, Inc. | (assignment on the face of the patent) | / | |||
| Jul 21 1999 | SANDCRAFT, INC | VENTURE LENDING & LEASING II, INC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 010150 | /0674 | |
| Jul 29 2003 | SANDCRAFT, INC | Raza Microelectronics, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 014624 | /0967 | |
| Dec 14 2004 | Raza Microelectronics, Inc | VENTURE LENDING & LEASING IV, INC , AS AGENT FOR ITSELF AND SILICON VALLEY BANK AND GOLD HILL VENTURE LENDING 03, L P | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 016116 | /0147 | |
| Dec 26 2006 | Raza Microelectronics, Inc | VENTURE LENDING & LEASING IV, INC | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 019224 | /0254 | |
| Dec 17 2007 | Raza Microelectronics, Inc | RMI Corporation | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 020951 | /0633 | |
| Dec 29 2009 | RMI Corporation | NetLogic Microsystems, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023926 | /0338 | |
| Sep 02 2011 | VENTURE LENDING & LEASING, INC | NetLogic Microsystems, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 026855 | /0108 | |
| Jan 23 2013 | NetLogic Microsystems, Inc | NETLOGIC I LLC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 035443 | /0824 | |
| Mar 27 2015 | NETLOGIC I LLC | Broadcom Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 035443 | /0763 | |
| Feb 01 2016 | Broadcom Corporation | BANK OF AMERICA, N A , AS COLLATERAL AGENT | PATENT SECURITY AGREEMENT | 037806 | /0001 | |
| Jan 19 2017 | BANK OF AMERICA, N A , AS COLLATERAL AGENT | Broadcom Corporation | TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS | 041712 | /0001 | |
| Jan 20 2017 | Broadcom Corporation | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041706 | /0001 | |
| May 09 2018 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 047022 | /0620 | |
| May 09 2018 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE AND EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047022 FRAME 0620 ASSIGNOR S HEREBY CONFIRMS THE MERGER | 047185 | /0643 | |
| Sep 05 2018 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047185 FRAME 0643 ASSIGNOR S HEREBY CONFIRMS THE MERGER | 047476 | /0845 | |
| Sep 05 2018 | AVAGO TECHNOLOGIES GENERAL IP SINGAPORE PTE LTD | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED AT REEL: 047185 FRAME: 0643 ASSIGNOR S HEREBY CONFIRMS THE CORRECTIVE MERGER | 047959 | /0296 |
| Date | Maintenance Fee Events |
| Sep 05 2003 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Sep 06 2007 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Oct 22 2008 | ASPN: Payor Number Assigned. |
| Oct 04 2010 | ASPN: Payor Number Assigned. |
| Oct 04 2010 | RMPN: Payer Number De-assigned. |
| Sep 07 2011 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| Mar 07 2003 | 4 years fee payment window open |
| Sep 07 2003 | 6 months grace period start (w surcharge) |
| Mar 07 2004 | patent expiry (for year 4) |
| Mar 07 2006 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Mar 07 2007 | 8 years fee payment window open |
| Sep 07 2007 | 6 months grace period start (w surcharge) |
| Mar 07 2008 | patent expiry (for year 8) |
| Mar 07 2010 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Mar 07 2011 | 12 years fee payment window open |
| Sep 07 2011 | 6 months grace period start (w surcharge) |
| Mar 07 2012 | patent expiry (for year 12) |
| Mar 07 2014 | 2 years to revive unintentionally abandoned end. (for year 12) |