A field effect transistor utilizes an oxide film to obtain satisfactory performance characteristics and ease of manufacture. The field effect transistor includes a gate over a silicon substrate. The gate of the field effect transistor consists of an oxide film on the silicon substrate, a ferroelectric film on the oxide film, and an electrode metal film on the ferroelectric film. The material and the thickness of ferroelectric film are selected such that the product of the relative dielectric constant of ferroelectric film and the electric field across ferroelectric film is less than 15.6 mv/cm. The ferroelectric film is easily formed on the oxide film. An electric filed across the oxide film of more than 4 mv/cm will result in a break down in the oxide layer. By employing a ferroelectric film with a low relative dielectric constant, the applied electric field across the oxide film is less than 4 mv/cm. In another embodiment of the invention, a gate includes an oxide layer, an intermediate layer on the oxide layer and a ferroelectric layer on the oxide layer. The intermediate layer provides an improvement to the crystallinity of the ferroelectric layer which results in enhanced performance to the transistor, for example the turn-on voltage. The intermediate layer consists of a titanium layer on a platinum layer. The platinum layer is formed on the oxide layer to prevent the intermediate layer from peeling away from the oxide layer. The titanium layer improves the crystallinity of the ferroelectric layer.
|
2. A field effect transistor according to
3. A field effect transistor according to
4. A field effect transistor according to
said film of Pb (Zr, Ti) O3 contains a high percentage of PbTiO3 such that the relative dielectric constant of said Pb (Zr, Ti) O3 is less than 156.
5. A field effect transistor according to
6. A field effect transistor according to
7. A field effect transistor according to
10. A field effect transistor as in claim, wherein said intermediate layer includes at least one titanium layer.
11. A field effect transistor as in
12. A field effect transistor as in
13. A field effect transistor as in
said intermediate layer includes a layer of platinum on said oxide layer; and said intermediate layer also includes a titanium layer between said ferroelectric layer and said platinum layer, said titanium layer effective to prevent said intermediate layer from peeling away from said oxide layer.
14. A field effect transistor as in
said intermediate layer includes a layer of platinum on said oxide layer; and said intermediate layer also includes a titanium layer between said ferroelectric layer and said platinum layer, said platinum layer provides said means for improving the crystallinity of said ferroelectric layer.
15. A field effect transistor as in
said intermediate layer includes a layer of platinum on said oxide layer; and said intermediate layer also includes a titanium layer between said ferroelectric layer and said platinum layer, said intermediate layer effective to lower a turn on voltage applied to said gate of said transistor.
|
|||||||||||||||||||||||||||
The present invention relates to a field effect transistor. More specifically, the present invention relates to a field effect transistor that includes a gate having a ternary laminate structure composed of an electrode metal film, a ferroelectric film and an oxide film.
The so-called metal ferroelectrics semiconductor (MFS) type field effect transistor (FET) has a gate which includes a ferroelectric film. This type of field effect transistor utilizes dielectric polarization of the ferroelectrics for its turning-on and -off. An MFS-FET includes a gate, a drain on one side of the gate and a source on another side of the gate electrode. The gate includes a thin ferroelectric film formed directly on a silicon substrate. An electrode metal film is then formed on the ferroelectric film. The drain includes a drain diffusion region in a surface portion of the silicon substrate on one side of the gate. An electrode metal film is formed on the drain diffusion region. The source includes a source diffusion region in another surface portion of the silicon substrate on another side of the gate. An electrode metal film is formed on the source diffusion region.
There are difficulties in forming a ferroelectric film directly onto a silicon substrate. These difficulties are due to differences in the lattice constants of ferroelectrics and silicon. Moreover, an oxide film may form between the ferroelectric film and the silicon substrate. The ferroelectic film is heat treaded to crystallize the deposited material on the substrate. This heat treatment causes a mutual diffusion in the constituent elements of the ferroelectric film and the substrate. This mutual diffusion impairs the crystallinity of the ferroelectric film and the silicon substrate. The mutual diffusion causes poor performance characteristics in the resulting field effect transistor. It is important to note that unwanted energy levels are formed between the ferroelectric film and the silicon substrate. The unwanted energy levels result in a malfunctioning field effect transistor.
Most of the voltage that is applied between the gate electrode and the silicon substrate is applied to the oxide film. The applied voltage causes the oxide film to break down while the field effect transistor is in use. The break down in the oxide film is a main cause of failure in this type of field effect transistor. As a consequence of this, the oxide film on the surface of a silicon substrate is normally removed before the ferroelectric film is formed on the silicon substrate. Oxide film formation is suppressed as much as possible during the formation of the ferroelectric film.
A Conventional MFS-type FET is hard to manufacture and its behavior is unstable. During deposition of a ferroelectric film in the substrate, it is impossible to prevent the formation of an oxide film on the surface of the silicon substrate. The resulting oxide film breaks down while the field effect transistor is used, resulting in failure of the field effect transistor.
It is an object of the present invention to provide a field effect transistor which overcomes the drawbacks of the prior art.
It is another object of the invention to provide a field effect transistor that obviates the problems caused by the oxide film and exhibits desirable characteristics.
It is yet another object of the invention to provide a field effect transistor that is easy to manufacture.
According to an aspect of the invention, there is provided for a field effect transistor that includes: a gate including an oxide film, a ferroelectric film on the oxide film and an electrode metal film on the ferroelectric film; the ferroelectric film being formed such that the product of its relative dielectric constant and the electric field across it is less than 15.6 MV/cm. The relative dielectric constant of the ferroelectric film is set to a small value so that application of an electric field which would be high enough to cause breakdown is not applied accross the oxide film. The relative dielectric constant of the ferroelectric film is set to a small value by using a ferroelectric with a low dielectric permeability or by setting the thickness of the ferroelectric film to be thin. The intentionally formed oxide film is utilized as a part of the gate structure to facilitate forming the ferroelectric film thereon.
Briefly stated, the present invention provides for a field effect transistor that utilizes an oxide film to obtain satisfactory performance characteristics and ease of manufacture. The field effect transistor includes a gate over a silicon substrate. The gate of the field effect transistor consists of an oxide film on the silicon substrate, a ferroelectric film on the oxide film, and an electrode metal film on the ferroelectric film. The material and the thickness of ferroelectric film are selected such that the product of the relative dielectric constant of ferroelectric film and the electric field across ferroelectric film is less than 15.6 MV/cm. The ferroelectric film is easily formed on the oxide film. An electric filed across the oxide film of more than 4 MV/cm will result in a break down in the oxide layer. By employing a ferroelectric film with a low relative dielectric constant, the applied electric field across the oxide film is less than 4 MV/cm. In another embodiment of the invention, a gate includes an oxide layer, an intermediate layer on the oxide layer and a ferroelectric layer on the oxide layer. The intermediate layer provides an improvement to the crystallinity of the ferroelectric layer which results in enhanced performance to the transistor, for example the turn-on voltage. The intermediate layer consists of a titanium layer on a platinum layer. The platinum layer is formed on the oxide layer to prevent the intermediate layer from peeling away from the oxide layer. The titanium layer improves the crystallinity of the ferroelectric layer.
According to an embodiment of the present invention, there is provided for a field effect transistor comprising: a gate including an oxide film, a ferroelectric film on the oxide film and an electrode metal film on the ferroelectric film, the ferroelectric film being of a material producing a predetermined relative dielectric constant, and a product of the relative dielectric constant and an electric field across the ferroelectric film is less than 15.6 MV/cm.
According to another embodiment of the present invention, there is provided for a field effect transistor, comprising: a gate including an oxide film and a ferroelectric film on the oxide film, the ferroelectric film being of a material producing a predetermined relative dielectric constant, and the relative dielectric constant such that an operation of the gate will not produce an electric field across the oxide film of more than 4 MV/cm whereby operation of the transistor is achieved without producing a breakdown in the oxide film.
According to yet another embodiment of the present invention, there is provided for a field effect transistor, comprising: a gate including an oxide layer, an intermediate layer on the oxide layer, and a ferroelectric layer on the oxide layer, the ferroelectric layer having a crystallinity, and the intermediate layer includes means for improving the crystallinity of the ferroelectric layer.
The above, and other objects, features and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements.
FIG. 1 is a cross section of a field effect transistor according to an embodiment of the invention.
FIG. 2 is an electrical equivalent circuit of the portion that constitutes a field effect transistor.
FIG. 3 is a graph relating the time, at that the cumulative percentage defective is 20%, with the stress electric field.
FIG. 4 is a pair of hysteresis loops relating the electric field and the polarization charges with each other.
FIG. 5 is a cross section of a field effect transistor that includes a ferroelectric film, the crystallinity of that is improved, according to another embodiment of the invention.
Now the present invention will be explained hereinafter with reference made to the accompanying figures which illustrate the preferred embodiments of the invention. Throughout the figures, like parts are designated by the same reference numerals and their duplicated explanations are omitted for the sake of simplicity.
FIG. 1 shows a cross section of a field effect transistor which is designed in accordance with an embodiment of the invention. As shown in FIG. 1, a gate includes an oxide film 2 on a silicon substrate 1, a ferroelectric film 3 on oxide film 2 and an electrode metal film 4 on ferroelectric film 3. A source 5 and a drain 6 are space apart from each other on silicon substrate 1 by the gate. The metal electrode films of source 5 and drain 6 are not illustrated.
The field effect transistor of FIG. 1 positively utilizes the oxide film 2 as part of the structure of the device. The oxide film 2 is located between the substrate 1 and the ferroelectric film 3. As discussed previously, the prior art considers it hazardous to apply a voltage to a ferroelectric film when the oxide layer is present between the ferrolectric film and the substrate.
It is preferred that the relative dielectric constant of the ferroelectrics is less than 156 for following reason.
When it is desired to operate a field effect transistor, a voltage is applied to the gate of a device. To accomplish this, a voltage is applied between the gate electrode (metal film 4) and the substrate 1. FIG. 2 shows an equivalent electrical circuit for the gate portion of a field effect transistor in operation. The ferroelectric film 3 and the oxide film 3 taken together constitute the gate portion of the device.
As shown in FIG. 2, ferroelectric film 3 and oxide film 2 are electrically represented by two capacitors 11 and 12 connected in series to each other. When the device is operated by applying a voltage between the gate and substrate, (electrode metal film 4 and silicon substrate 1), a voltage is applied across the series connected capacitors. The voltage Vf is the voltage across capacitor 11 that represents ferroelectric film 3. The voltage Vox is the voltage across capacitor 12 that represents oxide film 2. Qf represents the charge stored in capacitor 11. Qox represents the charge stored in capacitor 12.
The constants used in the following descriptions will be explained at first below.
| ______________________________________ |
| Vf : Voltage applied to the ferroelectric film |
| Ef : Electric field across the ferroelectric film |
| Cf : Electrostatic capacity of the ferroelectric film |
| tf : Thickness of the ferroelectric film |
| εf : Dielectric permeability of the ferroelectric film |
| Vox : Voltage applied to the oxide film |
| Eox : Electric field across the oxide film |
| Cox : Electrostatic capacity of the oxide film |
| tox : Thickness of the oxide film |
| εox : Dielectric permeability of the oxide film |
| εo : Dielectric permeability of vacuum |
| ______________________________________ |
When the ferroelectric is polarized, the charges Qf and Qox induced in capacitors 11 and 12 are same. The charges Qf and Qox are expressed by the products of the respective electrostatic capacities and the voltages as expressed by the following equation (1).
Cf ·Vf =Cox ·Vox (1)
Considering the unit area of the films, the electrostatic capacities Cf and Cox of capacitors 11 and 12 are expressed by the following equations (2a) and (2b).
Cf =εf /tf (2a)
Cox =εox /tox (2b)
The voltages applied to capacitors 11 and 12 are expressed by the following equations (3a) and (3b).
Vf =Ef ·tf (3a)
Vox =Eox ·tox (3b)
Therefore, the following relational expression (4) is obtained by substituting the equations (3a) and (3b) in to the equation (1).
εf /εox =Eox /Ef (4)
The electric field Eox across oxide film 2 must be set to a value at which the oxide film 2 will never break down while the field effect transistor is used practically. This condition is expressed by the index described by K. Yamabe and K Taniguchi in "Time-dependent Dielectric Breakdown of Thin Thermally Grown Si O2 Films", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 20, No. 1 (1985).
FIG. 3 shows a graph relating the time it takes for the cumulative percentage of defect to reach 20% when under the stress of an electric field. As shown in the figure, the amount of time it takes to reach 20% defects is proportional to the amount of stress the electric field is exerting. Also shown in FIG. 3, break down of the oxide film is achieved in a shorter time interval when the stress electric field is larger. Conversely, the oxide film endures for a longer time interval when the stress electric field is smaller.
Considering the above relations between the electric field and the cumulative percentage defective, it is preferred that the electric field Eox across oxide film 2 is less than 4 MV/cm. When this is followed, oxide film 2 will not break down when electric field Eox across oxide film 2 is less than 4 MV/cm.
By applying the relation of the dielectric permeability εox of the oxide film, that is εox =3.9 εo, and the above condition Eox <4 MV/cm to equation (4), the following relational expression (5) is obtained.
εf ·Ef <15.6 εo MV/cm(5)
The relational expression (5) indicates that the field effect transistor will not be broken down as long as the product of the relative dielectric constant εf /εo of ferroelectric film 3 and the electric field Ef across ferroelectric film 3 is less than 15.6 MV/cm, even when oxide film 2 is between silicon substrate 1 and ferroelectric film 3.
As indicated by equation (5), the above requirements are met by selecting a ferroelectric material for ferroelectric film 3 where the dielectric permeability εf is suitably small, or by setting the electric field Ef across ferroelectric film 3 to a suitably small value. As a matter of course, a certain electric field Ef should be applied across ferroelectric film 3 to make the field effect transistor work. The strength of the electric field Ef which is required to make the ferroelectrics transistor work will be discussed below.
Carlos Paz de Araujo, James F. Scott and George W. Taylor describe the relations between the electric field and the polarization charges for the case, in that lead zirconate titanate (Pb (Zr, Ti) O3) is used as a ferroelectrics, in "FERROELECTRIC THIN FILMS: SYNTHESIS AND BASIC PROPERTIES" (1996).
FIG. 4 shows a pair of hysteresis loops relating the electric field and the polarization charges with each other before and after the fatigue test. As shown in FIG. 4, it is necessary for the electric field Ef to be equal to or higher than the electric field Er, i.e. the so-called coercive field A in FIG. 4, at that the moment polarization is caused. In addition, it is enough for the electric field Ef to be 0.1 MV/cm. FIG. 4 indicates that the polarization charge at the electric field Ef of 0.1 MV/cm is 10 μC/cm2.
Various properties of MSF-FETs are described in "Integration Technology on Ferroelectric Thin Film Memories" (in Japanese), edited by Tadashi Shiozaki et. al., Science Forum, Inc., (1992), pp. 268-269. This publication describes that the polarization charge of 0.6 μC/cm2 is enough to make the MFS-FET surely work as intended. Therefore, the polarization charge of 10 μC/cm2 is sufficiently high for proper operation of the FET.
Thus, the following relational expression (6) is obtained from the relational expression (5) described above.
εf <156 εo (6)
According to the above expression, as long as the electric field across ferroelectric film 3 is 0.1 MV/cm and its relative dielectric constant is less than 156, the field effect transistor operates normally and will not break down even if oxide film 2 is between silicon substrate 1 and ferroelectric film 3.
The ferroelectrics that exhibit the relative dielectric constant as described above will be explained below.
According to "Basis and Applications of Ferroelectric Thin Films for Nonvolatile Memories" (in Japanese), Text in the First Seminar School of JSAP Divisions Solid State Physics and Application, published from Japan Society of Applied Physics, (1997), the relative dielectric constant of Pb (Zr, Ti) O3 is around 1000. However, the relative dielectric constant of Pb (Zr, Ti) O3 lowers with increasing PbTiO3 concentration (cf N. Setter "Ferroelectric Ceramics"). Therefore, by increasing the PbTiO3 concentration in Pb (Zr, Ti) O3, the field effect transistor having the structure as described in FIG. 1 is realized. The field effect transistor shown in FIG. 1 works as intended as long as an electric filed of greater than 4 MV / cm is not applied to the gate of the device.
It is disclosed in page 77 of the foregoing "Integration Technology on Ferroelectric Thin Film Memories" that the dielectric permeability tends to be smaller as the thickness of the Pb (Zr, Ti) O3 film becomes thinner. The relative dielectric constant of the Pb (Zr, Ti) O3 film is 600 for a film thickness of 110 nm and 250 for a film thickness of 40 nm. These values satisfy the condition expressed by the foregoing relational expression (6). Further, by setting the thickness of the Pb (Zr, Ti) O3 film to 70 nm or less, the condition expressed by the relational expression (6) is satisfied with sufficient leeway. Thus, when the ferroelectric material is made from a film of Pb (Zr, Ti) O3 with a thickness no greater than 70 nm, the electric field across the oxide film does not reach or exceed 4 MV/cm and a properly functioning field effect transistor is achieved.
Ferroelectric materials with a low relative dielectric constant are applicable to the ferroelectric film in the gate structure shown in FIG. 1. For example, the relative dielectric constant of BaBi4 Ti4 O15 is 150 and the relative dielectric constant of K0.5 Bi4.5 Ti4 O15 is 140 (cf. the foregoing JSAP Seminar School Text). Since the field effect transistor that employs one of these ferroelectrics surely works under the electric field Ef of 0.1 MV/cm, the foregoing relational expression (5) is satisfied.
FIG. 5 is a cross section of a field effect transistor, according to another embodiment of the invention, that includes a ferroelectric film with improved crystallinity. As shown in FIG. 5, an intermediate film 7 is formed between oxide film 2 and ferroelectric film 3. Intermediate film 7 consists of two layers: a titanium layer 7a on the side of oxide film 2, and a platinum layer 7b on the side of ferroelectric film 3. When intermediate film 7 is composed only of platinum, it tends to peel off from oxide film 2. Titanium layer 7a is interposed to prevent film 7 from peeling away from oxide film 2. The crystallinity of ferroelectric film 3 is improved by growing it on platinum layer 7b. The crystal structure of platinum exhibits a crystallinity which enhances the titanium crystallinity. The improved crystallinity of ferroelectric film 3 further improves the characteristics of the resulting transistor. For example, the amount of voltage required at the gate to turn on the transistor is lowered with improved crystallinity in the ferroelectric film 3.
As explained above, the field effect transistor according to the invention includes an oxide film, interposed between a silicon substrate and a ferroelectric film. The transistor is constructed such that the product of the relative dielectric constant of the ferroelectric film and the electric field across the ferroelectric film is less than 15.6 Mv/cm. Since the ferroelectric film is formed easily on the oxide film, a field effect transistor is realized that is easy to manufacture and exhibits satisfactory characteristics. The oxide film prevents mutual diffusion of the constituent elements of the substrate and the ferroelectric film. Since the oxide film provides the field effect transistor with the same structure as the usual metal oxide semiconductor (MOS) structure, no unwanted energy levels are produced.
Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims.
Furuta, Taku, Nagayasu, Yoshihiko
| Patent | Priority | Assignee | Title |
| 6608339, | Apr 07 2000 | Seiko NPC Corporation | Ferroelectric memory element |
| 6674110, | Mar 02 2001 | COVA TECHNOLOGIES, INC | Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric |
| 6714435, | Sep 19 2002 | COVA Technologies, Inc. | Ferroelectric transistor for storing two data bits |
| 6790679, | Aug 28 2002 | COVA Technologies, Inc. | Ferroelectric transistor with enhanced data retention |
| 6812509, | Jun 28 2002 | Palo Alto Research Center, Incorporated | Organic ferroelectric memory cells |
| 6888736, | Sep 19 2002 | COVA Technologies, Inc. | Ferroelectric transistor for storing two data bits |
| 7008833, | Jan 12 2004 | Sharp Kabushiki Kaisha | In2O3thin film resistivity control by doping metal oxide insulator for MFMox device applications |
| 7030435, | Aug 24 2000 | COVA TECHNOLOGIES, INC | Single transistor rare earth manganite ferroelectric nonvolatile memory cell |
| 7034349, | Sep 19 2002 | COVA Technologies, Inc. | Ferroelectric transistor for storing two data bits |
| 7504682, | Jan 25 2006 | Seiko Epson Corporation | Polarization transfer device and control method therefor |
| Patent | Priority | Assignee | Title |
| 3832700, | |||
| 5368094, | Nov 02 1993 | Bipartite heat sink positioning device for computer chips | |
| 5572052, | Jul 24 1992 | Mitsubishi Denki Kabushiki Kaisha | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer |
| 5621681, | Mar 22 1995 | SAMSUNG ELECTRONICS CO , LTD | Device and manufacturing method for a ferroelectric memory |
| 5812422, | Sep 07 1995 | U S PHILIPS CORPORATION | Computer software for optimizing energy efficiency of a lighting system for a target energy consumption level |
| 5821005, | Mar 08 1995 | Sharp Kabushiki Kaisha | Ferroelectrics thin-film coated substrate and manufacture method thereof and nonvolatile memory comprising a ferroelectrics thinfilm coated substrate |
| 5959879, | Jun 09 1997 | Samsung Electronics Co., Ltd. | Ferroelectric memory devices having well region word lines and methods of operating same |
| 5962884, | Mar 07 1997 | Sharp Laboratories of America, Inc | Single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization and method of making the same |
| JP11050255, | |||
| JP5243562, | |||
| JP9213819, |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Mar 03 1999 | Fuji Electric Co., Ltd. | (assignment on the face of the patent) | / | |||
| Mar 30 1999 | FURUTA, TAKU | FUJI ELECTRIC CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009982 | /0437 | |
| Mar 30 1999 | NAGAYASU, YOSHIHIKO | FUJI ELECTRIC CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009982 | /0437 |
| Date | Maintenance Fee Events |
| Jan 03 2001 | ASPN: Payor Number Assigned. |
| Dec 22 2003 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Jan 21 2008 | REM: Maintenance Fee Reminder Mailed. |
| Jul 11 2008 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
| Date | Maintenance Schedule |
| Jul 11 2003 | 4 years fee payment window open |
| Jan 11 2004 | 6 months grace period start (w surcharge) |
| Jul 11 2004 | patent expiry (for year 4) |
| Jul 11 2006 | 2 years to revive unintentionally abandoned end. (for year 4) |
| Jul 11 2007 | 8 years fee payment window open |
| Jan 11 2008 | 6 months grace period start (w surcharge) |
| Jul 11 2008 | patent expiry (for year 8) |
| Jul 11 2010 | 2 years to revive unintentionally abandoned end. (for year 8) |
| Jul 11 2011 | 12 years fee payment window open |
| Jan 11 2012 | 6 months grace period start (w surcharge) |
| Jul 11 2012 | patent expiry (for year 12) |
| Jul 11 2014 | 2 years to revive unintentionally abandoned end. (for year 12) |