A plurality of row electrodes and a plurality of column electrodes are provided so as to intersect with each other to form a pixel at every intersection. A phosphor layer is provided along each of the column electrodes. The phosphor layer is disposed so that three unit luminous areas of red, green and blue are provided in each pixel. Three phosphor layers for a first pixel on a display line are disposed in order of red, green and blue, and three phosphor layers for a second pixel adjacent the first pixel are disposed in order of blue, green and red.

Patent
   6157355
Priority
Apr 25 1997
Filed
Apr 08 1998
Issued
Dec 05 2000
Expiry
Apr 08 2018
Assg.orig
Entity
Large
6
7
EXPIRED
1. A matrix type display device comprising:
a plurality of row electrodes which define display lines;
a plurality of column electrodes which intersect the row electrodes to thereby form a pixel at every intersection; and
phosphor layers having luminous colors of red, green and blue provided across the row electrodes in such a way that three adjoining unit luminous areas of red, green and blue corresponding to the phosphor layers of the associated colors in each display line are associated with each of pixels arranged in such a manner that on the display line, those pixels whose three unit luminous areas are laid in order of red, green and blue and those pixels whose three unit luminous areas are laid in order of blue, green and red are alternately arranged.
2. The display device according to claim 1, wherein each of the row electrodes comprises a transparent conductive film and a metallic film laminated on the transparent electrode and is disposed on a display-side substrate and the phosphor layers are provided on a back-side substrate facing the display-side substrate with a discharge space interposed there between.

The present invention relates to a display device of a matrix type such as a plasma display panel (PDP), a liquid crystal display (LCD), and an electroluminescent display (ELD) for displaying color images.

Recently, as a display device becomes large in size, thickness of the display device is desired to be thin. Therefore, various types of display devices thin are supplied. In the display device such as PDP, LCD and ELD, three primary colors of red (R), green (G) and blue (B) are properly combined to display various color images. In the matrix display, three unit luminous areas corresponding to the three primary colors are provided in each pixel. As one of the matrix type display devices in which color images are properly displayed using a phosphor layer, a PDP of a surface discharge type using alternating current (AC) is known.

For example, a PDP of surface discharge type of three-electrode comprises a pair of front and rear substrates disposed opposite to each other, interposing a discharge space therebetween. The front substrate as a display portion has a plurality of row electrodes which are alternately disposed in pairs to be parallel with each other at the inside portion thereof. The row electrodes are covered by a dielectric layer at the discharge space. On the rear substrate, a plurality of column electrodes are formed on the inside portion thereof to intersect the row electrodes of the front substrate. A phosphor layer having a different luminous color covers each of the column electrodes. At the intersection of each of the column electrodes and each pair of row electrodes, a unit luminous area (discharge cell) is formed.

FIG. 3 shows an arrangement of pixels in the conventional PDP of surface discharge type.

A pair of row electrodes X and Y are laterally disposed, interposing a discharge gap at every line L as a display line. A plurality of column electrodes A (Ai, Ai+1, Ai+2 . . . ) are disposed to intersect the row electrodes X and Y. A plurality of phosphor layers 8 (8R, 8G and 8B) are provided on the column electrodes A. The phosphor layers 8R, 8G and 8B have luminous colors red (R), green (G) and blue (B) respectively, corresponding to the three primary colors R, G and B. The phosphor layers 8R, 8G and 8B are disposed on the column electrodes A in the order from the left to right in FIG. 3.

At the intersection of the data electrode A having the phosphor layer 8 and the row electrodes X and Y, a unit luminous area EU is defined. Corresponding to the luminous colors of the phosphor layers 8B, 8G and 8B, a unit luminous area EU(R) of red (R), a unit luminous area EU(G) of green (G), and a unit luminous area EU(B) of blue (B) are respectively defined.

A pixel EG consists of three unit luminous areas EU(R), EU(G) and EU(B) which are disposed in the order from the left to right in FIG. 3.

In a driving operation of the PDP, a unit period of display is divided into an address period and a discharge sustaining period.

In the address period, pixel data pulses are applied to the column electrodes, while scanning pulses are applied to one of the row electrodes by a selecting and writing address method or a selecting and erasing address method. Thus, a wall charge is accumulated only in the unit luminous area EU to be lighted every line in order.

In the discharge sustaining period, discharge sustaining pulses are alternately applied to the row electrodes X and Y. Thus, only the unit luminous area EU to be lighted which holds the wall charge sustains the discharge. If the number of applications of discharge sustaining pulses per unit time is properly set, the luminance of the display can be controlled.

In the address period, if a difference of potential is produced between the column electrodes, a reactive power produces by a parasitic capacitance between the data electrodes. In particular, in case of a monochromatic display by either of R, G or B, the reactive power increases. For example, in the monochromatic display of R, a parasitic capacitance between the column electrode of R and the column electrode of G adjacent to the column electrode of R, and a parasitic capacitance between the column electrode of R and the column electrode of B adjacent to the data electrode of R are equivalently loaded, thereby increasing the reactive power.

In order to reduce the parasitic capacitance between the column electrodes which causes the reactive power to increase, it is necessary to provide a sufficient large distance between the column electrodes. Therefore, it is difficult to obtain the PDP of high definition by reducing the distance between the column electrodes.

An object of the present invention is to provide a matrix type display device in which an increase in reactive power is suppressed, thereby ensuring high definition display.

According to the present invention, there is provided a matrix type display device having a plurality of row electrodes, a plurality of column electrodes which intersect with the row electrodes to form a pixel at every intersection, and a phosphor layer provided along each of the column electrodes, the phosphor layer being disposed so that three unit luminous areas of red, green and blue are provided in each pixel, wherein three phosphor layers for a first pixel on a display line are disposed in order of red, green and blue, three phosphor layers for a second pixel adjacent the first pixel are disposed in order of blue, green and red, and the first and second pixels are sequentially arranged.

The display device comprises a pair of substrates disposed opposite to each other, interposing a discharge space, the row electrodes are disposed on the substrate on a display side, and covered by a dielectric layer, each of the row electrodes comprises a transparent conductive film and a metallic film layered on the transparent electrode, the phosphor layers are provided on the substrate on a back side of the display.

These and other objects and features of the present invention will become more apparent from the following detailed description with reference to the accompanying drawings.

FIG. 1 is a schematic perspective view showing a plasma display panel according to the present invention;

FIG. 2 is a schematic plan view showing the arrangement of pixels of the plasma display panel; and

FIG. 3 is a schematic plan view of a conventional plasma display panel.

FIG. 1 shows an ACPDP of a reflection type of three-electrode according to the present invention. An ACPDP 11 comprises a pair of glass substrates 1 and 2 disposed opposite to each other, interposing a discharge space 7 therebetween. The glass substrate 1 as a display portion has row electrodes (sustain electrodes) X and Y which are alternately disposed in pairs to be parallel with each other at the inside portion thereof. The row electrodes X and Y are covered by a dielectric layer 5 for producing wall charge. A protection layer 6 made of MgO is coated on the dielectric layer 5.

Each of the row electrodes X and Y comprises a transparent electrode 4 formed by a transparent conductive film having a large width and a bus electrode (metallic electrode) 3 formed by a metallic film having a small width and layered on the transparent electrode 4.

On the glass substrate 2 as a rear member, a plurality of elongated barriers 10 are provided at the inside portion thereof for defining the discharge space 7. The barrier 10 extends in the direction perpendicular to the row electrodes X, Y. Between the barriers 10, column electrodes (address electrodes) A are formed to intersect the row electrodes X and Y of the glass substrate 1. A phosphor layer 8 having a predetermined luminous color red (R), green (G) or blue (B) covers each of the column electrodes A and opposite side portions of the barrier 10. The discharge space 7 is filled with discharge gas consisting of neon mixed with xenon. Thus, a discharge cell (pixel) is formed at the intersection of the row electrodes in pairs and the column electrode.

FIG. 2 shows an arrangement of pixels in the conventional PDP of surface discharge type.

A pair of row electrodes X and Y are laterally disposed, interposing a discharge gap at every display line L. A plurality of column electrodes A (Ai, Ai+1, Ai+2 . . . ) are disposed to intersect the row electrodes X and Y. A plurality of phosphor layers 8 (8R, 8G and 8B) are provided on the column electrodes A. The phosphor layers 8R, 8G and 8B have luminous colors red (R), green (G) and blue (B) respectively, corresponding to the three primary colors R, G and B.

At the intersection of the column electrode A having the phosphor layer 8 and the row electrodes X and Y, a unit luminous area EU(R) of red (R), a unit luminous area EU(G) of green (G), or a unit luminous area EU(B) of blue (B) is formed corresponding to each of the luminous colors of the phosphor layers 8B, 8G and 8B.

A pixel EG-1 comprises three unit luminous areas EUs in the order of EU(R), EU(G) and EU(B) from the left to right in FIG. 2, and a pixel EG-2 comprises three unit luminous areas EUs in the order of EU(B), EU(G) and EU(R) from the left to right in FIG. 2. The pixels EG-1 and EG-2 are alternately disposed along the display line L.

In the embodiment, the unit luminous area EU(R) of red (R) in the pixel EG-2 is disposed to adjoin the unit luminous area EU(R) of red (R) in the adjacent pixel EG-1. Similarly, the unit luminous area EU(B) of the blue (B) in the pixel EG-1 is disposed to adjoin the unit luminous area EU(B) of the blue (B) in the opposite adjacent pixel EG-2.

Therefore, in the case of the monochromatic display of R, only the parasitic capacitance between the column electrodes of R and G is equivalently loaded. Thus, the reactive power is reduced half.

Similarly, in the monochromatic display of B, only the parasitic capacitance between the column electrodes of B and G is equivalently loaded. Thus, the reactive power is reduced half.

Since the disposition of the unit luminous area EU(G) which has a high spectral luminous efficacy does not change, the resolution of display does not deteriorate.

In accordance with the present invention, in the monochromatic display of R or B, since the unit luminous area of R or B is disposed to adjoin each other in the adjacent pixels, the difference of potential is not produced. Thus, the reactive power is regulated from increasing. Since the distance between the column electrodes can be reduced, it is possible to obtain a display of high definition.

While the invention has been described in conjunction with preferred specific embodiment thereof, it will be understood that this description is intended to illustrate and not limit the scope of the invention, which is defined by the following claims.

Ide, Shigeo

Patent Priority Assignee Title
6549180, May 04 1998 POLYVISTA, INC Plasma display panel and driving method thereof
6879104, Jan 02 2001 THOMSON LICENSING S A Structure of sustain electrodes for the front tile of a plasma display panel
6882114, Mar 18 1999 MAXELL, LTD Plasma display panel
RE41669, May 10 2002 Transpacific Infinity, LLC Low-cost circuit board materials and processes for area array electrical interconnections over a large area between a device and the circuit board
RE41914, May 10 2002 Transpacific Infinity, LLC Thermal management in electronic displays
RE42542, May 10 2002 Transpacific Infinity, LLC Low-cost circuit board materials and processes for area array electrical interconnections over a large area between a device and the circuit board
Patent Priority Assignee Title
4689522, Dec 03 1985 The United States of America as represented by the Administator of the Flat-panel, full-color, electroluminescent display
4975691, Jun 16 1987 Interstate Electronics Corporation Scan inversion symmetric drive
5113274, Jun 13 1988 Mitsubishi Denki Kabushiki Kaisha Matrix-type color liquid crystal display device
5629716, Jul 19 1993 MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD Luminescent panel for color video display and its driving system, and a color video display apparatus utilizing the same.
5661500, Jan 28 1992 Hitachi Maxell, Ltd Full color surface discharge type plasma display device
5674553, Jan 28 1992 Hitachi Maxell, Ltd Full color surface discharge type plasma display device
5854540, Jun 18 1996 Mitsubishi Denki Kabushiki Kaisha Plasma display panel driving method and plasma display panel device therefor
//
Executed onAssignorAssigneeConveyanceFrameReelDoc
Mar 31 1998IDE, SHIGEOPioneer Electronic CorporationASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS 0090900994 pdf
Apr 08 1998Pioneer Electronic Corporation(assignment on the face of the patent)
Date Maintenance Fee Events
Feb 12 2001ASPN: Payor Number Assigned.
May 04 2004M1551: Payment of Maintenance Fee, 4th Year, Large Entity.
Sep 28 2004ASPN: Payor Number Assigned.
Sep 28 2004RMPN: Payer Number De-assigned.
Jun 16 2008REM: Maintenance Fee Reminder Mailed.
Dec 05 2008EXP: Patent Expired for Failure to Pay Maintenance Fees.


Date Maintenance Schedule
Dec 05 20034 years fee payment window open
Jun 05 20046 months grace period start (w surcharge)
Dec 05 2004patent expiry (for year 4)
Dec 05 20062 years to revive unintentionally abandoned end. (for year 4)
Dec 05 20078 years fee payment window open
Jun 05 20086 months grace period start (w surcharge)
Dec 05 2008patent expiry (for year 8)
Dec 05 20102 years to revive unintentionally abandoned end. (for year 8)
Dec 05 201112 years fee payment window open
Jun 05 20126 months grace period start (w surcharge)
Dec 05 2012patent expiry (for year 12)
Dec 05 20142 years to revive unintentionally abandoned end. (for year 12)