The differential mode gate includes a first load resistance having a first current driving capability. The first load resistance is connected to a power supply voltage. A constant current source, having a second current driving capacity, is connected to ground. A first logic gate is connected between the first load resistance and the constant current source. The first logic gate performs a first logic operation on received inputs to generate a first output. The differential mode gate additionally includes a second load resistance and a second logic gate. The second load resistance has a third current driving capability and is connected to the power supply voltage. The second logic gate is connected between the second load resistance an the constant current source, and performs a second logic operation on the received inputs to generate a second output.
|
1. A logic circuit, comprising:
a first load resistance having a first current driving capability connected to a power supply voltage; a constant current source having a second current driving capacity connected to ground; and a first logic gate connected between said first load resistance and said constant current source, said first logic gate performing a first logic operation on received inputs to generate a first output, wherein said first load resistance includes a transistor connected between said power supply voltage and said first logic gate, and having a connected gate and drain.
11. A logic circuit, comprising:
a first load resistance having a first current driving capability connected to a power supply voltage; a constant current source having a second current driving capacity connected to ground; a first logic gate connected between said first load resistance and said constant current source, said first logic gate performing a first logic operation on received inputs to generate a first output; a second load resistance having a third current driving capability connected to said power supply voltage; and a second logic gate connected between said second load resistance and said constant current source, said second logic gate performing a second logic operation on said received inputs to generate a second output, wherein said first logic operation is a nand operation and said second logic operation is a NOR operation.
12. A logic circuit, comprising:
a first load resistance having a first current driving capability connected to a power supply voltage; a constant current source having a second current driving capacity connected to ground; a first logic gate connected between said first load resistance and said constant current source, said first logic gate performing a first logic operation on received inputs to generate a first output; a second load resistance having a third current driving capability connected to said power supply voltage; and a second logic gate connected between said second load resistance and said constant current source, said second logic gate performing a second logic operation on said received inputs to generate a second output, wherein said first logic gate includes a first pull-up circuit performing a first pull-up operation on said first output based on said received inputs and a first pull-down circuit performing a first pull-down operation on said first output based on said received inputs; and said second logic gate includes a second pull-up circuit performing a second pull-up operation on said second output based on said received inputs and a second pull-down circuit performing a second pull-down operation on said second output based on said received inputs.
2. The logic circuit of
3. The logic circuit of
6. The logic circuit of
7. The logic circuit of
a second load resistance having a third current driving capability connected to said power supply voltage; and a second logic gate connected between said second load resistance and said constant current source, said second logic gate performing a second logic operation on said received inputs to generate a second output.
8. The logic circuit of
9. The logic circuit of
10. The logic circuit of
|
|||||||||||||||||||||||||
1. Field of the Invention
The present invention relates to logic circuits, and more particularly to logic gates with improved operating speed and noise properties.
2. Discussion of Related Art
NAND and NOR gates are the basic logic elements used for representing a digital logic circuit in a semiconductor integrated circuit. In general, the logic elements used in a digital logic circuit include AND, OR, NOT, NAND, NOR, XOR and XNOR gates. All these logic elements do not have a different circuit from each other. Instead, a combination of NAND, NOR and NOT gates defines circuits of the other logic elements. For instance, the circuit of an AND gate is defined by connecting, in series, a NOT gate to the output of a NAND gate. The circuit of an OR gate is defined by connecting, in series, a NOT gate to the output of a NOR gate.
FIGS. 1A, 1B and 1C are the logical symbol, truth table, and circuit, respectively, of a related art NAND gate. In FIG. 1A, A1 and B1 are input signals, and Z1 is an output signal. A logical value of output signal Z1 is determined by the logical values of the, two input signals A1 and B1. FIG. 1B is the truth table of output signal Z1 based on input signals A1 and B1. When at least one of A1 and B1 is 0 (VSS), output signal Z1 becomes 1 (VDD). On the other hand, when both input signals A1 and B1 are 1, output signal Z1 becomes 0.
In FIG. 1C, two PMOS transistors MP11 and MP12, of which sources are supplied a power supply voltage VDD, are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP11 is supplied the first input signal A1 and the gate of the other PMOS transistor MP12 is supplied the second input signal B1. The drains of the two transistors MP11 and MP12 are connected to each other to form a common node.
Two NMOS transistors MN11 and MN12 are connected in series between the common node and ground VSS to form a pull-down circuit. The gate of NMOS transistor MN11, which is directly connected to the common node, is supplied input signal A1 and the gate of NMOS transistor MN12, which is connected to the ground VSS, is supplied input signal B1.
When at least one of the two input signals A1 and B1 is 0 (VSS), at least one of the two PMOS transistors MP11 and MP12 is turned on, and at least one of the two NMOS transistors MN11 and MN12 is turned off. Therefore, output signal Z1 becomes 1 (VDD). On the other hand, when both input signals A1 and B1 are 1, the two PMOS transistors MP11 and MP12 are turned off, and the two NMOS transistors MN11 and MN12 are turned on. Therefore, output signal Z1 becomes 0.
FIGS. 2A, 2B and 2C are the logical symbol, truth table, and circuit, respectively, of a related art NOR gate. In FIG. 2A, A2 and B2 are input signals and Z2 is an output signal. A logical value of output signal Z2 is determined by the logical values of the two input signals A2 and B2. FIG. 2B is a truth table of output signal Z2 based on input signals A2 and B2. As shown in the truth table, when at least one of the two input signals A2 and B2 is 1, output signal Z2 becomes 0. On the other hand, if both of the two input signals A2 and B2 are 0, output signal Z2 is 1.
In FIG. 2C, two PMOS transistors MP21 and MP22, of which sources are supplied the power supply voltage VDD, are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP21 is supplied the input signal A2 and the gate of PMOS transistor MP22 is supplied the input signal B2. Two NMOS transistors MN21 and MN22 are connected in parallel between the drain of PMOS transistor MP22 and the ground VSS to form a pull-down circuit. The gate of NMOS transistor MN21 is supplied input signal A2 and the gate of NMOS transistor MN22 is supplied input signal B2.
When at least one of the two input signals A2 and B2 is 1, at least one of the two PMOS transistors MP21 and MP22 is turned off, and at least one of the two NMOS transistors MN21 and MN22 is turned on. Therefore, output signal Z2 becomes 0. On the other hand, when both input signals A2 and B2 are 0, the two PMOS transistors MP21 and MP22 are turned on and the two NMOS transistors MN21 and MN22 are turned off. Therefore, output signal Z2 becomes 1.
As described above, in a NAND gate or a NOR gate of the related art, the output signal fully swings between the levels of the power supply voltage VDD and the ground voltage VSS. Therefore, high-speed operation and low power consumption can not be expected. Also, since the highest levels of the input/output signals are in a single mode, a power supply voltage and ground voltage, if the power supply voltage is varied because of temperature variations, the output signal fails to have a stable logic value. As a result, the reliability of circuit operation is remarkably reduced.
Accordingly, the present invention is directed to a logic circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a logic circuit having high operation speed and low power consumption.
Another object of the present invention is to reduce chip size by simultaneously representing, for example, a NAND gate and a NOR gate in a logic circuit, and decreasing the number of gates.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
These and other objects are achieved by providing a logic circuit including a first load resistance, a constant current source, and a first logic gate connected between the first load resistance and the constant current source. The first load resistance has a first current driving capability and is connected to a power supply voltage. The constant current source has a second current driving capacity and is connected to ground. The first logic gate performs a first logic operation on received inputs to generate a first output.
These and other objects are also achieved by further providing a second load resistance and a second logic gate. The second load resistance has a third current driving capability and is connected to the power supply voltage. The second logic gate is connected between the second load resistance and the constant current source, and performs a second logic operation on received inputs to generate a second output.
The accompanying drawings, which are included to provide a further understanding of the invention and which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, wherein like reference numerals denote like components, and together with the description serve to explain the principles of the invention.
In the drawings:
FIGS. 1A to 1C show a related art NAND gate.
FIGS. 2A to 2C show a related art NOR gate.
FIGS. 3A to 3C show differential mode NAND/NOR gates according to an embodiment of the present invention.
FIGS. 4A to 4F compare input/output signals of the differential mode NAND/NOR gate of FIG. 3C with input/output signals of the NAND gate of FIG. 1C.
FIGS. 5A to 5C show differential mode NAND/NOR gates according to another embodiment of the present invention.
FIG. 6 shows another embodiment of the differential mode NAND/NOR gates according to the present invention.
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
FIG. 3A to 3C are the logic symbol, truth table and circuit of differential mode NAND/NOR gates according to the present invention, respectively.
In FIG. 3A, A3 and B3 are input signals. Z3 and /Z3 are output signals, which are complementary. Output signal Z3 is obtained by a NAND operation on the two input signals A3 and B3. That is, as shown in FIG. 3B, when at least one of the two input signals A3 and B3 is 0, the output signal Z3 becomes 1, while when both input signals A3 and B3 are 1, output signal Z3 becomes 0.
In FIG. 3C, respective gates and drains of two PMOS transistors MP31 and MP32, acting as active loads, are connected each other. The respective sources of the two PMOS transistors MP31 and MP32 are supplied with the power supply voltage VDD. The gates of the two PMOS transistors MP31 and MP32 are connected to each other. This equalizes the voltages applied to the gates of the two PMOS transistors MP31 and MP32, and overcomes a mismatch of the two PMOS transistors MP31 and MP32 caused during the manufacturing process.
The drain of PMOS transistor MP31 is connected to a NAND gate circuit NAND1. In NAND gate circuit NAND1, two PMOS transistors MP33 and MP34 are connected in parallel to form a pull-up circuit. The gate of PMOS transistor MP33 is supplied input signal A3 and the gate of PMOS transistor MP34 is supplied input signal B3. The drains of the two transistors MP33 and MP34 are connected to form a common node. Two NMOS transistors MN31 and MN32 are connected in series between this common node and a constant current source 10 to form a pull-down circuit. The gate of NMOS transistor MN31 is supplied input signal A3 and the gate of NMOS transistor MN32 is supplied input signal B3. The constant current source 10 is connected between the source of NMOS transistor MN32 and the ground.
When at least one of the two input signals A3 and B3 is 0, at least one of the two PMOS transistors MP33 and MP34 is turned on and at least one of two NMOS transistors MN31 and MN32 is turned off. Therefore output signal Z3 becomes 1.
When both of the two input signals A3 and B3 are 1, both of the two PMOS transistors MP33 and MP34 are turned off and both of the two NMOS transistors MN31 and MN32 are turned on. Therefore output signal Z3 becomes 0.
The drain of PMOS transistor MP32 is connected to a NOR gate circuit NOR1. In NOR gate circuit NOR1, two PMOS transistors MP35 and MP36, which are supplied the power supply voltage VDD, are connected in series to form a pull-up circuit. The gate of PMOS transistor MP35 is supplied the inverted input signal /A3, and the gate of PMOS transistor MP36 is supplied the inverted input signal /B3. Two NMOS transistors MN33 and MN34 are connected in parallel between the drain of PMOS transistor MP36 and the constant current source 10 to form a pull-down circuit. The gate of NMOS transistor MN33 is supplied the inverted input signal /A3, and the gate of NMOS transistor MN34 is supplied the inverted input signal /B3. The sources of the two NMOS transistors MN33 and MN34 are connected to each other to form a common node. This common node and the source of NMOS transistor MN32 are connected to the constant current source 10.
When at least one of the two input signals A3 and B3 is 0, at least one of the two inverted input signals /A3 and /B3 is 1 and at least one of the two PMOS transistors MP35 and MP36 is turned off. Also, at least one of the two NMOS transistors MN33 and MN34 is turned on. Therefore output signal /Z3 becomes 0. When both of the input signals A3 and B3 are 1, both of the inverted input signals /A3 and /B3 are 0 and both of the PMOS transistors MP35 and MP36 are turned on. Also, the two NMOS transistors MN33 and MN34 are turned off. Therefore output signal /Z3 becomes 1.
In the above description, the voltage level of two logic values 1 and 0 is determined by the current driving capabilities of PMOS transistors MP31 and MP32 and constant current source 10. When one or both of the two PMOS transistors MP33 and MP34 are turned on, the highest voltage level of output signal Z3 is determined by the current driving capability of PMOS transistor MP31. Therefore, it is possible to establish a desired highest voltage level of output signal Z3 by appropriately designing the current driving capability of PMOS transistor MP31.
When both NMOS transistors MN31 and MN32 are turned on, the lowest voltage level of output signal Z3 is determined by the current driving capability of constant current source 10. Therefore, it is possible to establish a desired lowest voltage level by appropriately designing the current driving capability of constant current source 10.
In the differential mode NAND/NOR gates according to the present invention, operation speed is improved and power consumption is reduced by, preferably, reducing the swing width of output signals Z3 and /Z3. This is accomplished by appropriately designing the current driving capabilities of PMOS transistors MP31 and MP32 and constant current source 10.
If the current driving capability of each PMOS transistor MP31 and MP32 and constant current source 10 is small, the current driving capability of each MOS transistor, of which NAND and NOR gate circuits NAND1 and NOR1 consist, does not have to be increased. Therefore, the current driving capability can be designed in such a way that the respective current driving capabilities of PMOS transistors MP31 and MP32, NAND gate circuit NAND1 and NOR gate circuit NOR1 are all the same, under the circumstance that the difference of mobility of each carrier of PMOS and NMOS transistors is sufficiently considered.
The fact that the current driving capabilities of MOS transistors in the NAND and NOR gate circuits NAND1 and NOR1 are the same as that of PMOS transistors MP31 and MP32 and constant current source 10 means that the voltage range of input signals A3, B3, /A3 and /B3 may be the same as that of output signals Z3 and /Z3. Therefore, when a circuit is designed using a plurality of differential mode NAND/NOR gates according to the present invention, matching the characteristics of input and output signals becomes a lesser concern.
FIGS. 4A-4F compare input/output signals of differential mode NAND/NOR gates of FIG. 3C with input/output signals of the NAND gate of FIG. 1C. FIGS. 4A and 4B are inputs of two-bit logic signals of the related art. FIG. 4C is a result of the NAND operation of FIG. 1C. As shown in FIGS. 4A to 4C, in a related art NAND gate, both input and output signals fully swing between the power supply source VDD and the ground voltage VSS. However, corresponding input and output signals of FIGS. 4D to 4F according to the present invention have a highest value which is less than the power supply voltage VDD, and a lowest value which is more than the ground voltage VSS. Therefore, a logic transition is carried out rapidly, and a higher operating speed is obtained accordingly.
FIGS. 5A to 5C are a logic symbol, truth table and circuit, respectively, of another embodiment of differential mode NAND/NOR gates in accordance with the present invention.
In FIG. 5A, A3 and B3 are input signals, and Z4 and /Z4 are output signals, which are complementary. Output signal Z4 is a result of NOR operation on the two input signals A3, B3, and output signal /Z4 is a result of an OR operation.
That is, as shown in FIG. 5B, when at least one of the two input signals A3, B3 is 1, output signal Z4 becomes 0, while when both are 0, output signal Z4 becomes 1. Furthermore, when at least one of the two input signals A3, B3 is 1, output signal /Z4 becomes 1, while when both are 0, output signal /Z4 becomes 0.
As shown in FIG. 5C, the structure of the differential mode NAND/NOR gates in accordance with this embodiment of the present invention is the same as that shown in FIG. 3C, except that the input signals A3 and B3 and the inverted input signals /A3 and /B3 have been applied differently. Namely, input signals A3 and B3 have been applied to PMOS transistor MP35 and PMOS transistor MP36, respectively, and also applied to the NMOS transistors MN33 and MN34, respectively. The inverted input signals /A3 and /B3 have been applied to the PMOS transistor 33 and PMOS transistor 34, respectively, and also applied to the NMOS transistor MN31 and the NMOS transistor MN32, respectively. Because the structure is the same, except for the differently applied input signals, the operation thereof will not be described in detail.
FIG. 6 shows another embodiment of the differential mode NAND/NOR gates according to the present invention, which is identical with FIG. 3C except that the gates of the two PMOS transistors MP31, MP32 are supplied a bias voltage VBIAS. Applying bias voltage VBIAS to transistors MP31, MP32 allows one to adjust the highest voltage level in the case that the output signals Z3, /Z3 are 1, by controlling the bias voltage VBIAS. If bias voltage VBIAS is increased, the highest voltage level is increased accordingly, while if the bias voltage VBIAS is decreased, the highest voltage level is also decreased. This means that the swing width of output signals is variable.
In the differential mode NAND/NOR gates according to the present invention input and output signals swing within a narrow range, thereby a higher-speed operation can be obtained, as well as lower power consumption.
Secondly, a stable output signal is generated regardless of variations in power supply voltage, and therefore, the induced noise is considerably improved.
Thirdly, it is possible that all of the MOS transistors, which constitute the differential mode NAND/NOR gates according to the present invention, have the same current driving capability, thereby the manufacturing process for determining the same current driving capability can be simplified.
Finally, in making a programmable gate array using the differential mode NAND/NOR gates of the present invention, it is possible to obtain two different results from one gate, thereby the number of devices can be reduced. As a result, the chip size can be reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made in a differential mode NAND/NOR gates of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Patent | Priority | Assignee | Title |
| 6731136, | Nov 01 2001 | Hewlett Packard Enterprise Development LP | Differential CMOS logic with dynamic bias |
| 6882179, | Nov 01 2001 | Hewlett-Packard Development Company, L.P. | Differential CMOS logic with dynamic bias |
| 7088162, | Sep 07 2001 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Circuit generating constant narrow-pulse-width bipolarity monocycles |
| 9024653, | Oct 30 2012 | Samsung Electro-Mechanics Co., Ltd. | Input buffer circuit |
| Patent | Priority | Assignee | Title |
| 5149992, | Apr 30 1991 | STATE OF OREGON ACTING BY AND THROUGH THE STATE BOARD OF HIGHER EDUCATION ON BEHALF OF OREGON STATE UNIVERSITY, THE | MOS folded source-coupled logic |
| 5179358, | Mar 04 1992 | MOTOROLA SOLUTIONS, INC | Circuit, counter and frequency synthesizer with adjustable bias current |
| 5218246, | Sep 14 1990 | ALI CORPORATION | MOS analog XOR amplifier |
| 5254891, | Apr 20 1992 | International Business Machines Corporation | BICMOS ECL circuit suitable for delay regulation |
| 5568073, | Dec 22 1993 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Data comparing sense amplifier |
| 5583456, | Aug 25 1994 | NEC Corporation | Differentially coupled AND/NAND and XOR/XNOR circuitry |
| 5592107, | Jun 30 1995 | VIA-Cyrix, Inc | Configurable NAND/NOR element |
| 5610539, | Jun 16 1993 | NXP B V | Logic family for low voltage high-speed applications |
| 5920205, | May 31 1996 | Loading element for a logic gate |
| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Mar 11 1999 | RA, YOUN-WOOK | LG SEMICON CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009899 | /0172 | |
| Apr 12 1999 | Hyundai Electronics Industries, Co., Ltd. | (assignment on the face of the patent) | / | |||
| Jul 26 1999 | LG SEMICON CO , LTD | HYUNDAI MICROELECTRONICS CO , LTD | CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY AND EXECUTION DATE PREVIOUSLY RECORDED ON REEL 011454 FRAME 0287 ASSIGNOR S HEREBY CONFIRMS THE RECEIVING PARTY IS HYUNDAI MICROELECTRONICS CO , LTD AND EXECUTION DATE IS 07 26 1999 | 022708 | /0872 | |
| Oct 14 1999 | HYUNDAI MICRO ELECTRONICS CO , LTD | HYUNDAI ELECTRONICS INDUSTRIES CO , LTD | MERGER SEE DOCUMENT FOR DETAILS | 022742 | /0478 | |
| Oct 14 1999 | HYUNDAI MICRO ELECTRONICS CO , LTD | HYUNDAI ELECTRONICS INDUSTRIES CO , LTD | CORRECTIVE ASSIGNMENT TO CORRECT THE COUNTRY IN THE ADDRESS OF THE RECEIVING PARTY PREVIOUSLY RECORDED ON REEL 022742 FRAME 0478 ASSIGNOR S HEREBY CONFIRMS THE COUNTRY SHOULD BE REPUBLIC OF KOREA | 022746 | /0279 | |
| May 30 2000 | LG SEMICON CO , LTD | HYUNDAI ELECTRONICS INDUSTRIES CO , LTD | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 011454 | /0287 | |
| Mar 29 2001 | HYUNDAI ELECTRONICS INDUSTRIES CO , LTD | Hynix Semiconductor Inc | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 015242 | /0899 | |
| Oct 04 2004 | Hynix Semiconductor, Inc | MagnaChip Semiconductor, Ltd | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 016216 | /0649 | |
| Dec 23 2004 | MagnaChip Semiconductor, Ltd | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 016470 | /0530 | |
| May 14 2009 | MagnaChip Semiconductor, Ltd | Crosstek Capital, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 022764 | /0270 | |
| May 27 2009 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE | MagnaChip Semiconductor, Ltd | PARTIAL RELEASE OF SECURITY INTEREST | 022746 | /0870 | |
| Aug 12 2009 | Crosstek Capital, LLC | CHIAO TUNG HOLDINGS, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023085 | /0864 | |
| Nov 26 2019 | CHIAO TUNG HOLDINGS, LLC | INTELLECTUAL VENTURES ASSETS 158 LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 051777 | /0081 | |
| Dec 06 2019 | INTELLECTUAL VENTURES ASSETS 158 LLC | HANGER SOLUTIONS, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 051486 | /0425 |
| Date | Maintenance Fee Events |
| Apr 10 2002 | ASPN: Payor Number Assigned. |
| Sep 22 2004 | M1551: Payment of Maintenance Fee, 4th Year, Large Entity. |
| Sep 24 2008 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
| Feb 23 2010 | ASPN: Payor Number Assigned. |
| Feb 23 2010 | RMPN: Payer Number De-assigned. |
| Oct 04 2012 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
| Date | Maintenance Schedule |
| May 01 2004 | 4 years fee payment window open |
| Nov 01 2004 | 6 months grace period start (w surcharge) |
| May 01 2005 | patent expiry (for year 4) |
| May 01 2007 | 2 years to revive unintentionally abandoned end. (for year 4) |
| May 01 2008 | 8 years fee payment window open |
| Nov 01 2008 | 6 months grace period start (w surcharge) |
| May 01 2009 | patent expiry (for year 8) |
| May 01 2011 | 2 years to revive unintentionally abandoned end. (for year 8) |
| May 01 2012 | 12 years fee payment window open |
| Nov 01 2012 | 6 months grace period start (w surcharge) |
| May 01 2013 | patent expiry (for year 12) |
| May 01 2015 | 2 years to revive unintentionally abandoned end. (for year 12) |